COMLINEAR CORP S9E D MM 2279101 00011495 770 MICMN QO io Comlinear Ultra Low Noises CL worporaion _ Wideband Op Amp ee ee. wel cae A et baka 3 APPLICATIONS: FEATURES (typical): = Fa 7 Fe 2 Lb ~ 10 instrumentation sense amplifiers 1.7GHz gain-bandwidth ordduct ultrasound pre-amps 1.05nV/VHz input voltage noise * magnetic tape & disk pre-amps 1.6pA/VHz input current noise photo-diode transimpedance amplifiers 100pV input offset voltage, 24V/C drift e wide band active filters 350V/us slew rate e low noise figure RF amplifiers 15m<A to 5mA adjustable supply current professional audio systems * gain range +10 to +1,000V/V e low-noise loop filters for PLLs evaluation board and simulation macromodel DESCRIPTION The CLC425 combines a wide bandwidth (1.7GHz GBW) with very low input noise (1.05nV/VHz, 1.6pA/VHz) and low de errors (100,1V vos, 2uV/C drift) to provide a very precise, wide dynamic- range op amp offering closed-loop gains of 210. Singularly suited for very wideband high-gain operation, the CLC425 employs a traditional voltage-feedback topology providing all the benefits of balanced inputs, such as low offsets and drifts, as well as a 96dB open-loop gain, a 100dB CMRR and a 95dB PSRR. The CLC425 also offers great flexibility with its externally adjust- able supply current, allowing designers to easily choose the : 1.05nV/VHz optimum set of power, bandwidth, noise and distortion perfor- mance. Operating from +5V power supplies, the CLC 425 defaults to a 15mA quiescent current, or by adding one external resistor, the supply current can be adjusted to less than 5mA. The CLC425's combination of ultra-low noise, wide gain-band- NC = 7 TB] Rp (optionay width, high slew rate and low de errors will enable applications in View 7] Vex areas such as medical diagnostic ultrasound, magnetic tape & Vaoninw = re] Ve disk storage, communications and opto-electronics to achieve VIG SNe maximum high-frequency signal-to-noise ratios. The CLC425 is avaitable in the following versions. Chip Topography CLO425AJP - -40C to +85C = 8-pin PDIP Rp Thickness is 0.044in, CLO425AJE -40C to +85C 8-pin SOIC Vinw Veo Note: Backside CLC425AIB -40C to +85C = 88-pin CerDIP Vnon-inw Seta tis CLC425A8B = -85C to +125C ~8-pin CerDIP, MIL-STD-883 Level B o.09s electrically connect CLO425A8L-2 -85C to +125C =. 20-pin LCC, MIL-STD-883 Level B the backside to the CLO425ALC -55C to +125C dice cae Contact CLO425AMC = 55C to +125C ~ dice, MIL-STD-883 Level B v Ven factory for more Moe cu informati Contact factory for other packages and DESC SMD number. } 0.039" J information. Package Dimensions 1402090 - 0.050 mf 076-12) S| weap Goss oli aaa bod o22-000 en Tee a = (559-787) HO 88 0.220 ~0.280 q 0300-0226 180-1025) pois-o00 Pat qT eon 82-Bae) ay 38-18) abs) i 8m 0.015 -0.050 bea ts9 |, om ca aan JES Tao to DIS ~ (9.40 - 11.68) L 0n60~ 0.080 18-5.) 2 _ | 0.060 BSC. (099-127) To.145-0200 T (27-203) ae alle Haast fe 4 4 88-508) 0.00 BSC cue 0008-0018 p59. ene 0004-0010 oxmonsa | 0.290 oai0 gove-oees (254886) (020-0046) (135-135) Too Gy s-e2 220 r seta yeaa Pes a ed em 0.000~ 0.110 (1.37850) 0.015 - 0.060 (228-279) (040-127) 8-pin plastic DIP 8-pin CERDIP 8-pin plastic SOIC Comlinear Corporation 4800 Wheaton Drive FortCollins,CO80525 (303)226-0500 FAX (303) 226-0564 DS425.01 (introductory) January 1993 3-109COMLINEAR CORP S9E D) MM 2279101 0003150 492 mCHN SS AG : : ce Pocus S a I o e PARAMETERS CONDITIONS TYP MIN AND MAX RATINGS UNITS SYMBOL Ambient Temperature CLC425 AJ/AI +25C -40C +25C +85C Ambient Temperature CLC425 A8/AM/AL +25C 55C +25C +125C FREQUENCY DOMAIN RESPONSE gain bandwidth product Vout < 0.4Vop 1.7 GHz GBW +-3dB bandwidth . Vour< 0.4 Vp, 85 TBD TBD TBD MHz SSBW . Vou < 5-OVep TBD TBD TBD TBD MHz LSBW gain flatness Vou < 0.4V op t peaking DC to 30MHz 0.3 TBD TBD TBD dB GFP t rolloff DC to 30MHz 0.1 TBD TBD TBD || dB GFR linear phase deviation DC to 30MHz TBD TBD TBD TBD LPD TIME DOMAIN RESPONSE rise and fall time 0.4V step 44 TBD TBD TBD ns TRS settling time to 0.1% 2V step 22 TBD TBD TBD ns TSS overshoot 0.4V step 5 TBD TBD TBD % Os slew rate 2V step 350 TBD TBD TBD Vits SR DISTORTION AND NOISE RESPONSE t2 harmonic distortion 1Vip, 1OMHz - 50 TBD TBD TBD || dBc HD2 +3" harmonic distortion 1Vpp, 10MHz - 80 TBD TBD TBD || dBc HD3 3" order intermodulation intercept 1OMHz2 35 dBm IMD 1/f input voltage noise corner 500 Hz V/F equivalent noise input voltage TBD to 100MHz 1.05 TBD TBD TBD nVAHz |VN current TBD to 100MHz 1.6 TBD TBD TBD || pAWHz jICN noise floor TBD to 100MHz - 165 TBD TBD TBD dBmyy. |SNF integrated noise TBD to 100MHz 12 TBD TBD TBD || uV INV STATIC DC PERFORMANCE open-loop gain DG 96 77 86 86 dB AOL *input offset voltage +100 +1000 | +800 +1000 |] pV VIO average drift +2 8 4 pvPC [DVIO *input bias current 12 34 20 20 HA IB average drift ~ 100 - 250 _ - 120 nAfrc DIB input offset current 40.2 3.4 2.0 2.0 pA Ilo average drift +3 +50 _ +25 nArc DIO tpower supply rejection ratio bc 95 82 88 88 dB PSRR acommon mode rejection ratio DC 100 88 92 92 dB CMRR *supply current Ry = 15 18 16 16 mA ICC MISCELLANEOUS PERFORMANCE input resistance common-mode 2 0.6 1.6 1.6 MQ RINC differential-mode 6 1 3 3 kQ RIND input capacitance common-mode 2.5 3 3 3 pF CINC ouiput resistance closed loop 5 50 10 10 mQ ROUT output voltage range Ri= co +3.8 43.5 3.7 3.7 Vv VO R,=100Q 43.4 +28 3.2 +3.2 v VOL input voltage range common mode 3.8 34 35 3.5 v CMIR output current source -65C/-40C 90 60/70 | 70 70 mA IOP sink -55C/-40C 90 40/55 | 55 55 mA ION I short circuit protected to ground, however maximum reliabiliy is obtained if I,,, does not exceed... common-mode input voltage differential input current maximum junction temperature operating temperature range AJ/Al A8/ AM/AL: storage temperature range lead temperature (soldering 10 sec) diode protected 150mA tV., +25mA +175C -40C to +85C -55C to +125C -65C to +150C +300C : 100% tested at +25C, sample at +85C. : Sample tested at +25C. : 100% tested at +25C, : 100% tested at +25C, -56C, +125C. : 100% tested at +25C, sample at -55C, +125C : 100% wafer probed +25C to +25C min/max specs. : Sample tested at +25C, -55C and +125C. Comlinear reserves the right to change specifications without notice.Frequency Response vs. G2vO19 Magnitude (1dB/div) Magnitude (1dB/div) SHG 10 Frequency (MHz) nd Phase vs. | meer seneenee Open Loop Gain (dB) 100k 1 Frequency (Hz) Frequency Response for Various R & : : . 10k TOM Magnitude (1dB/div} Magnitude (1dB/div) = 3 a 3 s @ 3 3 e a xs = Voltage Noise (nVAHz) 20log|Zo| Output Swing (Vpp) ome MO Oh Dn DO SG 100. tk 10k~~100k. Frequency (Hz) Differential Input Impedance 100 fesse serra he & CMRR (dB) 20log|Zincul 200g [Zinginl ee = ees oe 2 1 2 3 4 10 100 1k 10k 100k 1M 40 100 1k 10k 100k 1M 10M 100M 1G Voltage (V) Frequency (Hz) Frequency (Hz) 3-111COMLINEAR CORP ee oomas ay silicate Pulse Response (Vo=1Vpp) es an oS Output Voltage (0.2V/div) 5ns/div Short Term Settling Time 02 i a 0.15 ke co aS o ef a m csc ain rence Settling Error(%) e ~S nn oo ee 20 = = 10 . 5 2 : = 1 3 a on : SES : - a. 08 35 -40 45 ~@ 50 a 3-55 = 2 -60 8-65 2 -70 75 -80 65 1 50 10 Frequency (MHz) Output Voltage vs Load 5 k = > o 23 s > 3 Q 3 36 30 100 Load, Ri (2) SIE DD MCNN ue . SER asst Large SI Settling Tim as 00 & ae ECA RE 20 30 40 50 60 7 Gain (V/V) x 3 oo 402 > 50s = E - 3 $ = n jo* 10 4 Time (s) Gain-Bandwidth Product vs Ice 1.8 zr x Sg 3 314 Ss o 3 3S = ss 3 g a SS 2 10 S = 2 = 2 5 8 2 2 oS o 3 2 06 a 2 & a oO 02 oe oe 140613 12 1 109 #8 7 6 4 3 Supply Current, Ice (mA) istortion vs. Gain & lec (Vo=1 Vp; fo=3MH2) 40 eet ees sel otectentenctns oe Distortion (dBc) Intercept Point (+dBm) 1M Frequency (Hz) Ical DC Errors vs. Tempe Types DC ror ve. Temp Gain (V/V) CMRR and PSAR Sr oe a z e > & 100 = ' e = = 1 5 g ! ao = 2 2 s @ a & FE 3 = 5 g 50 30 Fr Z Z a = = a { Oo! 50 Frequency (Hz} Temperature (C) 3-112COMLINEAR CORP Rs Vs Rr Fiseq = Rs || Rr a14 ft Ay=1+ Re Figure 1: Non-inverting Amplifier Configuration Introduction The CLC425 is a very wide gain-bandwidith, ultra-low noise voltage feedback operational amplifier which en- ables application areas such as medical diagnostic ultra- sound, magnetic tape & disk storage and fiber-optics to achieve maximum high-frequency signal-to-noise ratios. The set of characteristic plots located in the "Typical Performance" section illustrates many of the perfor- mance trade-offs. The following discussion will enable the proper selection of external components in order to achieve optimum device performance. Bias Current Cancellation In order to cancel the bias current errors of the non- inverting configuration, the parallel combination of the gain-setting (R,) and feedback (R,) resistors should equal the equivalent source resistance (R,,,) as defined in Figure 1. Combining this constraint with the non-inverting gain equation also seen in Figure 1, allows both R;and R, to be determined explicitly from the following equations: R=AR,,, and Rg=R/(A,-1). When driven from a 0Q source, such as that from the output of an op amp, the non-inverting input of the CLC425 should be isolated with at least a 25Q series resistor. As seen in Figure 2, bias current cancellation is accom- plished for the inverting configuration by placing a resis- tor (R,) on the non-inverting input equal in value to the resistance seen by the inverting input (Ri|{(Rg+R,)). Rp is recommended to be no less than 25Q for best CLC425 performance. The additional noise contribution of R,can be minimized through the use of a shunt capacitor. +Voc 6.8nF Rs Vs Figure 2: Inverting Amplifier Configuration S9E D MM 2279101 00013153 171 MCMN Total Input Noise vs. Source Resistance Inorder to determine maximum signal-to-noise ratios from the CLC425, an understanding of the interaction between the amplifier's intrinsic noise sources and the noise arising from its external resistors is necessary. Figure 3 describes the noise model for the non-inverting amplifier configuration showing all noise sources. In addi- tion to the intrinsic input voltage noise (e,) and current noise (i,=i,,=i,.) sources, there also exists thermal voltage noise (e,=./4kTR ) associated with each of the external . resistors. Equation 1 provides the general form for total equivalent input voltage noise density (e,;). Equation 2 is asimplification of Equation 1 that assumes Rij|R, = Rs,, for 4kT =16.4e -21 Joules @ 25C Figure 3: Non-inverting Amplifer Noise Model 2 | 2 . 2 ey, = {e +[ineRy,,) +44IR,, +(i,_(R,UR,)) +447(R,lIR,) Equation 1: General Noise Equation bias current cancellation. Figure 4 illustrates the equiva- lent noise model using this assumption. Figure 5 is a plot of e, against equivalent source resistance (R.,,) with all of the contributing voltage noise sources of Equation 2 shown. This plot gives the expected e,; for a given R,,, which assumes P,||Rg = R,,, for bias current cancellation. The total equivaient output voltage noise (no) iS enr*Ay. Figure 4: Noise Model with Rif[Ry = Reeg e, =e? +2(i,R,,) +4k7(2R,, ) Equation 2: Noise Equation with Ril[Ry = Rsoq 3-113 Gevo19COMLINEAR CORP Asseenin Figure 5, ,,is dominated by the intrinsic voltage noise (e,) ofthe amplifier for equivalent source resistances below 33.5Q. Between 33.50 and 6.43kQ, e,; is domi- nated by the thermal noise (e,=./4kTRseq) of the external resistors. Above 6.43kQ, e,;is dominated by the amplifier's current noise (V/2i,R,,,,). The point at which the CLC425's voltage noise and current noise contribute equally occurs for Fg.g=464Q (i.e. e, /J/2i,). AS an example, configured with a gain of +20V/V giving a -3dB of 90MHz and driven from an Rs,,=25, the CLC425 produces a total equivalent input noise voltage (,,+1-57#90MHz ) Of 16.5Vins, Voltage Noise Density (nV/VFAz) 10 100 1k 10k 100k Equivalent Source Resistance, Rseq (2) Figure 5: Voltage Noise Density vs. Source Resistance ifbias current cancellation is nota requirement, then R,||R, does not need to equal R,,,. In this case, according to Equation 1, R,|/R, should be as low as possible in order to minimize noise. Results similar to Equation 1 are obtained for the inverting configuration of Figure 2 if R,,,,is replaced by R, and R, is replaced by R,+R,. With these substitu- tions, Equation 1 will yield an e,, refered to the non- inverting input. Refering e,; to the inverting input is easily accomplished by multiplying e,; by the ratio of non-invert- ing to inverting gains. Noise Figure Noise Figure (NF) can be defined as the ratio of the total output noise power (,,) to that portion of output noise power caused by the source resistance (e,*A,) and is so expressed in Equation 3. This definition assumes an unterminated source and that the parallel combination of R, and R, is chosen to equal to R, for bias current cancellation. The curve labeled "Unterminated in Figure 6 is a plot of NF vs. R, and for a 50Q source the CLC425's NF is 5.26dB. 2 Wi 2 NF <10 oe +2(,R,) ie AkTR, Equation 3: Noise Figure Equation for Unterminated Source Adding amatching termination resistor (Ry, Figure 1) tothe CLC425's input will result in a higher measured Noise Figure as seen by the curve labeled "Terminated". Noise Figure can also be defined as the ratio of the source's SNR tothe amplifier's SNR. Therefore, even though the thermal SSE D MM 2279101 0003154 038 Noise Figure (dB) ik 10k 100k Source Resistance, Rs (Q) Figure 6: Noise Figure vs. Source Resistance noise power contribution of all the external resistors is diminished by 1 (i.e. Ry||FRy = Rs||[Rr = 12R,), the addition of the matching termination resistor as a part of the amplifier also cuts the input signal amplitude by such that the amplifier's SNR is reduced and the resulting Noise Figure is highr as shown in the plot. From the curve labeled "Terminated", the CLC425 configured with a 50 match- ing termination resistor (R;) driven from the same 50Q (R,) source used above, yields a NF of 9.72dB. As seen from the two curves, the difference is negligible with very high source resistances where the currentnoise of the amplifier becomes the dominant factor. For more information re- garding Noise Figure, see OA-11. Supply Current Adjustment The CLC425's supply current can be externally adjusted downward from its nominal value by adding an optional resistor (Rp) between pin 8 and the negative supply as shownin Figure 7. Several of the plots found within the piot pages demonstrate the CLC425s behavior at different supply currents. The plot labeled I,, vs. R, provides the means for selecting R, and shows the result of standard IC process variation which is bounded by the 25C curve. Figure 7: External Supply Current Adjustment Non-Inverting Gains Less Than 10V/V Using the CLC425 at lower non-inverting gains requires external compensation such as the shunt compensation as shown in Figure 8. The quiescent supply current must also be reduced to 5mA with R, for stability. The compen- sation capacitors are chosen to reduce frequency re- sponse peaking to less than 1dB. The plot in the "Typical Performance section labeled Differential Gain and Phase shows the video performance of the CLC425 with this compensation circuitry. 3-114 MECMNNAe ne COMLINEAR CORP 78Q 750 Figure 8: External Shunt Compensation Inverting Gains Less Than 10V/V The lag compensation of Figure 9 will achieve stability for lower gains. Placing the network between the two input terminals does not affect the closed-loop nor noise gain, but is best used for the invering configuration because of its affect on the non-inverting input impedance. Vin Rg Rr Vout c Rout Ri Rp Figure 9: External Lag Compensation Single-Supply Operation The CLC425 can be operated with single power supply as shown iin Figure 10. Both the input and output are capaci- tively coupled to set the dc operating point. Veo co =Vge + Avec C Rout RL Figure 10: Single Supply Operation Low Noise Transimpedance Amplifier The circuit of Figure 11 implements a low-noise transimpedance amplifier commonly used with photo- diodes. The transimpedance gain is set by R,. The simu- lated frequency response is shown in Figure 12 and shows the influence C, has over gain flatness. Equation 4 pro- vides the total input current noise density (i,,) equation for the basic transimpedance configuration and is plotted against feedback resistance (R,) showing all contributing noise sources in Figure 13. This plot indicates the ex- pected total equivalent input current noise density (i,;) for a given feedback resistance (R,). The total equivalent output voltage noise density (e,.) is iy*R,. SSE D MM 2279101 00013155 T?74 MECHN Cy +Voe 6 W Rb A, = 1,,*R, Figure 11: Transimpedance Amplifier Configuration 70 Gain (dB) P| 1M 10M 100M 1G Frequency (Hz) Figure 12: Transimpedance Amplifier Frequency Response Current Noise Density (pA/VHZz) Feedback Resistance, Rr(Q) Figure 13: Current Noise Density vs. Feedback Resistance Equation 4: Total Equivalent Input Refered Current Noise Density Very Low Noise Figure Amplifier The circuit of Figure 14 implements a very low Noise Figure amplifier using a step-up transformer combined with a CLC425 and a CLC404. The circuit is configured with a gain of 35.6dB. The circuit achieves measured Noise Figures of less than 2.5dB in the 10-40MHz region. 3" order intercepts exceed +30dBm for frequencies less than 40MHz and gain flatness of 0.5dB is measured in the 1-50MHz pass bands. Application Note OA-14 provides greater detail on these low Noise Figure techniques. 3-115 S2v019COMLINEAR CORP 40kQ. son Pe Mint-Circults T16-6F Gain = Po = 35.6dB Pi Figure 14: Very Low Noise Figure Amplifier Low Noise Integrator The CLC425 implements a deBoo integrator shown in Figure 15. Integration linearity is maintained through posi- tive feedback. The GLC-425's low input offset voltage and matched inputs allowing bias current cancellation provide for very precise integration. Stability is maintained through the constraint on the circuit elements. Figure 15: Low Noise Integrator High-Gain Sallen-Key Active Filters The CLC425 is well suited for high-gain Sallen-Key type of active filters. Figure 16 shows the 2 order Sallen-Key low pass filter topology. Using component predistortion meth- ods as discussed in OA-21 enables the proper selection of components for these high-frequency filters. C1 If i Ri Re oh bt Co | Rr Rg V7 Figure 16: Sallen-Key Active Filter Topology Low Noise Magnetic Media Equalizer The CLC425 implements a high-performance low-noise equalizer for such applications as magnetic tape channels as shown in Figure 17. The circuit combines an integrator with a bandpass filter to produce the low-noise equal- ization. The circuit's simulated frequency response is illustrated in Figure 18. SSE D M@@ 2279101 0001156 900 MCMN Vin R= 6812 of Vo Ri = 45.30 ao Cy = 2200pF t Re = 2000 L Rg = 50Q Ry = 1kQ R L=01H C = 470pF Ko=1+ R, v, R, _\ SLR, sC,R, +1 eK, - hn sC,(R, + R)+1 x R, +R, }s?LCR,R, + sL{R, +R, )+2R, Figure 17: Low Noise Magnetic Media Equalizer Gain (dB) 10k 100k 1M 10M Frequency (Hz) Figure 18: Equalizer Frequency Response Low-Noise Phase-Locked Loop Filter The CLC425 is extremely useful as a Phase-Locked Loop filter in such applications as frequency synthesizers and data synchronizers. The circuit of Figure 19 implements one possible PLL filter with the CLC425. Ry Cr tS Vin Ry Vout Ro 7 Figure 19: Phased-Locked Loop Filter Decreasing the Input Noise Voltage The input noise voltage of the CLC425 can be reduced from its already low 1.05nV/./Hz by slightly increasing the supply current. Using a 50kQ resistor to ground on pin 8, as shown in the circuit of Figure 14, will increase the quiescent current to =17mA and reduce the input noise voltage to < 0.95nV/Hz. Printed Circuit Board Layout Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and pos- sible circuit oscillation, see OA-15 for more information. Comlinear suggests the 730013 Evaluation Board both as a guide for high-frequency layout and as an aid in device testing and characterization. 3-116