To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS Integrated Circuit V850ES/FG2 32-bit single-chip micro controller INTRODUCTION The V850ES/FG2 are 32-bit single-chip microcontrollers that include the V850ES CPU core and integrate peripheral functions such as timers/counters, serial interfaces, and an A/D converter. These microcontrollers also incorporate a CAN (Controller Area Network) as an automotive LAN. In addition to highly real-time responsive, 1-clock-pitch basic instructions, these microcontrollers have instructions ideal for digital servo applications, such as multiplication instructions using a hardware multiplier, sum-of-products operation instructions, and bit manipulation instructions. These microcontrollers can also realize a real-time control system that is highly cost effective and can be used in automotive instrumentation fields. FEATURES - Number of instructions: 83 - Minimum instruction execution time: 50 ns (main clock (fxx) = 20 MHz) - General-purpose registers: 32 bits x 32 - Power-on clear function - Low-voltage detection function - Ring-OSC: 200 kHz (TYP.) - Internal memory: - RAM: 6/12/16 KB - Flash memory: 256/384KB - Mask ROM: 128/256KB - Interrupts/exceptions : - Non-maskable interrupts : 1 source - Maskable interrupts : 61 sources - Software exceptions: 2 sources - Exception trap: 1 source - I/O lines I/O ports: 84 - Timer/counters: - 16-bit interval timer M (TMM): 1 ch - 16-bit timer/event counter P (TMP): 4 ch - 16-bit timer/event counter Q (TMQ): 2 ch - Watch timer: 1 ch - Watchdog timer 2: 1 ch - Serial interface (SIO): - Asynchronous serial interface A (UART): 3 ch - 3-wire variable-length serial interface B (CSIB): 2 ch - CAN controller: 2 ch - A/D converter 10-bit resolution: 16 ch - Clock generator Main clock/subclock operation: - CPU clock in seven steps (fxx, fxx/2, fxx/4, fxx/8, fxx/16, fxx/32, fxt) - Clock-through mode/PLL mode selectable - Internal oscillator: 200 kHzTYP. - Power save function: HALT/IDLE1/IDLE2/software STOP/subclock/sub-IDLE modes - Package: 100-pin plastic LQFP (fine pitch) (14 x 14) Part Number Internal ROM Internal RAM CAN I/F uPD703234 128KB (Mask ROM) 6KB 2 channel uPD703235 256KB (Mask ROM) 12KB 2 channel UPD70F3234 128KB (Flash) 6KB 2 channel uPD70F3235 256KB (Flash) 12KB 2 channel uPD70F3236 384KB (Flash) 16KB 2 channel DATA SHEET U17832EE1V0DS00 1 V850ES/FG2 Table of Contents 1. Electrical Specifications........................................................................................................................................... 4 1.1 Electrical Specifications of (A)-Grade ................................................................................................................ 4 1.1.1 Absolute maximum ratings .......................................................................................................................... 4 1.1.2 Capacitance ................................................................................................................................................ 8 1.1.3 Operating conditions ................................................................................................................................... 8 1.1.4 Oscillator Characteristics ............................................................................................................................ 9 1.1.5 PLL Characteristics ................................................................................................................................... 11 1.1.6 Ring-OSC Characteristics ......................................................................................................................... 11 1.1.7 Voltage Regulator Characteristics ............................................................................................................. 11 1.1.8 DC Characteristics .................................................................................................................................... 12 1.1.9 Data Retention Characteristics ................................................................................................................. 16 1.1.10 AC Characteristics .................................................................................................................................. 17 1.2 Electrical Specifications of (A1)-Grade ............................................................................................................ 28 1.2.1 Absolute maximum ratings ........................................................................................................................ 28 1.2.2 Capacitance .............................................................................................................................................. 32 1.2.3 Operating conditions ................................................................................................................................. 32 1.2.4 Oscillator Characteristics .......................................................................................................................... 33 1.2.5 PLL Characteristics ................................................................................................................................... 35 1.2.6 Ring-OSC Characteristics ......................................................................................................................... 35 1.2.7 Voltage Regulator Characteristics ............................................................................................................. 35 1.2.8 DC Characteristics .................................................................................................................................... 36 1.2.9 Data Retention Characteristics ................................................................................................................. 40 1.2.10 AC Characteristics .................................................................................................................................. 41 1.3 Electrical Specifications of (A2)-Grade ............................................................................................................ 52 1.3.1 Absolute maximum ratings ........................................................................................................................ 52 1.3.2 Capacitance .............................................................................................................................................. 56 1.3.3 Operating conditions ................................................................................................................................. 56 1.3.4 Oscillator Characteristics .......................................................................................................................... 57 1.3.5 PLL Characteristics ................................................................................................................................... 59 1.3.6 Ring-OSC Characteristics ......................................................................................................................... 59 1.3.7 Voltage Regulator Characteristics ............................................................................................................. 59 1.3.8 DC Characteristics .................................................................................................................................... 60 1.3.9 Data Retention Characteristics ................................................................................................................. 64 1.3.10 AC Characteristics .................................................................................................................................. 65 2. Injected Current Specification................................................................................................................................ 76 2.1 Injected Current Specification of (A)-Grade ..................................................................................................... 76 2.1.1 Absolute Maximum Ratings ...................................................................................................................... 76 2.1.2 DC Characteristics for overload current .................................................................................................... 76 2.1.3 DC Characteristics for pins influenced by injected current on an adjacent pin .......................................... 77 2.1.4 A/D converter influenced by injected current on an adjacent pin............................................................... 78 2.2 Injected Current Specification of (A1)-Grade ................................................................................................... 79 2.2.1 Absolute Maximum Ratings ...................................................................................................................... 79 2.2.2 DC Characteristics for overload current .................................................................................................... 79 2.2.3 DC Characteristics for pins influenced by injected current on an adjacent pin .......................................... 80 2.2.4 A/D converter influenced by injected current on an adjacent pin............................................................... 81 2.3 Injected Current Specification of (A2)-Grade ................................................................................................... 82 2 DATA SHEET U17832EE1V0DS00 V850ES/FG2 2.3.1 Absolute Maximum Ratings .......................................................................................................................82 2.3.2 DC Characteristics for overload current .....................................................................................................82 2.3.3 DC Characteristics for pins influenced by injected current on an adjacent pin...........................................83 2.3.4 A/D converter influenced by injected current on an adjacent pin ...............................................................84 3. Package Drawings .................................................................................................................................................85 Figure 3-1: Package Drawing .................................................................................................................................85 4. Recommended Soldering Conditions.....................................................................................................................86 Table 4-1: Soldering Conditions..............................................................................................................................86 DATA SHEET U17832EE1V0DS00 3 V850ES/FG2 1. Electrical Specifications 1.1 Electrical Specifications of (A)-Grade Absolute maximum ratings 1.1.1 Absolute maximum ratings (TA = 25C): Flash memory products (1/2) Parameter Symbol Supply voltage Conditions Unit VDD VDD = EVDD = BVDD -0.5 to +6.5 V BVDD VDD = EVDD = BVDD -0.5 to +6.5 V EVDD VDD = EVDD = BVDD -0.5 to +6.5 V -0.5 to +6.5 V AVREF0 Input voltage Ratings VSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V AVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V BVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V EVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, V -0.5 to EVDD + 0.5 Note -0.5 to BVDD + 0.5 Note V P90 to P915, RESET, FLMD0 VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, V PDL0 to PDL13 VI3 Analog input voltage Note VIAN -0.5 to VRO + 0.5 X1, X2, XT1, XT2 Note -0.5 to AVREF0 + 0.5 P70 to P715 Note V V Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 4 DATA SHEET U17832EE1V0DS00 V850ES/FG2 Absolute maximum ratings (TA = 25C): Flash memory products (2/2) Parameter Symbol Output current, low Output current, high Operating ambient IOL IOH TA temperature Storage temperature Conditions Ratings Unit P00 to P06, P10, P11, P30 to P39, Per pin 4 mA P40 to P42, P50 to P55, P90 to P915 Total of all pins 50 mA P70 to P715 Per pin 4 mA Total of all pins 20 mA PCM0 to PCM3, PCS0, PCS1, PCT0, Per pin 4 mA PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins 50 mA P00 to P06, P10, P11, P30 to P39, Per pin -4 mA P40 to P42, P50 to P55, P90 to P915 Total of all pins -50 mA P70 to P715 Per pin -4 mA Total of all pins -20 mA PCM0 to PCM3, PCS0, PCS1, PCT0, Per pin -4 mA PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins -50 mA Normal operating mode -40 to +85 C Flash programming mode -40 to +85 C -40 to +125 C Tstg Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. DATA SHEET U17832EE1V0DS00 5 V850ES/FG2 Absolute maximum ratings (TA = 25C): Mask ROM products (1/2) Parameter Symbol Supply voltage Conditions Unit VDD VDD = EVDD = BVDD -0.5 to +6.5 V BVDD VDD = EVDD = BVDD -0.5 to +6.5 V EVDD VDD = EVDD = BVDD -0.5 to +6.5 V -0.5 to +6.5 V VSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V AVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V BVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V EVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 AVREF0 Input voltage Ratings VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, V -0.5 to EVDD + 0.5 Note -0.5 to BVDD + 0.5 Note V P90 to P915, RESET, IC VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, V PDL0 to PDL13 VI3 Analog input voltage Note VIAN -0.5 to VRO + 0.5 X1, X2, XT1, XT2 Note -0.5 to AVREF0 + 0.5 P70 to P715 Note V V Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 6 DATA SHEET U17832EE1V0DS00 V850ES/FG2 Absolute maximum ratings (TA = 25C): Mask ROM products (2/2) Parameter Symbol Output current, low Output current, high Operating ambient IOL IOH TA Conditions Ratings Unit P00 to P06, P10, P11, P30 to P39, Per pin 4 mA P40 to P42, P50 to P55, P90 to P915 Total of all pins 50 mA P70 to P715 Per pin 4 mA Total of all pins 20 mA PCM0 to PCM3, PCS0, PCS1, PCT0, Per pin 4 mA PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins 50 mA P00 to P06, P10, P11, P30 to P39, Per pin -4 mA P40 to P42, P50 to P55, P90 to P915 Total of all pins -50 mA P70 to P715 Per pin -4 mA Total of all pins -20 mA PCM0 to PCM3, PCS0, PCS1, PCT0, Per pin -4 mA PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins -50 mA -40 to +85 C -65 to +150 C Normal operating mode temperature Storage temperature Tstg Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. DATA SHEET U17832EE1V0DS00 7 V850ES/FG2 1.1.2 Capacitance (TA = 25C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V) Parameter I/O capacitance Symbol CIO Conditions MIN. TYP. fX = 1 MHz, MAX. Unit 10 pF Unmeasured pins returned to 0 V. 1.1.3 Operating conditions (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Internal system clock frequency Symbol fCLK Conditions MIN. REGC Capacity = 4.7 F, at operation with TYP. MAX. Unit 4 20 MHz 32 35 kHz main clock REGC Capacity = 4.7 F, at operation with subclock (crystal resonator) REGC Capacity = 4.7 F, at operation with 12.5 subclock (RC resonator) Note 8 The internal system clock frequency is half the oscillation frequency. DATA SHEET U17832EE1V0DS00 Note 27.5 Note kHz V850ES/FG2 1.1.4 Oscillator Characteristics Main clock oscillator characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Resonator Recommended Circuit Ceramic resonator Parameter Conditions MIN. Oscillation frequency Note 1 (fX) X1 4 X2 Oscillation Note 2 stabilization time TYP. Unit 5 MHz 16 After reset release After STOP mode MAX. 0.5 Note 3 2 /fX s Note 4 ms Note 4 ms release After IDLE2 mode 0.35 release Crystal Oscillation frequency Note 1 (fX) resonator Oscillation Note 2 stabilization time 4 MHz 16 After reset release After STOP mode 5 0.5 Note 3 2 /fX s Note 4 ms Note 4 s release After IDLE2 mode 350 release Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize the crystal resonator after reset or STOP mode is released. 3. Time required to stabilize access to the internal flash memory. 4. The value differs depending on the OSTS register settings. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. DATA SHEET U17832EE1V0DS00 9 V850ES/FG2 Subclock oscillator characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Resonator Recommended Circuit Crystal resonator XT1 Parameter Conditions Oscillation frequency Note 1 (fXT) XT2 MIN. TYP. MAX. Unit 32 32.768 35 kHz 10 s 55 kHz 100 s Note 5 R'1 QU C1' C2' RC resonator XT1 Oscillation Note 2 stabilization time XT2 Oscillation frequency Notes1, 4 (fXT) R = 390 k 5% C = 47 pF 10% Note 3 25 40 Note 3 Oscillation Note 2 stabilization time Notes 1. Indicates only oscillator characteristics. Refer to 27. 1. 10 AC Characteristics for CPU operating clock. 2. Time required from when VDD reaches oscillation voltage range (MIN.: 3.5 V) to when the crystal resonator stabilizes. 3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible. 4. RC oscillation frequency is 40 kHz (Typ.). This clock is divided (1/2) internally. In case of RC oscillator, internal system clock frequency (fXT) is 12.5 kHz (Min.), 20 kHz (Typ.), and 27.5 kHz (Max.). 5. The values of capacitors C1', C2' and resistors R'1 depend on the resonator used and must be specified in cooperation with the manufacturer. Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used. 10 DATA SHEET U17832EE1V0DS00 V850ES/FG2 1.1.5 PLL Characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input frequency fx 4 5 MHz Output frequency fxx 16 20 MHz Clock time tPLL 800 s 1.1.6 After VDD reaches MIN.: 3.5 V Ring-OSC Characteristics (TA = -40 to +85C, VDD = EVDD = BVDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Output frequency 1.1.7 Symbol Conditions fr MIN. TYP. MAX. Unit 100 200 400 kHz MIN. TYP. MAX. Unit 5.5 V 1 ms Voltage Regulator Characteristics (TA = -40 to +85C, VDD = EVDD = BVDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input voltage Output voltage Lock time Note 1 Symbol Conditions VDD 3.5 VRO tREG 2.5 After VDD reaches MIN.: 3.5 V V Connect C = 4.7 F 20% to REGC pin Note 1. The lock time does not have to be considered for devices that have POC. VDD 3.5 V tREG VRO RESET DATA SHEET U17832EE1V0DS00 11 V850ES/FG2 1.1.8 DC Characteristics (1) Input/Output level (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input voltage, high Symbol Conditions MIN. TYP. MAX. Unit VIH1 P30, P34, P38, P41, P98, P911 0.7EVDD EVDD V VIH2 P00 to P06, P10, P11, P31 to P33, P35, P39, 0.8EVDD EVDD V 0.7BVDD BVDD V 0.7AVREF0 AVREF0 V 0.8EVDD EVDD V P40, P42, P50 to P55, P90 to P97, P99, P910, P912 to P915 VIH3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 Input voltage, low VIH4 P70 to P715 VIH5 RESET, FLMD0 VIL1 P30, P34, P38, P41, P98, P911 EVSS 0.3EVDD V VIL2 P00 to P06, P10, P11, P31 to P33, P35, P39, EVSS 0.2EVDD V BVSS 0.3BVDD V P40, P42, P50 to P55, P90 to P97, P99, P910, P912 to P915 VIL3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 Output voltage, Note 1 high VIL4 P70 to P715 AVSS 0.3AVREF0 V VIL5 RESET, FLMD0 EVSS 0.2EVDD V VOH1 P00 to P06, P10, P11, IOH = -1.0 mA EVDD - 1.0 EVDD V P30 to P39, P40 to P42, IOH = -0.1 mA EVDD - 0.5 EVDD V PCM0 to PCM3, PCS0, IOH = -1.0 mA BVDD - 1.0 BVDD V PCS1, PCT0, PCT1, PCT4, IOH = -0.1 mA BVDD - 0.5 BVDD V IOH = -1.0 mA AVREF0 - 1.0 AVREF0 V IOH = -0.1 mA AVREF0 - 0.5 AVREF0 V IOL = 1.0 mA 0 0.4 V IOL = 1.0 mA 0 0.4 V IOL = 1.0 mA 0 0.4 V P50 to P55, P90 to P915 VOH2 PCT6, PDL0 to PDL13 VOH3 Output voltage, Note 1 low VOL1 P70 to P715 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, P90 to P915 VOL2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 VOL3 P70 to P715 Pull-up resistor R1 VI = 0 V 10 30 100 k Pull-down Note 2 resistor R2 VI = VDD 10 30 100 k Notes 1. Total IOH/IOL (Max.) is 20 mA/-20 mA each power supply terminal (EVDD, BVDD and AVREF0). 2. DRST pin only (OCDM0 is the control register). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 12 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (2) Pin leakage current (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input leakage current, high Symbol ILIH1 Conditions VIN = VDD MIN. Analog pins Note 1 Input leakage current, low ILIL1 VIN = 0 V Output leakage current, low Note ILOH1 ILOL1 VO = VDD VO = 0 V MAX. Unit +0.2 A Other pins +0.5 Analog pins -0.2 Note 1 Output leakage current, high TYP. Other pins -0.5 Analog pins +0.2 Other pins +0.5 Analog pins -0.2 Other pins -0.5 A A A 1. For flash memory product, specification of FLMD0 is as follows: Input leakage current, high: 2 A Input leakage current, low: -2 A DATA SHEET U17832EE1V0DS00 13 V850ES/FG2 (3) Supply current Supply current (V850ES/FG2: PD70F3236, PD70F3235, PD70F3234) (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Flash memory products Note 1 supply current Symbol IDD1 Conditions fXX = 20 MHz Normal operation MIN. TYP. MAX. Unit 30 45 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 22 mA (OSC = 5 MHz), all peripheral functions stopped IDD2 fXX = 20 MHz HALT mode 18 28 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 11 mA (OSC = 5 MHz), all peripheral functions stopped IDD3 fXX = 5 MHz 0.6 0.9 mA 0.25 0.7 mA Subclock operation Crystal resonator Notes 2, 3 mode fXT = 32.768 kHz 200 400 A Subclock operation RC resonator Notes 2, 3 Note 4 mode fXT = 40 kHz 200 400 A 20 120 A IDLE1 mode (OSC = 5 MHz), PLL off IDD4 fXX = 5 MHz IDLE2 mode (OSC = 5 MHz), PLL off IDD5 IDD6 IDD7 Sub-IDLE Notes 2, 3 mode Crystal resonator Sub-IDLE Notes 2, 3 mode RC resonator Note 4 fXT = 40 kHz 35 140 A POC stopped, 7 50 A 10 55 A 15 65 A 18 70 A Stop mode fXT = 32.768 kHz Notes 2, 5 Ring-OSC stopped POC operating, Ring-OSC stopped POC stopped, Ring-OSC operating POC operating, Ring-OSC operating Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped). The current of AVREF0 and the port buffer current including the current flowing through the on-chip pull-up/pull-down resistors are not included. 2. When the main OSC is stopped. 3. POC operating, Ring-OSC operating. 4. The RC oscillation frequency is 40 kHz(TYP.). This clock is internally divided by 2. 5. When the sub-OSC is not used. 14 DATA SHEET U17832EE1V0DS00 V850ES/FG2 Supply current (V850ES/FG2: PD703235, PD703234) (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Mask ROM products supply Note 1 current Symbol IDD1 Conditions fXX = 20 MHz Normal operation MIN. TYP. MAX. Unit 25 40 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 20 mA (OSC = 5 MHz), all peripheral functions stopped IDD2 fXX = 20 MHz HALT mode 14 24 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 9 mA (OSC = 5 MHz), all peripheral functions stopped IDD3 fXX = 5 MHz IDLE1 mode 0.25 0.7 mA 0.2 0.7 mA (OSC = 5 MHz), PLL off IDD4 fXX = 5 MHz IDLE2 mode (OSC = 5 MHz), PLL off IDD5 Subclock operation Crystal resonator Notes 2, 3 mode fXT = 32.768 kHz 50 350 A IDD6 Sub-IDLE Notes 2, 3 mode Crystal resonator 20 120 A Sub-IDLE Notes 2, 3 mode RC resonator Note 4 fXT = 40 kHz 35 140 A POC stopped, 7 50 A 10 55 A 15 65 A 18 70 A IDD7 Stop mode fXT = 32.768 kHz Notes 2, 5 Ring-OSC stopped POC operating, Ring-OSC stopped POC stopped, Ring-OSC operating POC operating, Ring-OSC operating Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped). The current of AVREF0 and the port buffer current including the current flowing through the on-chip pull-up/pull-down resistors are not included. 2. When the main OSC is stopped. 3. POC operating, Ring-OSC operating. 4. The RC oscillation frequency is 40 kHz(TYP.). This clock is internally divided by 2. 5. When the sub-OSC is not used. DATA SHEET U17832EE1V0DS00 15 V850ES/FG2 1.1.9 Data Retention Characteristics STOP Mode (TA = -40 to +85C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Conditions Data retention voltage VDDDR In STOP mode Data retention current IDDDR VDDDR = 2.0 V Supply voltage rise time tRVD MIN. TYP. MAX. Unit 5.5 V 450 A 1.9 6 s 1 Supply voltage fall time tFVD 1 s Supply voltage retention time tHVD After STOP mode release 0 ms STOP release signal input time tDREL After VDD reaches MIN.: 3.5 V 0 s Data retention input voltage, high VIHDR All input ports 0.9VDDDR VDDDR V Data retention input voltage, low VILDR All input ports 0 0.1VDDDR V Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range. STOP mode setting Operating voltage lower limit (Min.) VDD/EVDD/BVDD tFVD tRVD VDDDR tHVD VIHDR RESET (input) VIHDR STOP mode release interrupt (NMI, etc.) (Released by falling edge) STOP mode release interrupt (NMI, etc.) (Released by rising edge) VILDR 16 DATA SHEET U17832EE1V0DS00 STOP release signal input tDREL V850ES/FG2 1.1.10 AC Characteristics AC Test Input Measurement Points (VDD, AVDD, EVDD, BVDD) VDD VIH (MIN.) VIH (MIN.) Measurement points VSS VIL (MAX.) VIL (MAX.) AC Test Output Measurement Points VOH (MIN.) VOH (MIN.) Measurement points VOL (MAX.) VOL (MAX.) Load Conditions DUT (Device under measurement) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. DATA SHEET U17832EE1V0DS00 17 V850ES/FG2 (1) CLKOUT output timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. 80 s Unit Output cycle tCYK 50 ns High-level width tWKH tCYK/2 - 15 ns Low-level width tWKL tCYK/2 - 15 ns Rise time tKR 15 ns Fall time tKF 15 ns Clock Timing tCYK tWKH tWKL CLKOUT (output) tKR 18 DATA SHEET U17832EE1V0DS00 tKF V850ES/FG2 (2) Basic Operation (a) Reset, Interrupt timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol RESET low-level width tWRSL NMI high-level width tWNIH NMI low-level width INTPn Note 1 high-level low-level MAX. Unit ns Analog noise elimination 500 ns tWNIL Analog noise elimination 500 ns tWITH Analog noise elimination (n = 0 to 7) Digital noise elimination (n = 3) Note 1 MIN. 500 width INTPn Conditions tWITL width Analog noise elimination (n = 0 to 7) Digital noise elimination (n = 3) 500 ns Note 2 ns 500 ns Note 2 ns Notes 1. ADTRG is same spec (P03/INTP0/ADTRG). DRST is same spec (P05/INTP2/DRST). 2. 2Tsamp + 20 or 3Tsamp + 20 Tsamp: Sampling clock for noise elimination Reset/Interrupt VDD tREG tWRSL RESET (input) tWNIH tWNIL tWITH tWITL NMI (input) INTPn (input) Remark n = 0 to 7 DATA SHEET U17832EE1V0DS00 19 V850ES/FG2 (b) Key return timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol KRn input high-level width tWKRH KRn input low-level width tWKRL Conditions MIN. Analog noise elimination (n = 0 to 7) MAX. Unit 500 ns 500 ns tWKRL tWKRH KRn (input) Remark n = 0 to 7 (c) Timer input timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter TIn high-level width Symbol tTIH Conditions MIN. MAX. Unit TIP00, TIP01, TIP10, TIP11, TIP20, Note ns Note ns TIP21, TIP30, TIP31, TIn low-level width Note tTIL TIQ00 to TIQ03, TIQ10 to TIQ13 2Tsamp + 20 or 3Tsamp + 20 Tsamp: Sampling clock for noise elimination tTIL tTIH TIn (input) Remark 20 TIn: TIP00, TIP01, TIP10 TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (d) CSIB timing (i) Master mode (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKBn cycle time tKCYn 125 ns SCKBn high-level width tKHn tKCYn/2 - 15 ns SCKBn low-level width tKLn tKCYn/2 - 15 ns SIBn setup time (to SCKBn) tSIKn 30 ns SIBn hold time (from SCKBn) tKSIn 25 ns Output delay time from SCKBn to SOBn tKSOn Remark 25 ns n = 0, 1 (ii) Slave mode (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKBn cycle time tKCYn 200 ns SCKBn high-level width tKHn 90 ns SCKBn low-level width tKLn 90 ns SIBn setup time (to SCKBn) tSIKn 50 ns SIBn hold time (from SCKBn) tKSIn 50 ns Output delay time from SCKBn to SOBn tKSOn Remark 50 ns n = 0, 1 DATA SHEET U17832EE1V0DS00 21 V850ES/FG2 tKCYn tKLn tKHn SCKBn (I/O) tSIKn SIBn (input) Hi-Z tKSIn Input data tKSOn Output data SOBn (output) Remark n = 0. 1 (e) UART timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Communication rate ASCK0 cycle time 22 DATA SHEET U17832EE1V0DS00 MIN. MAX. Unit 312.5 kbps 10 MHz V850ES/FG2 (f) CAN timing (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. Transfer rate Internal delay time Note MAX. Unit 1 Mbps 100 ns Note Internal delay time (tNODE) = Internal transfer delay time (tOUTPUT) + Internal receive delay time (tINPUT) CAN internal clock Note toutput CTXDn pin (Transfer data) tinput CRXDn pin (Receive data) Remark *CAN internal clock (fCAN): CAN baud rate clock n = 0, 1 V850ES/FG2 CAN macro CTXDn pin Internal transfer delay {{ Note Internal receive delay CRXDn pin Image figure of internal delay Remark n = 0, 1 DATA SHEET U17832EE1V0DS00 23 V850ES/FG2 (g) A/D converter (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. Resolution Note 4.0 AVREF0 5.5 V Overall error 0.15 MAX. Unit 10 bit 0.3 %FSR Conversion time tCONV 3.1 16 s Analog input voltage VIAN AVSS AVREF0 V AVREF0 current IAREF0 Note When using A/D converter 5 10 mA When not using A/D converter 1 10 A Excluding quantization error (0.05%FSR). Indicates the ratio to the full-scale value (%FSR). Remark FSR: Full Scale Range (h) POC circuit characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Detection voltage VPOC0 Power supply startup time tPTH VDD = 0 V 3.5 V tPTHD In case of power on. Response delay time 1 Note 1 MIN. TYP. MAX. 3.5 3.7 3.9 0.002 Unit V ms 3.0 ms 1 ms After VDD reaches 3.9 V. Response delay time 2 Note tPD In case of power off. 2 After VDD drops 3.5 V. Minimum VDD width tPW 0.2 ms Notes 1. From detect voltage to release reset signal. 2. From detect voltage to output reset signal. VDD Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD tPTHD Time 24 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (i) LVI circuit characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Detection voltage Note 1 Response time Symbol Conditions MIN. TYP. MAX. Unit VLVI0 4.2 4.4 4.6 V VLVI1 4.0 4.2 4.4 V 0.2 2.0 ms After VDD reaches VLVI0/VLVI1 tLD (Max.). After VDD drops VLVI0/VLVI1 (Min.). Minimum VDD width tLW 0.2 Reference voltage stabilization Note 2 wait time tLWAIT ms 0.1 After VDD reaches 3.5 V. 0.2 ms After LVION bit (LVIM.bit7) = 0 1 Notes 1. The time required to output an interrupt/reset after the detection voltage is detected. 2. Unnecessary when the POC function is used. VDD Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT tLD LVION bit = 0 1 DATA SHEET U17832EE1V0DS00 tLD Time 25 V850ES/FG2 (j) RAM retention flag characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Detection voltage VRAMH Supply voltage rise time tRAMHTH VDD = 0 V 3.5 V tRAMHD After the supply voltage reaches Note Response time MIN. TYP. MAX. Unit 1.9 2.0 2.1 V 1,800 ms 2.0 ms 0.002 0.2 the detection voltage (MAX.) Minimum VDD width Note tRAMHW 0.2 ms Time required to set the RAMF bit after the detection voltage is detected. VDD Operating voltage (MIN.) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tRAMHTH tRAMHW tRAMHD tRAMHD Time 26 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (k) Flash memory programming characteristics (i) Basic characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Operating frequency fCPU Supply voltage VDD CWRT Number of writes Conditions MIN. TYP. MAX. Unit 4 20 MHz 3.5 5.5 V 100 Times Note Input voltage, high VIH FLMD0 0.8EVDD EVDD V Input voltage, low VIL FLMD0 EVSS 0.2EVDD V tIWRT Flash: 256 KB (PD70F3235) T.B.D s +85 C Write time + erase time + tERASE Programming temperature Note 384 KB (PD70F3236) -40 tPRG The initial write when the product is shipped, any erase write set of operations, or any programming operation is counted as one rewrite. Example: P: Write, E: Erase P E P E P: 3 rewrites Shipped product Shipped product E P E P E P: 3 rewrites (ii) Serial Write Operation Characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit 3 ms FLMD0 setup time from RESET tRFCF Count execution time tCOUNT FLMD0 high-level width tCH 10 100 s FLMD0 low-level width tCL 10 100 s FLMD rise time tR 50 ns FLMD fall time tF 50 ns Note 5000/fX+ s " " represents the oscillation stabilization time. VDD RESET VSS tCOUNT tRFCF tCH VDD FLMD0 VSS tCL tF tR VDD FLMD1 VSS L DATA SHEET U17832EE1V0DS00 27 V850ES/FG2 Electrical Specifications of (A1)-Grade 1.2 1.2.1 Absolute maximum ratings Absolute Maximum Ratings (TA = 25C): Flash memory products (1/2) Parameter Symbol Supply voltage Conditions Unit VDD VDD = EVDD = BVDD -0.5 to +6.5 V BVDD VDD = EVDD = BVDD -0.5 to +6.5 V EVDD VDD = EVDD = BVDD -0.5 to +6.5 V -0.5 to +6.5 V VSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V AVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V BVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V EVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 AVREF0 Input voltage Ratings VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, V -0.5 to EVDD + 0.5 Note -0.5 to BVDD + 0.5 Note V P90 to P915, RESET, FLMD0 VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, V PDL0 to PDL13 VI3 Analog input voltage Note VIAN -0.5 to VRO + 0.5 X1, X2, XT1, XT2 Note -0.5 to AVREF0 + 0.5 P70 to P715 Note V V Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 28 DATA SHEET U17832EE1V0DS00 V850ES/FG2 Absolute maximum ratings (TA = 25C): Flash memory products (2/2) Parameter Symbol Output current, low Output current, high IOL IOH Conditions P00 to P06, P10, P11, P30 to P39, Per pin 4 mA Total of all pins Note1 mA P70 to P715 Per pin 4 mA Total of all pins Note2 mA 4 mA Note1 mA PCM0 to PCM3, PCS0, PCS1, PCT0, Per pin PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins P00 to P06, P10, P11, P30 to P39, Per pin P40 to P42, P50 to P55, P90 to P915 Total of all pins P70 to P715 Per pin PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 TA temperature Storage temperature Unit P40 to P42, P50 to P55, P90 to P915 Total of all pins Operating ambient Ratings Per pin Total of all pins 50 20 50 -4 -50 Note1 -4 -20 Note2 -4 -50 Note1 mA mA mA mA mA mA Normal operating mode -40 to +110 C Flash programming mode -40 to +85 C -40 to +125 C Tstg Notes 1. This value is a value at the time of TA = 25 C. At the time of TA = 110 C, This value is 20 mA/-20 mA. 2. This value is a value at the time of TA = 25 C. At the time of TA = 110 C, This value is 10 mA/-10 mA. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. DATA SHEET U17832EE1V0DS00 29 V850ES/FG2 Absolute Maximum Ratings (TA = 25C): Mask ROM products (1/2) Parameter Symbol Supply voltage Conditions Unit VDD VDD = EVDD = BVDD -0.5 to +6.5 V BVDD VDD = EVDD = BVDD -0.5 to +6.5 V EVDD VDD = EVDD = BVDD -0.5 to +6.5 V -0.5 to +6.5 V VSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V AVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V BVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V EVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 AVREF0 Input voltage Ratings VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, V -0.5 to EVDD + 0.5 Note -0.5 to BVDD + 0.5 Note V P90 to P915, RESET, IC VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, V PDL0 to PDL13 VI3 Analog input voltage Note VIAN -0.5 to VRO + 0.5 X1, X2, XT1, XT2 Note -0.5 to AVREF0 + 0.5 P70 to P715 Note V V Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 30 DATA SHEET U17832EE1V0DS00 V850ES/FG2 Absolute maximum ratings (TA = 25C): Mask ROM products (2/2) Parameter Symbol Output current, low Output current, high IOL IOH Conditions P00 to P06, P10, P11, P30 to P39, Unit Per pin 4 mA P40 to P42, P50 to P55, P90 to P915 Total of all pins Note1 mA P70 to P715 Per pin 4 mA Total of all pins Note2 mA 4 mA Note1 mA PCM0 to PCM3, PCS0, PCS1, PCT0, Per pin PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins P00 to P06, P10, P11, P30 to P39, Per pin P40 to P42, P50 to P55, P90 to P915 Total of all pins P70 to P715 Per pin Total of all pins PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 Operating ambient Ratings Per pin Total of all pins 50 20 50 -4 -50 Note1 -4 -20 Note2 -4 -50 Note1 mA mA mA mA mA mA TA -40 to +110 C Tstg -65 to +110 C temperature Storage temperature Notes 1. This value is a value at the time of TA = 25 C. At the time of TA = 110 C, This value is 20 mA/-20 mA. 2. This value is a value at the time of TA = 25 C. At the time of TA = 110 C, This value is 10 mA/-10 mA. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. DATA SHEET U17832EE1V0DS00 31 V850ES/FG2 1.2.2 Capacitance (TA = 25C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V) Parameter I/O capacitance Symbol CIO Conditions MIN. TYP. fX = 1 MHz, MAX. Unit 10 pF Unmeasured pins returned to 0 V. 1.2.3 Operating conditions (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Internal system clock frequency Symbol fCLK Conditions MIN. REGC Capacity = 4.7 F at operation with 4 subclock (RC resonator) 32 MAX. Unit 20 MHz main clock REGC Capacity = 4.7 F at operation with Note TYP. The internal system clock frequency is half the oscillation frequency. DATA SHEET U17832EE1V0DS00 12.5 Note 27.5 Note kHz V850ES/FG2 1.2.4 Oscillator Characteristics Main clock oscillator characteristics (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Resonator Recommended Circuit Ceramic resonator Parameter Conditions MIN. Oscillation frequency Note 1 (fX) X1 4 X2 Oscillation Note 2 stabilization time TYP. Unit 5 MHz 16 After reset release After STOP mode MAX. 0.5 Note 3 2 /fX s Note 4 ms Note 4 ms release After IDLE2 mode 0.35 release Crystal Oscillation frequency Note 1 (fX) resonator Oscillation Note 2 stabilization time 4 MHz 16 After reset release After STOP mode 5 0.5 Note 3 2 /fX s Note 4 ms Note 4 s release After IDLE2 mode 350 release Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize the crystal resonator after reset or STOP mode is released. 3. Time required to stabilize access to the internal flash memory. 4. The value differs depending on the OSTS register settings. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. DATA SHEET U17832EE1V0DS00 33 V850ES/FG2 Subclock Oscillator Characteristics (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Resonator Recommended Circuit RC resonator XT1 XT2 Parameter Conditions Oscillation frequency Notes1, 4 (fXT) R = 390 k 5% C = 47 pF 10% Note 3 MIN. TYP. MAX. Unit 25 40 55 kHz 100 s Note 3 Oscillation Note 2 stabilization time Notes 1. Indicates only oscillator characteristics. Refer to 27. 2. 10 AC Characteristics for CPU operating clock. 2. Time required from when VDD reaches oscillation voltage range (MIN.: 3.5 V) to when the crystal resonator stabilizes. 3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible. 4. RC oscillation frequency is 40 kHz (Typ.). This clock is divided (1/2) internally. In case of RC oscillator, internal system clock frequency (fXT) is 12.5 kHz (Min.), 20 kHz (Typ.), and 27.5 kHz (Max.). Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used. 34 DATA SHEET U17832EE1V0DS00 V850ES/FG2 1.2.5 PLL Characteristics (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input frequency fx 4 5 MHz Output frequency fxx 16 20 MHz Clock time tPLL 800 s 1.2.6 After VDD reaches MIN.: 3.5 V Ring-OSC Characteristics (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Output frequency 1.2.7 Symbol Conditions fr MIN. TYP. MAX. Unit 100 200 400 kHz MIN. TYP. MAX. Unit 5.5 V 1 ms Voltage Regulator Characteristics (TA = -40 to +110C, VDD = EVDD = BVDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input voltage Output voltage Lock time Note 1 Symbol Conditions VDD 3.5 VRO tREG 2.5 After VDD reaches MIN.: 3.5 V V Connect C = 4.7 F 20% to REGC pin Note 1. The lock time does not have to be considered for devices that have POC. VDD 3.5 V tREG VRO RESET DATA SHEET U17832EE1V0DS00 35 V850ES/FG2 1.2.8 DC Characteristics (1) Input/Output level (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input voltage, high Symbol Conditions MIN. TYP. MAX. Unit VIH1 P30, P34, P38, P41, P98, P911 0.7EVDD EVDD V VIH2 P00 to P06, P10, P11, P31 to P33, P35, P39, 0.8EVDD EVDD V 0.7BVDD BVDD V 0.7AVREF0 AVREF0 V 0.8EVDD EVDD V P40, P42, P50 to P55, P90 to P97, P99, P910, P912 to P915 VIH3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 Input voltage, low VIH4 P70 to P715 VIH5 RESET, FLMD0 VIL1 P30, P34, P38, P41, P98, P911 EVSS 0.3EVDD V VIL2 P00 to P06, P10, P11, P31 to P33, P35, P39, EVSS 0.2EVDD V BVSS 0.3BVDD V P40, P42, P50 to P55, P90 to P97, P99, P910, P912 to P915 VIL3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 Output voltage, Note 1 high VIL4 P70 to P715 AVSS 0.3AVREF0 V VIL5 RESET, FLMD0 EVSS 0.2EVDD V VOH1 P00 to P06, P10, P11, IOH = -1.0 mA EVDD - 1.0 EVDD V P30 to P39, P40 to P42, IOH = -0.1 mA EVDD - 0.5 EVDD V PCM0 to PCM3, PCS0, IOH = -1.0 mA BVDD - 1.0 BVDD V PCS1, PCT0, PCT1, PCT4, IOH = -0.1 mA BVDD - 0.5 BVDD V IOH = -1.0 mA AVREF0 - 1.0 AVREF0 V IOH = -0.1 mA AVREF0 - 0.5 AVREF0 V IOL = 1.0 mA 0 0.4 V IOL = 1.0 mA 0 0.4 V IOL = 1.0 mA 0 0.4 V P50 to P55, P90 to P915 VOH2 PCT6, PDL0 to PDL13 VOH3 Output voltage, Note 1 low VOL1 P70 to P715 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, P90 to P915 VOL2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 VOL3 P70 to P715 Pull-up resistor R1 VI = 0 V 10 30 100 k Pull-down Note 2 resistor R2 VI = VDD 10 30 100 k Notes 1. Total IOH/IOL (Max.) is 20 mA/-20 mA each power supply terminal (EVDD, BVDD and AVREF0). 2. DRST pin only (OCDM0 is the control register). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 36 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (2) Pin leakage current (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input leakage current, high Symbol ILIH1 Conditions VIN = VDD MIN. Analog pins Note 1 Input leakage current, low ILIL1 VIN = 0 V Output leakage current, low Note ILOH1 ILOL1 VO = VDD VO = 0 V MAX. Unit +0.3 A Other pins +2.0 Analog pins -0.3 Note 1 Output leakage current, high TYP. Other pins -2.0 Analog pins +0.3 Other pins +2.0 Analog pins -0.2 Other pins -2.0 A A A 1. For flash memory product, specification of FLMD0 is as follows: Input leakage current, high: 4 A Input leakage current, low: -4 A DATA SHEET U17832EE1V0DS00 37 V850ES/FG2 (3) Supply current Supply current (V850ES/FG2: PD70F3236, PD70F3235, PD70F3234) (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Flash memory products Note 1 supply current Symbol IDD1 Conditions Normal operation fXX = 20 MHz MIN. TYP. MAX. Unit 30 45 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 22 mA (OSC = 5 MHz), all peripheral functions stopped IDD2 HALT mode fXX = 20 MHz 18 30 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 11 mA (OSC = 5 MHz), all peripheral functions stopped IDD3 IDLE1 mode fXX = 5 MHz 0.6 1.2 mA 0.25 0.9 mA (OSC = 5 MHz), PLL off IDD4 IDLE2 mode fXX = 5 MHz (OSC = 5 MHz), PLL off IDD5 Subclock operation RC resonator Notes 2, 3 Note 4 mode fXT = 40 kHz 200 600 A IDD6 Sub-IDLE Notes 2, 3 mode RC resonator Note 4 fXT = 40 kHz 35 340 A IDD7 Stop mode POC stopped, 7 250 A 10 255 A 15 265 A 18 270 A Notes 2, 5 Ring-OSC stopped POC operating, Ring-OSC stopped POC stopped, Ring-OSC operating POC operating, Ring-OSC operating Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped). The current of AVREF0 and the port buffer current including the current flowing through the on-chip pull-up/pull-down resistors are not included. 2. When the main OSC is stopped. 3. POC operating, Ring-OSC operating. 4. The RC oscillation frequency is 40 kHz (TYP.). This clock is internally divided by 2. 5. When the sub-OSC is not used. 38 DATA SHEET U17832EE1V0DS00 V850ES/FG2 Supply current (V850ES/FG2: PD703235, PD703234) (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Mask ROM products supply Note 1 current Symbol IDD1 Conditions fXX = 20 MHz Normal operation MIN. TYP. MAX. Unit 25 40 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 20 mA (OSC = 5 MHz), all peripheral functions stopped IDD2 fXX = 20 MHz HALT mode 14 26 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 9 mA (OSC = 5 MHz), all peripheral functions stopped IDD3 fXX = 5 MHz IDLE1 mode 0.25 0.9 mA 0.2 0.9 mA (OSC = 5 MHz), PLL off IDD4 fXX = 5 MHz IDLE2 mode (OSC = 5 MHz), PLL off IDD5 Subclock operation RC resonator Notes 2, 3 Note 4 mode fXT = 40 kHz 50 550 A IDD6 Sub-IDLE Notes 2, 3 mode RC resonator Note 4 fXT = 40 kHz 35 340 A IDD7 Stop mode POC stopped, 7 250 A 10 255 A 15 265 A 18 270 A Notes 2, 5 Ring-OSC stopped POC operating, Ring-OSC stopped POC stopped, Ring-OSC operating POC operating, Ring-OSC operating Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped). The current of AVREF0 and the port buffer current including the current flowing through the on-chip pull-up/pull-down resistors are not included. 2. When the main OSC is stopped. 3. POC operating, Ring-OSC operating. 4. The RC oscillation frequency is 40 kHz(TYP.). This clock is internally divided by 2. 5. When the sub-OSC is not used. DATA SHEET U17832EE1V0DS00 39 V850ES/FG2 1.2.9 Data Retention Characteristics STOP Mode (TA = -40 to +110C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Conditions Data retention voltage VDDDR In STOP mode Data retention current IDDDR VDDDR = 2.0 V Supply voltage rise time tRVD MIN. TYP. MAX. Unit 5.5 V 230 A 1.9 10 s 1 Supply voltage fall time tFVD 1 s Supply voltage retention time tHVD After STOP mode release 0 ms STOP release signal input time tDREL After VDD reaches MIN.: 3.5 V 0 s Data retention input voltage, high VIHDR All input ports 0.9VDDDR VDDDR V Data retention input voltage, low VILDR All input ports 0 0.1VDDDR V Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range. STOP mode setting Operating voltage lower limit (Min.) VDD/EVDD/BVDD tFVD tRVD VDDDR tHVD VIHDR RESET (input) VIHDR STOP mode release interrupt (NMI, etc.) (Released by falling edge) STOP mode release interrupt (NMI, etc.) (Released by rising edge) VILDR 40 DATA SHEET U17832EE1V0DS00 STOP release signal input tDREL V850ES/FG2 1.2.10 AC Characteristics AC Test Input Measurement Points (VDD, AVDD, EVDD, BVDD) VDD VIH (MIN.) VIH (MIN.) Measurement points VSS VIL (MAX.) VIL (MAX.) AC Test Output Measurement Points VOH (MIN.) VOH (MIN.) Measurement points VOL (MAX.) VOL (MAX.) Load Conditions DUT (Device under measurement) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. DATA SHEET U17832EE1V0DS00 41 V850ES/FG2 (1) CLKOUT output timing (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. 80 s Unit Output cycle tCYK 50 ns High-level width tWKH tCYK/2 - 15 ns Low-level width tWKL tCYK/2 - 15 ns Rise time tKR 15 ns Fall time tKF 15 ns Clock Timing tCYK tWKH tWKL CLKOUT (output) tKR 42 DATA SHEET U17832EE1V0DS00 tKF V850ES/FG2 (2) Basic Operation (a) Reset, Interrupt timing (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol RESET low-level width tWRSL NMI high-level width tWNIH NMI low-level width INTPn Note 1 high-level low-level MAX. Unit ns Analog noise elimination 500 ns tWNIL Analog noise elimination 500 ns tWITH Analog noise elimination (n = 0 to 7) Digital noise elimination (n = 3) Note 1 MIN. 500 width INTPn Conditions tWITL width Analog noise elimination (n = 0 to 7) Digital noise elimination (n = 3) 500 ns Note 2 ns 1 ns Note 2 ns Notes 1. ADTRG is same spec (P03/INTP0/ADTRG). DRST is same spec (P05/INTP2/DRST). 2. 2Tsamp + 20 or 3Tsamp + 20 Tsamp: Sampling clock for noise elimination Reset/Interrupt VDD tREG tWRSL RESET (input) tWNIH tWNIL tWITH tWITL NMI (input) INTPn (input) Remark n = 0 to 7 DATA SHEET U17832EE1V0DS00 43 V850ES/FG2 (b) Key return timing (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol KRn input high-level width tWKRH KRn input low-level width tWKRL Conditions MIN. Analog noise elimination (n = 0 to 7) MAX. Unit 500 ns 500 ns tWKRL tWKRH KRn (input) Remark n = 0 to 7 (c) Timer input timing (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter TIn high-level width Symbol tTIH Conditions MIN. MAX. Unit TIP00, TIP01, TIP10, TIP11, TIP20, Note ns Note ns TIP21, TIP30, TIP31, TIn low-level width Note tTIL TIQ00 to TIQ03, TIQ10 to TIQ13 2Tsamp + 20 or 3Tsamp + 20 Tsamp: Sampling clock for noise elimination tTIL tTIH TIn (input) Remark 44 TIn: TIP00, TIP01, TIP10 TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (d) CSIB timing (i) Master mode (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKBn cycle time tKCYn 125 ns SCKBn high-level width tKHn tKCYn/2 - 15 ns SCKBn low-level width tKLn tKCYn/2 - 15 ns SIBn setup time (to SCKBn) tSIKn 30 ns SIBn hold time (from SCKBn) tKSIn 25 ns Output delay time from SCKBn to SOBn tKSOn Remark 25 ns n = 0, 1 (ii) Slave mode (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKBn cycle time tKCYn 200 ns SCKBn high-level width tKHn 90 ns SCKBn low-level width tKLn 90 ns SIBn setup time (to SCKBn) tSIKn 50 ns SIBn hold time (from SCKBn) tKSIn 50 ns Output delay time from SCKBn to SOBn tKSOn Remark 50 ns n = 0, 1 DATA SHEET U17832EE1V0DS00 45 V850ES/FG2 tKCYn tKLn tKHn SCKBn (I/O) tSIKn SIBn (input) Hi-Z tKSIn Input data tKSOn Output data SOBn (output) Remark n = 0, 1 (e) UART timing (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Communication rate ASCK0 cycle time 46 DATA SHEET U17832EE1V0DS00 MIN. MAX. Unit 312.5 kbps 10 MHz V850ES/FG2 (f) CAN timing (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. Transfer rate Internal delay time Note MAX. Unit 1 Mbps 100 ns Note Internal delay time (tNODE) = Internal transfer delay time (tOUTPUT) + Internal receive delay time (tINPUT) CAN internal clock Note toutput CTXDn pin (Transfer data) tinput CRXDn pin (Receive data) Remark *CAN internal clock (fCAN): CAN baud rate clock n = 0, 1 V850ES/FG2 CAN macro CTXDn pin Internal transfer delay {{ Note Internal receive delay CRXDn pin Image figure of internal delay Remark n = 0, 1 DATA SHEET U17832EE1V0DS00 47 V850ES/FG2 (g) A/D converter (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. Resolution Note 4.0 AVREF0 5.5 V Overall error 0.15 MAX. Unit 10 bit 0.3 %FSR Conversion time tCONV 3.1 16 s Analog input voltage VIAN AVSS AVREF0 V AVREF0 current IAREF0 Note When using A/D converter 5 10 mA When not using A/D converter 1 10 A Excluding quantization error (0.05%FSR). Indicates the ratio to the full-scale value (%FSR). Remark FSR: Full Scale Range (h) POC circuit characteristics (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Detection voltage VPOC0 Power supply startup time tPTH VDD = 0 V 3.5 V tPTHD In case of power on. Response delay time 1 Note 1 MIN. TYP. MAX. 3.5 3.7 3.9 0.002 Unit V ms 3.0 ms 1 ms After VDD reaches 3.9 V. Response delay time 2 Note 2 tPD In case of power off. After VDD drops 3.5 V. Minimum VDD width tPW 0.2 ms Notes 1. From detect voltage to release reset signal. 2. From detect voltage to output reset signal. VDD Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD tPTHD Time 48 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (i) LVI circuit characteristics (TA = -40 to +110C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Detection voltage Note 1 Response time Symbol Conditions MIN. TYP. MAX. Unit VLVI0 4.2 4.4 4.6 V VLVI1 4.0 4.2 4.4 V 0.2 2.0 ms After VDD reaches VLVI0/VLVI1 tLD (Max.). After VDD drops VLVI0/VLVI1 (Min.). Minimum VDD width tLW 0.2 Reference voltage stabilization Note 2 wait time tLWAIT ms 0.1 After VDD reaches 3.5 V. 0.2 ms After LVION bit (LVIM.bit7) = 0 1 Notes 1. The time required to output an interrupt/reset after the detection voltage is detected. 2. Unnecessary when the POC function is used. VDD Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT tLD LVION bit = 0 1 DATA SHEET U17832EE1V0DS00 tLD Time 49 V850ES/FG2 (j) RAM retention flag characteristics (TA = -40 to +110C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Detection voltage VRAMH Supply voltage rise time tRAMHTH VDD = 0 V 3.5 V tRAMHD After the supply voltage reaches Note Response time MIN. TYP. MAX. Unit 1.9 2.0 2.1 V 1,800 ms 2.0 ms 0.002 0.2 the detection voltage (MAX.) Minimum VDD width Note tRAMHW 0.2 ms Time required to set the RAMF bit after the detection voltage is detected. VDD Operating voltage (MIN.) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tRAMHTH tRAMHW tRAMHD tRAMHD Time 50 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (k) Flash memory programming characteristics (i) Basic characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Operating frequency fCPU Supply voltage VDD CWRT Number of writes Conditions MIN. TYP. MAX. Unit 4 20 MHz 3.5 5.5 V 100 Times Note Input voltage, high VIH FLMD0 0.8EVDD EVDD V Input voltage, low VIL FLMD0 EVSS 0.2EVDD V tIWRT Flash: 256 KB (PD70F3235) T.B.D s +85 C Write time + erase time + tERASE Programming temperature Note 384 KB (PD70F3236) -40 tPRG The initial write when the product is shipped, any erase write set of operations, or any programming operation is counted as one rewrite. Example: P: Write, E: Erase P E P E P: 3 rewrites Shipped product Shipped product E P E P E P: 3 rewrites (ii) Serial Write Operation Characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit 3 ms FLMD0 setup time from RESET tRFCF Count execution time tCOUNT FLMD0 high-level width tCH 10 100 s FLMD0 low-level width tCL 10 100 s FLMD rise time tR 50 ns FLMD fall time tF 50 ns Note 5000/fx+ s " " represents the oscillation stabilization time. VDD RESET VSS tCOUNT tRFCF tCH VDD FLMD0 VSS tCL tF tR VDD FLMD1 VSS L DATA SHEET U17832EE1V0DS00 51 V850ES/FG2 Electrical Specifications of (A2)-Grade 1.3 1.3.1 Absolute maximum ratings Absolute Maximum Ratings (TA = 25C): Flash memory products (1/2) Parameter Symbol Supply voltage Conditions Unit VDD VDD = EVDD = BVDD -0.5 to +6.5 V BVDD VDD = EVDD = BVDD -0.5 to +6.5 V EVDD VDD = EVDD = BVDD -0.5 to +6.5 V -0.5 to +6.5 V VSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V AVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V BVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V EVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 AVREF0 Input voltage Ratings VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, V -0.5 to EVDD + 0.5 Note -0.5 to BVDD + 0.5 Note V P90 to P915, RESET, FLMD0 VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, V PDL0 to PDL13 VI3 Analog input voltage Note VIAN -0.5 to VRO + 0.5 X1, X2, XT1, XT2 Note -0.5 to AVREF0 + 0.5 P70 to P715 Note V V Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 52 DATA SHEET U17832EE1V0DS00 V850ES/FG2 Absolute maximum ratings (TA = 25C): Flash memory products (2/2) Parameter Symbol Output current, low Output current, high IOL IOH Conditions P00 to P06, P10, P11, P30 to P39, Per pin 4 mA Total of all pins Note1 mA P70 to P715 Per pin 4 mA Total of all pins Note2 mA 4 mA Note1 mA PCM0 to PCM3, PCS0, PCS1, PCT0, Per pin PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins P00 to P06, P10, P11, P30 to P39, Per pin P40 to P42, P50 to P55, P90 to P915 Total of all pins P70 to P715 Per pin PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 TA temperature Storage temperature Unit P40 to P42, P50 to P55, P90 to P915 Total of all pins Operating ambient Ratings Per pin Total of all pins 50 20 50 -4 -50 Note1 -4 -20 Note2 -4 -50 Note1 mA mA mA mA mA mA Normal operating mode -40 to +125 C Flash programming mode -40 to +85 C -40 to +125 C Tstg Notes 1. This value is a value at the time of TA = 25 C. At the time of TA = 125 C, This value is 20 mA/-20 mA. 2. This value is a value at the time of TA = 25 C. At the time of TA = 125 C, This value is 10 mA/-10 mA. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. DATA SHEET U17832EE1V0DS00 53 V850ES/FG2 Absolute Maximum Ratings (TA = 25C): Mask ROM products (1/2) Parameter Symbol Supply voltage Conditions Unit VDD VDD = EVDD = BVDD -0.5 to +6.5 V BVDD VDD = EVDD = BVDD -0.5 to +6.5 V EVDD VDD = EVDD = BVDD -0.5 to +6.5 V -0.5 to +6.5 V VSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V AVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V BVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V EVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 AVREF0 Input voltage Ratings VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, V -0.5 to EVDD + 0.5 Note -0.5 to BVDD + 0.5 Note V P90 to P915, RESET, IC VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, V PDL0 to PDL13 VI3 Analog input voltage Note VIAN -0.5 to VRO + 0.5 X1, X2, XT1, XT2 Note -0.5 to AVREF0 + 0.5 P70 to P715 Note V V Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 54 DATA SHEET U17832EE1V0DS00 V850ES/FG2 Absolute maximum ratings (TA = 25C): Mask ROM products (2/2) Parameter Symbol Output current, low Output current, high IOL IOH Conditions P00 to P06, P10, P11, P30 to P39, Unit Per pin 4 mA P40 to P42, P50 to P55, P90 to P915 Total of all pins Note1 mA P70 to P715 Per pin 4 mA Total of all pins Note2 mA 4 mA Note1 mA PCM0 to PCM3, PCS0, PCS1, PCT0, Per pin PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins P00 to P06, P10, P11, P30 to P39, Per pin P40 to P42, P50 to P55, P90 to P915 Total of all pins P70 to P715 Per pin Total of all pins PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 Operating ambient Ratings Per pin Total of all pins 50 20 50 -4 -50 Note1 -4 -20 Note2 -4 -50 Note1 mA mA mA mA mA mA TA -40 to +125 C Tstg -65 to +150 C temperature Storage temperature Notes 1. This value is a value at the time of TA = 25 C. At the time of TA = 125 C, This value is 20 mA/-20 mA. 2. This value is a value at the time of TA = 25 C. At the time of TA = 125 C, This value is 10 mA/-10 mA. Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. DATA SHEET U17832EE1V0DS00 55 V850ES/FG2 1.3.2 Capacitance (TA = 25C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V) Parameter I/O capacitance Symbol CIO Conditions MIN. TYP. fX = 1 MHz, MAX. Unit 10 pF Unmeasured pins returned to 0 V. 1.3.3 Operating conditions (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Internal system clock frequency Symbol fCLK Conditions MIN. REGC Capacity = 4.7 F, at operation with 4 subclock (RC resonator) 56 MAX. Unit 20 MHz main clock REGC Capacity = 4.7 F, at operation with Note TYP. The internal system clock frequency is half the oscillation frequency. DATA SHEET U17832EE1V0DS00 12.5 Note 27.5 Note kHz V850ES/FG2 1.3.4 Oscillator Characteristics Main clock oscillator characteristics (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Resonator Recommended Circuit Ceramic resonator Parameter Conditions MIN. Oscillation frequency Note 1 (fX) X1 4 X2 Oscillation Note 2 stabilization time TYP. Unit 5 MHz 16 After reset release After STOP mode MAX. 0.5 Note 3 2 /fX s Note 4 ms Note 4 ms release After IDLE2 mode 0.35 release Crystal Oscillation frequency Note 1 (fX) resonator Oscillation Note 2 stabilization time 4 MHz 16 After reset release After STOP mode 5 0.5 Note 3 2 /fX s Note 4 ms Note 4 s release After IDLE2 mode 350 release Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize the crystal resonator after reset or STOP mode is released. 3. Time required to stabilize access to the internal flash memory. 4. The value differs depending on the OSTS register settings. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. DATA SHEET U17832EE1V0DS00 57 V850ES/FG2 Subclock Oscillator Characteristics (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Resonator Recommended Circuit RC resonator XT1 XT2 Parameter Conditions Oscillation frequency Notes1, 4 (fXT) R = 390 k 5% C = 47 pF 10% Note 3 MIN. TYP. MAX. Unit 25 40 55 kHz 100 s Note 3 Oscillation Note 2 stabilization time Notes 1. Indicates only oscillator characteristics. Refer to 27. 3. 10 AC Characteristics for CPU operating clock. 2. Time required from when VDD reaches oscillation voltage range (MIN.: 3.5 V) to when the crystal resonator stabilizes. 3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible. 4. RC oscillation frequency is 40 kHz (Typ.). This clock is divided (1/2) internally. In case of RC oscillator, internal system clock frequency (fXT) is 12.5 kHz (Min.), 20 kHz (Typ.), and 27.5 kHz (Max.). Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used. 58 DATA SHEET U17832EE1V0DS00 V850ES/FG2 1.3.5 PLL Characteristics (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input frequency fx 4 5 MHz Output frequency fxx 16 20 MHz Clock time tPLL 800 s 1.3.6 After VDD reaches MIN.: 3.5 V Ring-OSC Characteristics (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Output frequency 1.3.7 Symbol Conditions fr MIN. TYP. MAX. Unit 100 200 400 kHz MIN. TYP. MAX. Unit 5.5 V 1 ms Voltage Regulator Characteristics (TA = -40 to +125C, VDD = EVDD = BVDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input voltage Output voltage Lock time Note 1 Symbol Conditions VDD 3.5 VRO tREG 2.5 After VDD reaches MIN.: 3.5 V V Connect C = 4.7 mF 20% to REGC pin Note 1. The lock time does not have to be considered for devices that have POC. VDD 3.5 V tREG VRO RESET DATA SHEET U17832EE1V0DS00 59 V850ES/FG2 1.3.8 DC Characteristics (1) Input/Output level (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input voltage, high Symbol Conditions MIN. TYP. MAX. Unit VIH1 P30, P34, P38, P41, P98, P911 0.7EVDD EVDD V VIH2 P00 to P06, P10, P11, P31 to P33, P35, P39, 0.8EVDD EVDD V 0.7BVDD BVDD V 0.7AVREF0 AVREF0 V 0.8EVDD EVDD V P40, P42, P50 to P55, P90 to P97, P99, P910, P912 to P915 VIH3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 Input voltage, low VIH4 P70 to P715 VIH5 RESET, FLMD0 VIL1 P30, P34, P38, P41, P98, P911 EVSS 0.3EVDD V VIL2 P00 to P06, P10, P11, P31 to P33, P35, P39, EVSS 0.2EVDD V BVSS 0.3BVDD V P40, P42, P50 to P55, P90 to P97, P99, P910, P912 to P915 VIL3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 Output voltage, Note 1 high VIL4 P70 to P715 AVSS 0.3AVREF0 V VIL5 RESET, FLMD0 EVSS 0.2EVDD V VOH1 P00 to P06, P10, P11, IOH = -1.0 mA EVDD - 1.0 EVDD V P30 to P39, P40 to P42, IOH = -0.1 mA EVDD - 0.5 EVDD V PCM0 to PCM3, PCS0, IOH = -1.0 mA BVDD - 1.0 BVDD V PCS1, PCT0, PCT1, PCT4, IOH = -0.1 mA BVDD - 0.5 BVDD V IOH = -1.0 mA AVREF0 - 1.0 AVREF0 V IOH = -0.1 mA AVREF0 - 0.5 AVREF0 V IOL = 1.0 mA 0 0.4 V IOL = 1.0 mA 0 0.4 V IOL = 1.0 mA 0 0.4 V P50 to P55, P90 to P915 VOH2 PCT6, PDL0 to PDL13 VOH3 Output voltage, Note 1 low VOL1 P70 to P715 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55, P90 to P915 VOL2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL13 VOL3 P70 to P715 Pull-up resistor R1 VI = 0 V 10 30 100 k Pull-down Note 2 resistor R2 VI = VDD 10 30 100 k Notes 1. Total IOH/IOL (Max.) of EVDD is 20 mA/-20 mA. Total IOH/IOL (Max.) of AVREF0 is 10 mA/-10 mA. 2. DRST pin only (OCDM0 is the control register). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 60 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (2) Pin leakage current (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit A Input leakage current, high ILIH1 VIN = VDD Analog pins +1.0 Other pins +5.0 Input leakage current, low ILIL1 VIN = 0 V Analog pins -1.0 Other pins -5.0 Analog pins +1.0 Other pins +5.0 Analog pins -1.0 Other pins -5.0 Output leakage current, high Output leakage current, low ILOH1 ILOL1 VO = VDD VO = 0 V DATA SHEET U17832EE1V0DS00 A A A 61 V850ES/FG2 (3) Supply current Supply current (V850ES/FG: PD70F3236, PD70F3235, PD70F3234) (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Flash memory products Note 1 supply current Symbol IDD1 Conditions fXX = 20 MHz Normal operation, MIN. TYP. MAX. Unit 30 45 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 22 mA (OSC = 5 MHz), all peripheral functions stopped IDD2 fXX = 20 MHz HALT mode 18 30 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 11 mA (OSC = 5 MHz), all peripheral functions stopped IDD3 fXX = 5 MHz IDLE1 mode 0.6 1.5 mA 0.25 1.15 mA (OSC = 5 MHz), PLL off IDD4 fXX = 5 MHz IDLE2 mode (OSC = 5 MHz), PLL off IDD5 Subclock operation RC resonator Notes 2, 3 Note 4 mode fXT = 40 kHz 200 850 A IDD6 Sub-IDLE Notes 2, 3 mode RC resonator Note 4 fXT = 40 kHz 35 590 A IDD7 Stop mode POC stopped, 7 500 A 10 505 A 15 515 A 18 520 A Notes 2, 5 Ring-OSC stopped POC operating, Ring-OSC stopped POC stopped, Ring-OSC operating POC operating, Ring-OSC operating Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped). The current of AVREF0 and the port buffer current including the current flowing through the on-chip pull-up/pull-down resistors are not included. 2. When the main OSC is stopped. 3. POC operating, Ring-OSC operating. 4. The RC oscillation frequency is 40 kHz(TYP.). This clock is internally divided by 2. 5. When the sub-OSC is not used. 62 DATA SHEET U17832EE1V0DS00 V850ES/FG2 Supply current (V850ES/FG2: PD703235, PD703234) (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Mask ROM products supply Note 1 current Symbol IDD1 Conditions Normal operation, fXX = 20 MHz MIN. TYP. MAX. Unit 25 40 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 20 mA (OSC = 5 MHz), all peripheral functions stopped IDD2 HALT mode fXX = 20 MHz 14 26 mA (OSC = 5 MHz), all peripheral functions operating fXX = 20 MHz 9 mA (OSC = 5 MHz), all peripheral functions stopped IDD3 IDLE1 mode fXX = 5 MHz 0.25 1.15 mA 0.2 1.15 mA (OSC = 5 MHz), PLL off IDD4 IDLE2 mode fXX = 5 MHz (OSC = 5 MHz), PLL off IDD5 Subclock operation RC resonator Notes 2, 3 Note 4 mode fXT = 40 kHz 50 800 A IDD6 Sub-IDLE Notes 2, 3 mode RC resonator Note 4 fXT = 40 kHz 35 590 A IDD7 Stop mode POC stopped, 7 500 A 10 505 A 15 515 A 18 520 A Notes 2, 5 Ring-OSC stopped POC operating, Ring-OSC stopped POC stopped, Ring-OSC operating POC operating, Ring-OSC operating Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped). The current of AVREF0 and the port buffer current including the current flowing through the on-chip pull-up/pull-down resistors are not included. 2. When the main OSC is stopped. 3. POC operating, Ring-OSC operating. 4. The RC oscillation frequency is 40 kHz (TYP.). This clock is internally divided by 2. 5. When the sub-OSC is not used. DATA SHEET U17832EE1V0DS00 63 V850ES/FG2 1.3.9 Data Retention Characteristics STOP Mode (TA = -40 to +125C, VDD = EVDD = BVDD =1.9 V to 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Conditions Data retention voltage VDDDR In STOP mode Data retention current IDDDR VDDDR = 2.0 V Supply voltage rise time tRVD MIN. TYP. MAX. Unit 5.5 V 450 A 1.9 6 s 1 Supply voltage fall time tFVD 1 s Supply voltage retention time tHVD After STOP mode release 0 ms STOP release signal input time tDREL After VDD reaches MIN.: 3.5 V 0 s Data retention input voltage, high VIHDR All input ports 0.9VDDDR VDDDR V Data retention input voltage, low VILDR All input ports 0 0.1VDDDR V Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range. STOP mode setting Operating voltage lower limit (Min.) VDD/EVDD/BVDD tFVD tRVD VDDDR tHVD VIHDR RESET (input) VIHDR STOP mode release interrupt (NMI, etc.) (Released by falling edge) STOP mode release interrupt (NMI, etc.) (Released by rising edge) VILDR 64 DATA SHEET U17832EE1V0DS00 STOP release signal input tDREL V850ES/FG2 1.3.10 AC Characteristics AC Test Input Measurement Points (VDD, AVDD, EVDD, BVDD) VDD VIH (MIN.) VIH (MIN.) Measurement points VSS VIL (MAX.) VIL (MAX.) AC Test Output Measurement Points VOH (MIN.) VOH (MIN.) Measurement points VOL (MAX.) VOL (MAX.) Load Conditions DUT (Device under measurement) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. DATA SHEET U17832EE1V0DS00 65 V850ES/FG2 (1) CLKOUT output timing (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. 80 s Unit Output cycle tCYK 50 ns High-level width tWKH tCYK/2 - 15 ns Low-level width tWKL tCYK/2 - 15 ns Rise time tKR 15 ns Fall time tKF 15 ns Clock Timing tCYK tWKH tWKL CLKOUT (output) tKR 66 DATA SHEET U17832EE1V0DS00 tKF V850ES/FG2 (2) Basic Operation (a) Reset, Interrupt timing (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol RESET low-level width tWRSL NMI high-level width tWNIH NMI low-level width INTPn Note 1 high-level low-level MAX. Unit ns Analog noise elimination 500 ns tWNIL Analog noise elimination 500 ns tWITH Analog noise elimination (n = 0 to 7) Digital noise elimination (n = 3) Note 1 MIN. 500 width INTPn Conditions tWITL width Analog noise elimination (n = 0 to 7) Digital noise elimination (n = 3) 500 ns Note 2 ns 1 ns Note 2 ns Notes 1. ADTRG is same spec (P03/INTP0/ADTRG). DRST is same spec (P05/INTP2/DRST). 2. 2Tsamp + 20 or 3Tsamp + 20 Tsamp: Sampling clock for noise elimination Reset/Interrupt VDD tREG tWRSL RESET (input) tWNIH tWNIL tWITH tWITL NMI (input) INTPn (input) Remark n = 0 to 7 DATA SHEET U17832EE1V0DS00 67 V850ES/FG2 (b) Key return timing (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol KRn input high-level width tWKRH KRn input low-level width tWKRL Conditions MIN. Analog noise elimination (n = 0 to 7) MAX. Unit 500 ns 500 ns tWKRL tWKRH KRn (input) Remark n = 0 to 7 (c) Timer input timing (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter TIn high-level width Symbol tTIH Conditions MIN. MAX. Unit TIP00, TIP01, TIP10, TIP11, TIP20, Note ns Note ns TIP21, TIP30, TIP31, TIn low-level width Note tTIL TIQ00 to TIQ03, TIQ10 to TIQ13 2Tsamp + 20 or 3Tsamp + 20 Tsamp: Sampling clock for noise elimination tTIL tTIH TIn (input) Remark 68 TIn: TIP00, TIP01, TIP10 TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (d) CSIB timing (i) Master mode (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKBn cycle time tKCYn 125 ns SCKBn high-level width tKHn tKCYn/2 - 15 ns SCKBn low-level width tKLn tKCYn/2 - 15 ns SIBn setup time (to SCKBn) tSIKn 30 ns SIBn hold time (from SCKBn) tKSIn 25 ns Output delay time from SCKBn to SOBn tKSOn Remark 25 ns n = 0, 1 (ii) Slave mode (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKBn cycle time tKCYn 200 ns SCKBn high-level width tKHn 90 ns SCKBn low-level width tKLn 90 ns SIBn setup time (to SCKBn) tSIKn 50 ns SIBn hold time (from SCKBn) tKSIn 50 ns Output delay time from SCKBn to SOBn tKSOn Remark 50 ns n = 0, 1 DATA SHEET U17832EE1V0DS00 69 V850ES/FG2 tKCYn tKLn tKHn SCKBn (I/O) tSIKn SIBn (input) Hi-Z tKSIn Input data tKSOn Output data SOBn (output) Remark n = 0, 1 (e) UART timing (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Communication rate ASCK0 cycle time 70 DATA SHEET U17832EE1V0DS00 MIN. MAX. Unit 312.5 kbps 10 MHz V850ES/FG2 (f) CAN timing (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. Transfer rate Internal delay time Note MAX. Unit 1 Mbps 100 ns Note Internal delay time (tNODE) = Internal transfer delay time (tOUTPUT) + Internal receive delay time (tINPUT) CAN internal clock Note toutput CTXDn pin (Transfer data) tinput CRXDn pin (Receive data) Remark *CAN internal clock (fCAN): CAN baud rate clock n = 0, 1 V850ES/FG2 CAN macro CTXDn pin Internal transfer delay {{ Note Internal receive delay CRXDn pin Image figure of internal delay Remark n = 0, 1 DATA SHEET U17832EE1V0DS00 71 V850ES/FG2 (g) A/D converter (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. Resolution Note 4.0 AVREF0 5.5 V Overall error 0.15 MAX. Unit 10 bit 0.35 %FSR Conversion time tCONV 3.1 16 s Analog input voltage VIAN AVSS AVREF0 V AVREF0 current IAREF0 Note When using A/D converter 5 10 mA When not using A/D converter 1 10 A Excluding quantization error (0.05%FSR). Indicates the ratio to the full-scale value (%FSR). Remark FSR: Full Scale Range (h) POC circuit characteristics (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Detection voltage VPOC0 Power supply startup time tPTH VDD = 0 V 3.5 V tPTHD In case of power on. Response delay time 1 Note MIN. TYP. MAX. 3.5 3.7 3.9 0.002 Unit V ms 3.0 ms 1 ms 1 After VDD reaches 3.9 V. Response delay time 2 Note tPD In case of power off. 2 After VDD drops 3.5 V. Minimum VDD width tPW 0.2 ms Notes 1. From detect voltage to release reset signal. 2. From detect voltage to output reset signal. VDD Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD tPTHD Time 72 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (i) LVI circuit characteristics (TA = -40 to +125C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Detection voltage Note 1 Response time Symbol Conditions MIN. TYP. MAX. Unit VLVI0 4.2 4.4 4.6 V VLVI1 4.0 4.2 4.4 V 0.2 2.0 ms After VDD reaches VLVI0/VLVI1 tLD (Max.). After VDD drops VLVI0/VLVI1 (Min.). Minimum VDD width tLW 0.2 Reference voltage stabilization Note 2 wait time tLWAIT ms 0.1 After VDD reaches 3.5 V. 0.2 ms After LVION bit (LVIM.bit7) = 0 1 Notes 1. The time required to output an interrupt/reset after the detection voltage is detected. 2. Unnecessary when the POC function is used. VDD Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT tLD LVION bit = 0 1 DATA SHEET U17832EE1V0DS00 tLD Time 73 V850ES/FG2 (j) RAM retention flag characteristics (TA = -40 to +125C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Detection voltage VRAMH Supply voltage rise time tRAMHTH VDD = 0 V 3.5 V tRAMHD After the supply voltage reaches Note Response time MIN. TYP. MAX. Unit 1.9 2.0 2.1 V 1,800 ms 2.0 ms 0.002 0.2 the detection voltage (MAX.) Minimum VDD width Note tRAMHW 0.2 ms Time required to set the RAMF bit after the detection voltage is detected. VDD Operating voltage (MIN.) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tRAMHTH tRAMHW tRAMHD tRAMHD Time 74 DATA SHEET U17832EE1V0DS00 V850ES/FG2 (k) Flash memory programming characteristics (i) Basic characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Operating frequency fCPU Supply voltage VDD CWRT Number of writes Conditions MIN. TYP. MAX. Unit 4 20 MHz 3.5 5.5 V 100 Times Note Input voltage, high VIH FLMD0 0.8EVDD EVDD V Input voltage, low VIL FLMD0 EVSS 0.2EVSS V tIWRT Flash: 256 KB (PD70F3235) T.B.D s +85 C Write time + erase time + tERASE Programming temperature Note 384 KB (PD70F3236) -40 tPRG The initial write when the product is shipped, any erase write set of operations, or any programming operation is counted as one rewrite. Example: P: Write, E: Erase P E P E P: 3 rewrites Shipped product Shipped product E P E P E P: 3 rewrites (ii) Serial Write Operation Characteristics (TA = -40 to +85C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V AVREF0 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit 3 ms FLMD0 setup time from RESET tRFCF Count execution time tCOUNT FLMD0 high-level width tCH 10 100 s FLMD0 low-level width tCL 10 100 s FLMD rise time tR 50 ns FLMD fall time tF 50 ns Note 5000/fX+ s " " represents the oscillation stabilization time. VDD RESET VSS tCOUNT tRFCF tCH VDD FLMD0 VSS tCL tF tR VDD FLMD1 VSS L DATA SHEET U17832EE1V0DS00 75 V850ES/FG2 2. Injected Current Specification 2.1 Injected Current Specification of (A)-Grade 2.1.1 Absolute Maximum Ratings ( Ta = +25 C ) Parameter Pos. Overload Current Symbol IINJPM Conditions Digital input pins MIN. TYP. Total Analog input pins 4 mA 50 mA 4 mA Per pin Total IINJNM Unit Per pin VIN > VDD Neg. Overload Current MAX. Digital input pins 20 mA -4 mA Per pin VIN < VSS Total Analog input pins -50 mA -4 mA -20 mA Per pin Total Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. Remark: Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins. 2.1.2 DC Characteristics for overload current ( Ta = -40 to +85 C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V ) Parameter Pos. Overload Current Symbol IINJP Conditions Digital input pins VIN > VDD MIN. TYP. MAX. Unit Per pin 2 mA 16 mA Per pin 0.5 mA 2 mA Per pin -0.3 mA Total -2.4 mA Per pin -0.3 mA Total -1.2 mA Total Analog input pins Total Neg. Overload Current IINJN Digital input pins Note1 VIN < VSS Analog input pins Remark(s): 1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins. 2. These specifications are not tested in outgoing inspection, but specified based on the device characterization. 3. Refer to the next pages for Input leakage current and A/D characteristics. Note(s): 1. In case of using Sub clock, an adjacent pin of XT2 pin is the following specification. Parameter Neg. Overload Current VIN < VSS Symbol IINJN Conditions an adjacent pin MIN. Per pin of XT2 pin Note2 Note(s): 2. An adjacent pin of XT2 pin is as follows: V850ES/FE2: P00 pin, V850ES/FF2: P05 pin, V850ES/FG2: P02 pin, V850ES/FJ2: P02 pin 76 DATA SHEET U17832EE1V0DS00 TYP. MAX. Unit -0.1 mA V850ES/FG2 2.1.3 DC Characteristics for pins influenced by injected current on an adjacent pin ( Ta = -40 to +85 C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V ) Parameter Input leakage current Symbol ILIH Conditions TYP. MAX. Unit - 0.5 uA - 0.2 uA IINJN : -0.3mA(per pin), -0.6mA(total) 5 40 uA IINJN : -0.1mA(per pin), -0.2mA(total) 1 10 uA IINJN : -0.3mA(per pin), -0.6mA(total) 5 40 uA IINJN : -0.1mA(per pin), -0.2mA(total) 1 10 uA VI = VDD High MIN. Digital input pins IINJP : 2mA(per pin), 4mA(total) Analog input pins IINJP : 0.5mA(per pin), 1mA(total) Input leakage current ILIL VI = 0 Low Digital input pins Analog input pins Remark(s): 1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins. 2. These specifications are not tested in outgoing inspection, but specified based on the device characterization. 3. Measurement conditions are shown in Figure 1. 4. TYP. is the value of Ta=+25 C. DATA SHEET U17832EE1V0DS00 77 V850ES/FG2 2.1.4 A/D converter influenced by injected current on an adjacent pin ( Ta = -40 to +85 C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V ) Parameter Symbol Conditions MIN. TYP. MAX. Unit IINJP : 0.5mA(per pin), 1mA(total) +/- 0.10 %FSR IINJN : -0.3mA(per pin), -0.6mA(total) +/- 0.25 %FSR Degradation of Overall error Note1 Remark(s): 1. These specifications are not tested in outgoing inspection, but specified based on the device characterization. 2. Measurement conditions are shown in Figure 1. Note(s): This value is the degradation by injected current on an adjacent pin. Therefore, this value is added to the specification of A/D converter's overall error defined separately as the electrical specifications. Caution(s): When there is a leakage current, the effect on the ADC accuracy depends on the external analog source impedance. Example) Conditions: AVREF0 = 5.0V, external analog source impedance = 10K ohm If there is a leakage current of 10uA by injected current, the effect on the ADC accuracy is 10(uA) x 10K(ohm) / 5(V) = 2 %FSR Figure 1 Measurement Injected current Injected current DUT ( device under test ) 78 DATA SHEET U17832EE1V0DS00 V850ES/FG2 2.2 Injected Current Specification of (A1)-Grade 2.2.1 Absolute Maximum Ratings ( Ta = +25 C ) Parameter Pos. Overload Current Symbol IINJPM Conditions Digital input pins VIN > VDD MIN. TYP. Total IINJNM 4 mA 50 mA 4 mA 20 mA Per pin Total Digital input pins VIN < VSS Unit Per pin Analog input pins Neg. Overload Current MAX. -4 mA -50 mA -4 mA -20 mA Per pin Total Analog input pins Per pin Total Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. Remark: Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins. 2.2.2 DC Characteristics for overload current ( Ta = -40 to +110 C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V ) Parameter Pos. Overload Current Symbol IINJP Conditions Digital input pins VIN > VDD MIN. TYP. 2 mA mA Per pin 0.5 mA 2 mA Per pin -0.3 mA Total -2.4 mA Per pin -0.3 mA Total -1.2 mA Total Neg. Overload Current IINJN Digital input pins Note1 VIN < VSS Analog input pins Unit 16 Per pin Total Analog input pins MAX. Remark(s): 1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins. 2. These specifications are not tested in outgoing inspection, but specified based on the device characterization. 3. Refer to the next pages for Input leakage current and A/D characteristics. Note(s): 1. In case of using Sub clock, an adjacent pin of XT2 pin is the following specification. Parameter Neg. Overload Current VIN < VSS Symbol IINJN Conditions an adjacent pin of XT2 pin MIN. TYP. Per pin MAX. Unit -0.1 mA Note2 Note(s): 2. An adjacent pin of XT2 pin is as follows. V850ES/FE2: P00 pin, V850ES/FF2: P05 pin, V850ES/FG2: P02 pin, V850ES/FJ2: P02 pin DATA SHEET U17832EE1V0DS00 79 V850ES/FG2 2.2.3 DC Characteristics for pins influenced by injected current on an adjacent pin ( Ta = -40 to +110 C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V ) Parameter Input leakage current Symbol ILIH Conditions TYP. MAX. Unit - 2 uA - 2 uA IINJN : -0.3mA(per pin), -0.6mA(total) 5 60 uA IINJN : -0.1mA(per pin), -0.2mA(total) 1 15 uA IINJN : -0.3mA(per pin), -0.6mA(total) 5 60 uA IINJN : -0.1mA(per pin), -0.2mA(total) 1 15 uA VI = VDD High MIN. Digital input pins IINJP : 2mA(per pin), 4mA(total) Analog input pins IINJP : 0.5mA(per pin), 1mA(total) Input leakage current ILIL VI = 0 Digital input pins Low Analog input pins Remark(s): 1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins. 2. These specifications are not tested in outgoing inspection, but specified based on the device characterization. 3. Measurement conditions are shown in Figure 2. 4. TYP. is the value of Ta=+25 C. 80 DATA SHEET U17832EE1V0DS00 V850ES/FG2 2.2.4 A/D converter influenced by injected current on an adjacent pin ( Ta = -40 to +110 C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V ) Parameter Symbol Conditions TYP. MAX. Unit IINJP : 0.5mA(per pin), 1mA(total) +/- 0.10 %FSR IINJN : -0.3mA(per pin), -0.6mA(total) +/- 0.25 %FSR Degradation of Overall error MIN. Note1 Remark(s): 1. These specifications are not tested in outgoing inspection, but specified based on the device characterization. 2. Measurement conditions are shown in Figure 2. Note(s): This value is the degradation by injected current on an adjacent pin. Therefore, this value is added to the specification of A/D converter's overall error defined separately as the electrical specifications. Caution(s): When there is a leakage current, the effect on the ADC accuracy depends on the external analog source impedance. Example) Conditions: AVREF0 = 5.0V, external analog source impedance = 10K ohm If there is a leakage current of 10uA by injected current, the effect on the ADC accuracy is 10(uA) x 10K(ohm) / 5(V) = 2 %FSR Figure 2 Measurement Injected current Injected current DUT ( device under test ) DATA SHEET U17832EE1V0DS00 81 V850ES/FG2 2.3 Injected Current Specification of (A2)-Grade 2.3.1 Absolute Maximum Ratings ( Ta = +25 C ) Parameter Pos. Overload Current Symbol IINJPM Conditions Digital input pins VIN > VDD MIN. TYP. Total IINJNM 4 mA 50 mA 4 mA 20 mA Per pin Total Digital input pins VIN < VSS Unit Per pin Analog input pins Neg. Overload Current MAX. -4 mA -50 mA -4 mA -20 mA Per pin Total Analog input pins Per pin Total Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. Remark: Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins. 2.3.2 DC Characteristics for overload current ( Ta = -40 to +125 C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V ) Parameter Pos. Overload Current Symbol IINJP Conditions Digital input pins VIN > VDD MIN. TYP. 2 mA mA Per pin 0.5 mA 2 mA Per pin -0.3 mA Total -2.4 mA Per pin -0.3 mA Total -1.2 mA Total Neg. Overload Current IINJN Digital input pins Note1 VIN < VSS Analog input pins Unit 16 Per pin Total Analog input pins MAX. Remark(s): 1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins. 2. These specifications are not tested in outgoing inspection, but specified based on the device characterization. 3. Refer to the next pages for Input leakage current and A/D characteristics. Note(s): 1. In case of using Sub clock, an adjacent pin of XT2 pin is the following specification. Parameter Neg. Overload Current VIN < VSS Symbol IINJN Conditions an adjacent pin of XT2 pin MIN. TYP. Per pin Note2 Note(s): 2. An adjacent pin of XT2 pin is as follows. V850ES/FE2: P00 pin, V850ES/FF2: P05 pin, V850ES/FG2: P02 pin, V850ES/FJ2: P02 pin 82 DATA SHEET U17832EE1V0DS00 MAX. Unit -0.1 mA V850ES/FG2 2.3.3 DC Characteristics for pins influenced by injected current on an adjacent pin ( Ta = -40 to +125 C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V ) Parameter Input leakage current Symbol ILIH Conditions TYP. MAX. Unit - 5 uA - 3 uA IINJN : -0.3mA(per pin), -0.6mA(total) 5 60 uA IINJN : -0.1mA(per pin), -0.2mA(total) 1 15 uA IINJN : -0.3mA(per pin), -0.6mA(total) 5 60 uA IINJN : -0.1mA(per pin), -0.2mA(total) 1 15 uA VI = VDD High MIN. Digital input pins IINJP : 2mA(per pin), 4mA(total) Analog input pins IINJP : 0.5mA(per pin), 1mA(total) Input leakage current ILIL VI = 0 Digital input pins Low Analog input pins Remark(s): 1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins. 2. These specifications are not tested in outgoing inspection, but specified based on the device characterization. 3. Measurement conditions are shown in Figure 3. 4. TYP. is the value of Ta=+25 C. DATA SHEET U17832EE1V0DS00 83 V850ES/FG2 2.3.4 A/D converter influenced by injected current on an adjacent pin ( Ta = -40 to +125 C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V ) Parameter Symbol Conditions TYP. MAX. +/- 0.10 %FSR IINJN : -0.3mA(per pin), -0.6mA(total) +/- 0.25 %FSR Note1 Remark(s): 1. These specifications are not tested in outgoing inspection, but specified based on the device characterization. 2. Measurement conditions are shown in Figure 3. Note(s): This value is the degradation by injected current on an adjacent pin. Therefore, this value is added to the specification of A/D converter's overall error defined separately as the electrical specifications. Caution(s): When there is a leakage current, the effect on the ADC accuracy depends on the external analog source impedance. Example) Conditions: AVREF0 = 5.0V, external analog source impedance = 10K ohm If there is a leakage current of 10uA by injected current, the effect on the ADC accuracy is 10(uA) x 10K(ohm) / 5(V) = 2 %FSR Figure 3 Measurement Injected current Injected current DUT ( device under test ) 84 Unit IINJP : 0.5mA(per pin), 1mA(total) Degradation of Overall error MIN. DATA SHEET U17832EE1V0DS00 V850ES/FG2 3. Package Drawings Figure 3-1: Package Drawing 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S C D Q R 26 25 100 1 F G H I J M K P S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 16.000.20 B 14.000.20 C 14.000.20 D 16.000.20 F 1.00 G 1.00 H 0.22 +0.05 -0.04 I J 0.08 0.50 (T.P.) K 1.000.20 L 0.500.20 M 0.17 +0.03 -0.07 N 0.08 P 1.400.05 Q 0.100.05 R 3 +7 -3 S 1.60 MAX. S100GC-50-8EU, 8EA-2 DATA SHEET U17832EE1V0DS00 85 V850ES/FG2 4. Recommended Soldering Conditions Table 4-1: Soldering Conditions (1) PD70F3236MxGC(Ax)-8EA, PD70F3235MxGC(Ax)-8EA, PD70F3234MxGC(Ax)-8EA Soldering Method Soldering Condition Symbol of Recommended Soldering Condition Infrared Reflow Package Peak Temperature: 235C Time: 30 seconds max. (210C min.) Count: 3 max IR35-207-3 Note Exposure Limit: 7 days Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. After that, prebaking is necessary at 125 C for 20 to 72 hours. 86 DATA SHEET U17832EE1V0DS00