Integrated Circuit Systems, Inc. ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853011 is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V LVPECL/ HiPerClockSTM ECL Fanout Buffer and a member of the HiPerClockSTM family of High Perfor mance Clock Solutions from ICS. The ICS853011 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-par t skew characteristics make the ICS853011 ideal for those clock distribution applications demanding well defined perfor mance and repeatability. * 2 differential 2.5V/3.3V LVPECL / ECL outputs ICS * 1 differential PCLK, nPCLK input pair * PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: >3GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input * Output skew: 5ps (typical) * Part-to-part skew: 130ps (maximum) * Propagation delay: 390ps (maximum) * Additive phase jitter, RMS: 0.06ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V * -40C to 85C ambient operating temperature * Available in both, Standard and RoHS/Lead-Free compliant packages BLOCK DIAGRAM PCLK nPCLK PIN ASSIGNMENT Q0 nQ0 Q1 nQ1 Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 Vcc PCLK nPCLK VEE ICS853011 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View 853011BM www.icst.com/products/hiperclocks.html 1 REV. C JULY 13, 2005 Integrated Circuit Systems, Inc. ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Output Type Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5 VEE Power Negative supply pin. 6 nPCLK Input 7 PCLK Input 8 VCC Power Pullup/ Pulldown Pulldown Description Clock input. VCC/2 default when left floating. LVPECL interface levels. Clock input. Default LOW when left floating. LVPECL interface levels. Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLDOWN Input Pulldown Resistor 75 k RVCC/2 Pullup/Pulldown Resistors 50 k 853011BM Test Conditions www.icst.com/products/hiperclocks.html 2 Minimum Typical Maximum Units REV. C JULY 13, 2005 Integrated Circuit Systems, Inc. ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Negative Supply Voltage, VEE 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Supply Voltage, VCC Outputs, IO Continuous Current Surge Current to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- 50mA 100mA istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40C to +85C Storage Temperature, TSTG -65C to 150C Package Thermal Impedance, JA 112.7C/W (0 lfpm) (Junction-to-Ambient) TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 2.375 3. 3 3.8 V 25 mA TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Symbol Parameter VOH -40C 25C 85C Units Min Typ Max Mi n Typ Ma x Min Typ Max Output High Voltage; NOTE 1 2.175 2.275 2.38 2.225 2.295 2.37 2.22 2.295 2.365 VOL Output Low Voltage; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63 V VPP 150 800 1200 150 800 1200 150 800 1200 V 3.3 1. 2 3.3 1.2 3.3 V IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK, nPCLK High Current 150 A IIL Input Low Current VCMR PCLK 1.2 150 -10 150 -10 -10 A nPCLK -150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. -150 V -150 A TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V Min -40C Typ Max Output High Voltage; NOTE 1 1.375 1.475 VOL Output Low Voltage; NOTE 1 0.605 VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK, nPCLK High Current PCLK Input Low Current nPCLK 150 Symbol Parameter VOH VCMR IIH IIL Min 25C Typ Max 1.58 1.425 1.495 0.745 0.88 0.625 800 1200 150 2.5 1.2 1.2 Min 85C Typ Max 1.57 1.42 1.495 1.565 V 0.72 0.815 0.64 0.735 0.83 V 800 1200 150 800 1200 V 2.5 1.2 2.5 V 150 A 150 150 Units -10 -10 -10 A -150 -150 -150 A For notes see above Table 3B, 3.3V LVPECL DC Characteristics. 853011BM www.icst.com/products/hiperclocks.html 3 REV. C JULY 13, 2005 Integrated Circuit Systems, Inc. ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 3D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V Symbol Parameter VOH -40C 25C 85C Units Min Typ Max Min Typ Max Min Typ Max Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.08 -1.005 -0.935 V VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK, nPCLK High Current Input PCLK 150 800 1200 150 800 1200 15 0 800 1200 V 0 VEE+1.2V 0 VEE+1.2V 0 V 150 A VCMR IIH IIL VEE+1.2V 150 150 -10 -10 -10 A -150 -150 -150 Low Current nPCLK Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 Min 245 Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, Integration Range: 12KHz to 20MHz Output Rise/Fall Time Typ 25C Max Min Typ >3 tsk(o) tR/tF VCC = 2.375 TO 3.8V; VEE = 0V -40C Symbol tjit OR 375 5 20% to 80% 85C Max Min 26 0 20 390 5 275 20 5 130 0.06 0.06 25 0 Typ >3 130 70 A 80 Max >3 GHz 415 ps 20 ps 150 ps 0.06 250 100 Units ps 250 ps odc Output Duty Cycle f 1GHz 48 50 52 48 50 52 48 50 52 % All parameters are measured at f 1.7GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 853011BM www.icst.com/products/hiperclocks.html 4 REV. C JULY 13, 2005 Integrated Circuit Systems, Inc. ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Additive Phase Jitter -20 155.52MHz@12kHz to 20MHz = 0.06ps (typical) -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 853011BM www.icst.com/products/hiperclocks.html 5 REV. C JULY 13, 2005 ICS853011 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC, VCCO Qx VCC SCOPE nPCLK LVPECL V Cross Points PP V CMR PCLK nQx VEE V EE -1.8V to -0.375V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nPCLK 80% 80% PCLK VSW I N G Clock Outputs nQ0, nQ1 20% 20% tF tR Q0, Q1 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nQ0, nQ1 Q0, Q1 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 853011BM www.icst.com/products/hiperclocks.html 6 REV. C JULY 13, 2005 ICS853011 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR 3.3V LVPECL OUTPUTS 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50 125 FOUT FIN Zo = 50 Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o FIN 50 Zo = 50 VCC - 2V RTT 84 FIGURE 2A. LVPECL OUTPUT TERMINATION 853011BM 125 84 FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. C JULY 13, 2005 Integrated Circuit Systems, Inc. TERMINATION FOR ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE 853011BM www.icst.com/products/hiperclocks.html 8 REV. C JULY 13, 2005 ICS853011 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 SSTL R4 120 Zo = 60 Ohm Zo = 50 Ohm PCLK PCLK Zo = 60 Ohm nPCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm C1 LVDS R3 1K R4 1K PCLK PCLK R5 100 Zo = 50 Ohm nPCLK LVPECL R1 84 C2 nPCLK Zo = 50 Ohm HiPerClockS Input R1 1K R2 84 FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER HiPerClockS PC L K/n PCL K R2 1K FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 853011BM www.icst.com/products/hiperclocks.html 9 REV. C JULY 13, 2005 Integrated Circuit Systems, Inc. ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resister can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resister can be tied from the CLK input to ground. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resister can be tied from the TEST_CLK to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resister can be tied from CLK to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVHSTL OUTPUT All unused LVHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS OUTPUT All unused LVDS outputs should be terminated with 100 resister between the differential pair. LVDS - Like OUTPUT All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resister can be tied from PCLK to ground. HCSL OUTPUT All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1k resister can be used. SSTL OUTPUT All unused SSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 853011BM www.icst.com/products/hiperclocks.html 10 REV. C JULY 13, 2005 Integrated Circuit Systems, Inc. ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853011. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853011 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 25mA = 95mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW Total Power_MAX (3.8V, with all outputs switching) = 95mW + 61.88mW = 156.88mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.157W * 103.3C/W = 101.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE JA FOR 8-PIN SOIC, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3C/W 112.7C/W 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 853011BM www.icst.com/products/hiperclocks.html 11 REV. C JULY 13, 2005 ICS853011 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC * For logic high, VOUT = V OH_MAX (V CC_MAX * -V OH_MAX =V CC_MAX -0.935V ) = 0.935V For logic low, VOUT = VOL_MAX = VCC_MAX - 1.67V (V CC_MAX -V OL_MAX ) = 1.67V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX - (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V ))/R ] * (V OH_MAX CC_MAX L -V OH_MAX )= [(2V - 0.935V)/50] * 0.935V = 19.92mW Pd_L = [(V OL_MAX - (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW 853011BM www.icst.com/products/hiperclocks.html 12 REV. C JULY 13, 2005 Integrated Circuit Systems, Inc. ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3C/W 112.7C/W 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS853011 is: 96 Pin compatible with MC100LVEP11 and SY100EP11U 853011BM www.icst.com/products/hiperclocks.html 13 REV. C JULY 13, 2005 ICS853011 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N A MAXIMUM 8 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e H 1.27 BASIC 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-012 853011BM www.icst.com/products/hiperclocks.html 14 REV. C JULY 13, 2005 Integrated Circuit Systems, Inc. ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Package Temperature ICS853011BM 853011B 8 lead SOIC tube -40C to 85C ICS853011BMT 853011B 8 lead SOIC 2500 tape & reel -40C to 85C ICS853011BMLF 853011BL "Lead Free" 8 lead SOIC tube -40C to 85C ICS853011BMLFT 853011BL "Lead Free" 8 lead SOI 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853011BM www.icst.com/products/hiperclocks.html 15 REV. C JULY 13, 2005 Integrated Circuit Systems, Inc. ICS853011 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER REVISION HISTORY SHEET Rev B Table T3B Page 3 T3C 4 2.5V LVPECL Table - changed VOH @ 85, from 1.495V min. to 1.42V min. and 1.53V typical to 1.495V typical. T3D 4 ECL Table - changed VOH @ 85, from -1.005V min. to -1.08V min. and -0.97V typical to -1.005V typical. 6 Updated LVPECL Output Termination Diagrams. 8 8 Updated LVPECL Clock Input Inteface Figure 4D. Corrected Figure 4C. Added "Lead Free" Par t/Order Number rows. AC Characteristics Table - added Additive Phase Jitter. Added Additive Phase Jitter Section. Features Section - added Lead-Free bullet. Added "Recommendations for Unused Input and Output Pins". Ordering Information Table - corrected Lead-Free marking and added LeadFree note. B C C 853011BM T4 T8 13 4 5 1 10 15 Description of Change 3.3V LVPECL Table - changed VOH @ 85 , from 2.295V min. to 2.22V min. and 2.33V typical to 2.295V typical. www.icst.com/products/hiperclocks.html 16 Date 9/2/03 11/12/03 9/7/04 7/13/05 REV. C JULY 13, 2005