SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR # Socket and Object Code Compatible with 80960CA # Two Instructions/Clock Sustained Execution # Four 59 Mbytes/s DMA Channels with Data Chaining # Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions/clock Execution Load/Store Architecture Sixteen 32-bit Global Registers Sixteen 32-bit Local Registers Manipulate 64-bit Bit Fields 11 Addressing Modes Full Parallel Fault Model Supervisor Protection Model Y Fast Procedure Call/Return Model Full Procedure Call in 4 clocks Y On-Chip Register Cache Caches Registers on Call/Ret Minimum of 6 Frames provided Up to 15 Programmable Frames Y On-Chip Instruction Cache 4 Kbyte Two-Way Set Associative 128-bit Path to Instruction Sequencer Cache-Lock Modes Cache-Off Mode Y On-Chip Data Cache 1 Kbyte Direct-Mapped, Write Through 128 bits per Clock Access on Cache Hit Y Product Grades Available SE3: b 40 C to a 110 C Y Y Y Y Y High Bandwidth On-Chip Data RAM 1 Kbytes On-Chip RAM for Data Sustain 128 bits per clock access Four On-Chip DMA Channels 59 Mbytes/s Fly-by Transfers 32 Mbytes/s Two-Cycle Transfers Data Chaining Data Packing/Unpacking Programmable Priority Method 32-Bit Demultiplexed Burst Bus 128-bit Internal Data Paths to and from Registers Burst Bus for DRAM Interfacing Address Pipelining Option Fully Programmable Wait States Supports 8, 16 or 32-bit Bus Widths Supports Unaligned Accesses Supervisor Protection Pin Selectable Big or Little Endian Byte Ordering High-Speed Interrupt Controller Up to 248 External Interrupts 32 Fully Programmable Priorities Multi-mode 8-bit Interrupt Port Four Internal DMA Interrupts Separate, Non-maskable Interrupt Pin Context Switch in 750 ns Typical *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT (c) INTEL CORPORATION, 1995 January 1995 Order Number: 271328-001 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 1 Figure 1. 80960CF Die Photo 2 Special Environment 80960CF-30, -25, -16 32-Bit High Performance Superscalar Processor CONTENTS PAGE 1.0 PURPOSE AAAAAAAAAAAAAAAAAAAAAAAAAAAAA 5 2.0 i960 CF PROCESSOR OVERVIEW AAAAAAAAAAAAAAAAAAAAAAAAAAAAA 5 2.1 The C-Series Core AAAAAAAAAAAAAAAAAAA 6 2.2 Pipelined, Burst Bus AAAAAAAAAAAAAAAAA 6 2.3 Flexible DMA Controller AAAAAAAAAAAAA 6 2.4 Priority Interrupt Controller AAAAAAAAAAA 6 2.5 Instruction Set Summary AAAAAAAAAAAAA 7 3.0 PACKAGE INFORMATION AAAAAAAAAAAA 8 3.1 Package Introduction AAAAAAAAAAAAAAAA 8 3.2 Pin Descriptions AAAAAAAAAAAAAAAAAAAAA 8 3.3 80960CF Pinout AAAAAAAAAAAAAAAAAAAA 14 3.4 Mechanical Data AAAAAAAAAAAAAAAAAAA 18 3.5 Package Thermal Specifications AAAA 20 3.6 Stepping Register Information AAAAAA 21 3.7 Suggested Sources for 80960CF Accessories AAAAAAAAAAAAAAAAAAAAAAAAA 21 4.0 ELECTRICAL SPECIFICATIONS AAAAA 22 4.1 Absolute Maximum Ratings AAAAAAAAA 22 4.2 Operating Conditions AAAAAAAAAAAAAAA 22 4.3 Recommended Connections AAAAAAAA 22 4.4 DC Specifications AAAAAAAAAAAAAAAAAA 23 4.5 AC Specifications AAAAAAAAAAAAAAAAAA 24 5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE AAAAAAAAAAAAAAAAAAAAAAA 35 CONTENTS FIGURES Figure 1 Figure 2 Figure 3 Figure 4a Figure 4b Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10a Figure 10b Figure 11 Figure 12a Figure 12b Figure 13 Figure 14 PAGE 80960CF Die Photo AAAAAAAAAAAA 2 80960CF Block Diagram AAAAAAA 5 Example Pin Description Entry AAAAAAAAAAAAAAAAAAAAAAAAAA 8 80960CF PGA Pinout (View from Top Side) AAAAAAAAAAAAAAAA 16 80960CF PGA Pinout (View from Bottom Side) AAAAAAAAAAAA 17 168-Lead Ceramic PGA Package Dimensions AAAAAAAAA 18 80960CF PGA Package Thermal Characteristics AAAAAAA 20 Measuring 80960CF PGA Case Temperature AAAAAAAAAAAA 21 Register G0 AAAAAAAAAAAAAAAAAA 21 AC Test Load AAAAAAAAAAAAAAAAA 30 Input and Output Clocks Waveform AAAAAAAAAAAAAAAAAAAA 30 CLKIN Waveform AAAAAAAAAAAAA 30 Output Delay and Float Waveform AAAAAAAAAAAAAAAAAAAA 31 Input Setup and Hold Waveform AAAAAAAAAAAAAAAAAAAA 31 NMI, XINT7:0 Input Setup and Hold Waveform AAAAAAAAAA 31 Hold Acknowledge Timings AAAAAAAAAAAAAAAAAAAAAAA 32 Bus Back-Off (BOFF) Timings AAAAAAAAAAAAAAAAAAAAAAA 32 6.0 BUS WAVEFORMS AAAAAAAAAAAAAAAAAAA 36 3 CONTENTS CONTENTS Figure 15 Figure 31 PAGE Relative Timings Waveforms AAAAAAAAAAAAAAAAAAAA 33 Figure 16 Output Delay or Hold vs Load Capacitance AAAAAAAAAAAAAAAAAA 33 Figure 17 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC AAAAAAAAAAAAAAAAAAAAAAAAAAA 34 Figure 18 ICC vs Frequency and Temperature AAAAAAAAAAAAAAAAAA 34 Figure 19 Cold Reset Waveform AAAAAAAAA 36 Figure 20 Warm Reset Waveform AAAAAAAA 37 Figure 21 Entering the ONCE State AAAAAA 38 Figure 22a Clock Synchronization in the 2x Clock Mode AAAAAAAAAAAAAAAA 39 Figure 22b Clock Synchronization in the 1x Clock Mode AAAAAAAAAAAAAAAA 39 Figure 23 Non-Burst, Non-Pipelined Requests without Wait States AAAAAAAAAAAAAAAAAAAAAAAA 40 Figure 24 Non-Burst, Non-Pipelined Read Request with Wait States AAAAAAAAAAAAAAAAAAAAAAAA 41 Figure 25 Non-Burst, Non-Pipelined Write Request with Wait States AAAAAAAAAAAAAAAAAAAAAAAA 42 Figure 26 Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus AAAAAAAAAAAAAAAAAAAAA 43 Figure 27 Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus AAAAAAAAAAAAAAAAAAAAA 44 Figure 28 Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus AAAAAAAAAAAAAAAAAAAAA 45 Figure 29 Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus AAAAAAAAAAAAAAAAAAAAA 46 Figure 30 Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus AAAAAAAAAAAAAAAAAAAAA 47 4 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 PAGE Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus AAAAAAAAAAAAAAAAAAAAA 48 Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus AAAAAAAAAAAAAAAAAAAA 49 Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus AAAAAAAAAAAAAAAAAAAA 50 Burst, Pipelined Read Request without Wait States, 32-Bit Bus AAAAAAAAAAAAAAAAAAAA 51 Burst, Pipelined Read Requests with Wait States, 32-Bit Bus AAAAAAAAAAAAAAAAAAAA 52 Burst, Pipelined Read Requests with Wait States, 16-Bit Bus AAAAAAAAAAAAAAAAAAAA 53 Burst, Pipelined Read Requests with Wait States, 8-Bit Bus AAAAAAAAAAAAAAAAAAAAA 54 Using External READY AAAAAAAA 55 Terminating a Burst with BTERM AAAAAAAAAAAAAAAAAAAAAA 56 BOFF Functional Timing AAAAAA 57 HOLD Functional Timing AAAAAA 57 DREQ and DACK Functional Timing AAAAAAAAAAAAAAAAAAAAAAAA 58 EOP Functional Timing AAAAAAA 58 Terminal Count Functional Timing AAAAAAAAAAAAAAAAAAAAAAAA 59 FAIL Functional Timing AAAAAAA 59 A Summary of Aligned and Unaligned Transfers for Little Endian Regions AAAAAAAAAAAAAAA 60 A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) AAAAAAAAAAAAAAAAAAA 61 Idle Bus Operation AAAAAAAAAAAA 62 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 1.0 tions every clock, and peak at execution of three instructions per clock. PURPOSE This document previews electrical characterizations of Intel's i960 CF embedded microprocessor (available in 33, 25 and 16 MHz). For a detailed description of any i960 CF processor functional topicother than parametric performancerefer to the latest i960 CA Microprocessor Reference Manual (Order No. 270710) and the i960 CF Reference Manual Addendum (Order No. 272188). 2.0 i960 CF PROCESSOR OVERVIEW Intel's i960 CF microprocessor is the performance follow-on product to the i960 CA processor. The i960 CF product is socket- and object code-compatible with the CA; this makes CA-to-CF design upgrades straightforward. The i960 CF processor's instruction cache is 4 Kbytes (CA device has 1 Kbyte); CF data cache is 1 Kbyte (CA device has no data cache). This extra cache on the CF product adds a significant performance boost over the CA. The 80960CF is object code compatible with the 32-bit 80960 Core Architecture while including Special Function Register extensions to control on-chip peripherals, and instruction set extensions to shift 64bit operands and configure on-chip hardware. Multiple 128-bit internal busses, on-chip instruction caching and a sophisticated instruction scheduler allow the processor to sustain execution of two instruc- A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system's highspeed external memory sub-system. In addition, the 80960CF's on-chip caching of instructions, procedure context and critical program data substantially decouples system performance from the wait states associated with accesses to the system's slower, cost sensitive, main memory sub-system. The 80960CF bus controller also integrates full wait state and bus width control for highest system performance with minimal system design complexity. Unaligned access and Big Endian byte order support reduces the cost of porting existing applications to the 80960CF. The processor also integrates four complete datachaining DMA channels and a high-speed interrupt controller on-chip. The DMA channels perform: single-cycle or two-cycle transfers, data packing and unpacking, and data chaining. Block transfers, in addition to source or destination synchronized transfers, are provided. The interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch (``latency'') time of 750 ns. 271328 - 2 Figure 2. 80960CF Block Diagram 5 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 2.1. The C-Series Core The C-Series core is a very high performance microarchitectural implementation of the 80960 Core Architecture. The C-Series core can sustain execution of two instructions per clock (66 MIPs at 33 MHz). To achieve this level of performance, Intel has incorporated state-of-the-art silicon technology and innovative microarchitectural constructs into the implementation of the C-Series core. Factors that contribute to the core's performance include: Parallel instruction decoding allows issue of up to three instructions per clock. Most instructions execute in a single clock. Parallel instruction decode allows sustained, simultaneous execution of two single-clock instructions every clock cycle. Efficient instruction pipeline minimizes pipeline break losses. Register and resource scoreboarding allow simultaneous multi-clock instruction execution. Branch look-ahead and prediction allows many branches to execute with no pipeline break. Local Register Cache integrated on-chip caches Call/Return context. Two-way set associative, 4 Kbyte integrated instruction cache. Direct mapped, 1 Kbyte data cache, write through, write allocate. 1 Kbyte integrated Data RAM sustains a fourword (128-bit) access every clock cycle. 2.2. Pipelined, Burst Bus A 32-bit high performance bus controller interfaces the 80960CF to external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 132 Mbytes per second (at 33 MHz). Internally programmable wait states and 16 separately configurable memory regions allow the processor to interface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance. The Bus Controller's main features include: 6 Demultiplexed, Burst Bus to exploit most efficient DRAM access modes. Address Pipelining to reduce memory cost while maintaining performance. 32-, 16- and 8-bit modes for I/O interfacing ease. Full internal wait state generation to reduce system cost. Little and Big Endian support to ease application development. Unaligned access support for code portability. Three-deep request queue to decouple the bus from the core. 2.3. Flexible DMA Controller A four channel DMA controller provides high speed DMA control for data transfers involving peripherals and memory. The DMA provides advanced features such as data chaining, byte assembly and disassembly, and a high performance fly-by mode capable of transfer speed of up to 59 Mbytes per second at 33 MHz. The DMA controller features a performance and flexibility which is only possible by integrating the DMA controller and the 80960CF core. 2.4. Priority Interrupt Controller A programmable-priority interrupt controller manages up to 248 external sources through the 8-bit external interrupt port. The Interrupt Unit also handles the four internal sources from the DMA controller, and a single non-maskable interrupt input. The 8-bit interrupt port can also be configured to provide individual interrupt sources that are level or edge triggered. Interrupts in the 80960CF are prioritized and signaled within 270 ns of the request. If the interrupt is of higher priority than the processor priority, the context switch to the interrupt routine typically is complete in another 480 ns. The interrupt unit provides the mechanism for the low latency and high throughput interrupt service which is essential for embedded applications. SPECIAL ENVIRONMENT 80960CF-30, -25, -16 2.5. Instruction Set Summary The following table summarizes the 80960CF instruction set by logical groupings. See the i960 CA Microprocessor Reference Manual for a complete description of the instruction set. Data Movement Load Store Move Load Address Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Modify Trace Controls Mark Force Mark Arithmetic Add Subtract Multiply Divide Remainder Modulo Shift *Extended Shift Extended Multiply Extended Divide Add with Carry Subtract with Carry Rotate Branch Unconditional Branch Conditional Branch Compare and Branch Processor Management Modify Process Controls Modify Arithmetic Controls *System Control *DMA Control Flush Local Registers Logical And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Bit, Bit Field and Byte Set Bit Clear Bit Not Bit Alter Bit Scan for Bit Span over Bit Extract Modify Scan Byte for Equal Call and Return Fault Call Call Extended Call System Return Branch and Link Conditional Fault Synchronize Faults Atomic Atomic Add Atomic Modify NOTE: Instructions marked by (*) are 80960CF extensions to the 80960 instruction set. 7 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 3.0 Table 1. Pin Description Nomenclature PACKAGE INFORMATION Symbol 3.1. Package Introduction This section describes the pins, pinouts and thermal characteristics for the 80960CF in the 168-pin Ceramic Pin Grid Array (PGA) package. For complete package specifications and information, see the Intel Packaging Outlines and Dimensions Guide (Order No. 231369). I O I/O - Pins associated with the 32-bit demultiplexed processor bus are described in Table 2. Pins associated with basic processor configuration and control are described in Table 3. Pins associated with the 80960CF DMA Controller and Interrupt Unit are described in Table 4. Figure 3 provides an example pin description table entry. ``I/O'' signifies that data pins are input-output. ``S'' indicates pins are synchronous to PCLK2:1. ``H(Z)'' indicates that these pins float while the processor bus is in a Hold Acknowledge state. ``R(Z)'' indicates that the pins also float while RESET is low. Type D31:0 I/O S(L) H(Z) R(Z) Pins ``must be'' connected as described Synchronous. Inputs must meet setup and hold times relative to PCLK2:1 for proper operation. All outputs are synchronous to PCLK2:1. S(E) Edge sensitive input S(L) Level sensitive input A( . . . ) Asynchronous. Inputs may be asynchronous to PCLK2:1. A(E) Edge sensitive input A(L) Level sensitive input H( . . . ) While the processor's bus is in the Hold Acknowledge or Bus Backoff state, the pin: H(1) is driven to VCC H(0) is driven to VSS H(Z) floats H(Q) continues to be a valid output R( . . . ) While the processor's RESET pin is low, the pin R(1) is driven to VCC R(0) is driven to VSS R(Z) floats R(Q) continues to be a valid output All pins float while the processor is in the ONCE mode. Name Output only pin Pin can be either an input or output S( . . . ) 3.2. Pin Descriptions The 80960CF pins are described in this section. Table 1 presents the legend for interpreting the pin descriptions in the following tables. Description Input only pin Description DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configuration. The least significant bit of the data is carried on D0 and the most significant on D31. When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used. Figure 3. Example Pin Description Entry 8 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Table 2. 80960CF Pin DescriptionExternal Bus Signals Type Description A31:2 Name O S H(Z) R(Z) ADDRESS BUS carries the physical address upper 30 bits. A31 is the most significant address bit and A2 is the least significant. During a bus access, A31:2 identify all external addresses to word (4-byte) boundaries. The byte enable signals indicate the selected byte in each word. During burst accesses, A3 and A2 increment to indicate successive data cycles. D31:0 I/O S(L) H(Z) R(Z) DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configuration. The least significant bit of the data is carried on D0 and the most significant on D31. When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used. BE3 BE2 BE1 BE0 O S H(Z) R(1) BYTE ENABLES select which of the four bytes addressed by A31:2 are active during an access to a memory region configured for a 32-bit data-bus width. BE3 applies to D31:24; BE2 applies to D23:16; BE1 applies to D15:8; and BE0 applies to D7:0. 32-bit bus: BE3 - Byte Enable 3 - enable D31:24 BE2 - Byte Enable 2 - enable D23:16 - Byte Enable 1 - enable D15:8 BE1 BE0 - Byte Enable 0 - enable D7:0 For accesses to a memory region configured for a 16-bit data-bus width, the processor directly encodes BE3, BE1 and BE0 to provided BHE, A1 and BLE respectively. 16-bit bus: BE3 BE2 BE1 BE0 - Byte High Enable (BHE) - enable D15:8 - Not used (is driven high or low) - Address Bit 1 (A1) - Byte Low Enable (BLE) - enable D7:0 For accesses to a memory region configured for an 8-bit data bus width, the processor directly encodes BE1 and BE0 to provide A1 and A0 respectively. 8-bit bus: BE3 BE2 BE1 BE0 - Not used (is driven high or low) - Not used (is driven high or low) - Address Bit 1 (A1) - Address Bit 0 (A0) W/R O S H(Z) R(0) WRITE/READ is asserted for read requests and deasserted for write requests. The W/R signal changes in the same clock cycle as ADS. It remains valid for the entire access in non-pipelined regions. In pipelined regions, W/R is not guaranteed valid in the last cycle of a read access. ADS O S H(Z) R(1) ADDRESS STROBE indicates valid address and the start of a new bus access. ADS is asserted for the first clock of a bus access. READY I S(L) H(Z) R(Z) READY is an input which signals the termination of a data transfer. READY is used to indicate that read data on the bus is valid, or that a write-data transfer has completed. The READY signal works in conjunction with the internally programmed wait-state generator. If READY is enabled in a region, the pin is sampled after the programmed number of wait-states has expired. If the READY pin is deasserted, wait states continue to be inserted until READY becomes asserted. This is true for the NRAD, NRDD, NWAD, and NWDD wait states. The NXDA wait states cannot be extended. 9 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Table 2. 80960CF Pin DescriptionExternal Bus Signals (Continued) Name Type Description BTERM I S(L) H(Z) R(Z) BURST TERMINATEThe burst terminate signal breaks up a burst access and causes another address cycle to occur. The BTERM signal works in conjunction with the internally programmed wait-state generator. If READY and BTERM are enabled in a region, the BTERM pin is sampled after the programmed number of wait states has expired. When BTERM is asserted, a new ADS signal is generated and the access is completed. The READY input is ignored when BTERM is asserted. BTERM must be externally synchronized to satisfy the BTERM setup and hold times. WAIT O S H(Z) R(1) WAIT indicates internal wait state generator status. WAIT is asserted when wait states are being caused by the internal wait state generator and not by the READY or BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT can also be thought of as a READY output that the processor provides when it is inserting wait states. BLAST O S H(Z) R(0) BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last data transfer of burst and non-burst accesses after the wait state counter reaches zero. BLAST remains asserted until the clock following the last cycle of the last data transfer of a bus access. If the READY or BTERM input is used to extend wait states, the BLAST signal remains asserted until READY or BTERM terminates the access. DT/R O S H(Z) R(0) DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in conjunction with DEN to provide control for data transceivers attached to the external bus. When DT/R is asserted, the signal indicates that the processor receives data. Conversely, when deasserted, the processor sends data. DT/R changes only while DEN is high. DEN O S H(Z) R(1) DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of the bus request first data cycle and is deasserted at the end of the last data cycle. DEN is used in conjunction with DT/R to provide control for data transceivers attached to the external bus. DEN remains asserted for sequential reads from pipelined memory regions. DEN is deasserted when DT/R changes. LOCK O S H(Z) R(1) BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK may be used to prevent external agents from accessing memory which is currently involved in an atomic operation. LOCK is asserted in the first clock of an atomic operation, and deasserted in the clock cycle following the last bus access for the atomic operation. To allow the most flexibility for a memory system enforcement of locked accesses, the processor acknowledges a bus hold request when LOCK is asserted. The processor performs DMA transfers while LOCK is active. HOLD I S(L) H(Z) R(Z) HOLD REQUEST signals that an external agent requests access to the external bus. The processor asserts HOLDA after completing the current bus request. HOLD, HOLDA and BREQ are used together to arbitrate access to the processor's external bus by external bus agents. BOFF I S(L) H(Z) R(Z) BUS BACKOFF The backoff pin, when asserted, suspends the current access and causes the bus pins to float. When deasserted, the ADS signal is asserted on the next clock cycle and the access is resumed. 10 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Table 2. 80960CF Pin DescriptionExternal Bus Signals (Continued) Name Type Description HOLDA O S H(1) R(Q) HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relinquished control of the external bus. When HOLDA is asserted, the external address bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ are used together to arbitrate access to the processor's external bus by external bus agents. Since the processor grants HOLD requests and enters the Hold Acknowledge state even while RESET is asserted, HOLDA pin state is independent of the RESET pin. BREQ O S H(Q) R(0) BUS REQUEST is asserted when the bus controller has a request pending. BREQ can be used by external bus arbitration logic in conjunction with HOLD and HOLDA to determine when to return mastership of the external bus to the processor. D/C O S H(Z) R(Z) DATA OR CODE is asserted for a data request and deasserted for instruction requests. D/C has the same timing as W/R. DMA O S H(Z) R(Z) DMA ACCESS indicates whether the bus request was initiated by the DMA controller. DMA is asserted for any DMA request. DMA is deasserted for all other requests. SUP O S H(Z) R(Z) SUPERVISOR ACCESS indicates whether the bus request is issued while in supervisor mode. SUP is asserted when the request has supervisor privileges, and is deasserted otherwise. SUP can be used to isolate supervisor code and data structures from non-supervisor requests. Table 3. 80960CF Pin DescriptionProcessor Control Signals Name Type Description RESET I A(L) H(Z) R(Z) N(Z) RESET causes the chip to reset. When RESET is asserted, all external signals return to the reset state. When RESET is deasserted, initialization begins. When the 2-x clock mode is selected, RESET must remain asserted for 16 PCLK2:1 cycles before being deasserted in order to guarantee correct processor initialization. When the 1-x clock mode is selected, RESET must remain asserted for 10,000 PCLK2:1 cycles before being deasserted in order to guarantee correct initialization. The CLKMODE pin selects 1-x or 2-x input clock division of the CLKIN pin. The processor's Hold Acknowledge bus state functions while the chip is reset. If the processor's bus is in the Hold Acknowledge state when RESET is asserted, the processor will internally reset, but maintains the Hold Acknowledge state on external pins until the Hold request is removed. If a hold request is made while the processor is in the reset state, the processor bus grants HOLDA and enters the Hold Acknowledge state. FAIL O S H(Q) R(0) FAIL indicates failure of the processor's self-test performed at initialization. When RESET is deasserted and the processor begins initialization, the FAIL pin is asserted. An internal self-test is performed as part of the initialization process. If this self-test passes, the FAIL pin is deasserted otherwise it remains asserted. The FAIL pin is reasserted while the processor performs an external bus self-confidence test. If this self-test passes, the processor deasserts the FAIL pin and branches to the user's initialization routine; otherwise the FAIL pin remains asserted. Internal self-test and the use of the FAIL pin can be disabled with the STEST pin. 11 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Table 3. 80960CF Pin DescriptionProcessor Control Signals (Continued) Type Description STEST Name I S(L) H(Z) R(Z) SELF TEST causes the processor's internal self-test feature to be enabled or disabled at initialization. STEST is read on the rising edge of RESET. When asserted, the processor's internal self-test and external bus confidence tests are performed during processor initialization. When deasserted, only the external bus confidence tests are performed during initialization. ONCE I A(L) H(Z) R(Z) ON CIRCUIT EMULATION causes all outputs to be floated when asserted. ONCE is continuously sampled while RESET is low, and is latched on the rising edge of RESET. To place the processor in the ONCE state: (1) assert RESET and ONCE (order does not matter) (2) wait for at least 16 CLKIN periods in 2-x mode, or 10,000 CLKIN periods in 1-x mode, after VCC and CLKIN are within operating specifications (3) deassert RESET (4) wait at least 32 CLKIN periods (The processor is now latched in the ONCE state as long as RESET is high.) To exit the ONCE state, bring VCC and CLKIN to operating conditions, then assert RESET and bring ONCE high prior to deasserting RESET. CLKIN must operate within the specified operating conditions of the processor until step 4 above is completed. The CLKIN may then be changed to DC to achieve the lowest possible ONCE mode leakage current. ONCE can be used by emulator products or for board testers to effectively make an installed processor transparent in the board. CLKIN I A(E) H(Z) R(Z) CLOCK INPUT is an input for the external clock needed to run the processor. The external clock is internally divided as prescribed by the CLKMODE pin to produce PCLK2:1. CLKMODE I A(L) H(Z) R(Z) CLOCK MODE selects the division factor applied to the external clock input (CLKIN). When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the processor's internal clock. When CLKMODE is low, CLKIN is divided by two to create PCLK2:1 and the processor's internal clock. CLKMODE should be tied high or low in a system, as the clock mode is not latched by the processor. If left unconnected, the processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode. PCLK2 PCLK1 O S H(Q) R(Q) PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and outputs of the processor. All inputs and output timings are specified in relation to PCLK2 and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are provided to allow flexibility in the system's allocation of capacitive loading on the clock. PCLK2:1 may also be connected at the processor to form a single clock signal. VSS GROUND connections consist of 24 pins which must be connected externally to a VSS board plane. VCC POWER connections consist of 24 pins which must be connected externally to a VCC board plane. VCCPLL VCCPLL is a separate VCC supply pin for the phase lock loop used in 1x clock mode. Connecting a simple low pass filter to VCCPLL may help reduce clock jitter (TCP) in noisy environments. Otherwise, VCCPLL should be connected to VCC. N/C NO CONNECT pins must not be connected in a system. 12 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Table 4. 80960CF Pin DescriptionDMA and Interrupt Unit Control Signals Type Description DREQ3 DREQ2 DREQ1 DREQ0 Name I A(L) H(Z) R(Z) DMA REQUEST causes a DMA transfer to be requested. Each of the four signals request a transfer on a single channel. DREQ0 requests channel 0, DREQ1 requests channel 1, etc. When two or more channels are requested simultaneously, the channel with the highest priority is serviced first. Channel priority mode is programmable. DACK3 DACK2 DACK1 DACK0 O S H(1) R(1) DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of the four signals acknowledge a transfer for a single channel. DACK0 acknowledges channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted when the requesting device of a DMA is accessed. I/O A(L) H(Z/Q) R(Z) END OF PROCESS/TERMINAL COUNT can be programmed as either an input (EOP3:0) or as an output (TC3:0), but not both. Each pin is individually programmable. When programmed as an input, EOPx causes the termination of a current DMA transfer for the channel corresponding to the EOPx pin. EOP0 corresponds to channel 0, EOP1 corresponds to channel 1, etc. When a channel is configured for source and destination chaining, the EOP pin for that channel causes termination of only the current buffer transferred and causes the next buffer to be transferred. EOP3:0 are asynchronous inputs. EOP3/TC3 EOP2/TC2 EOP1/TC1 EOP0/TC0 When programmed as an output, the channel's TCx pin indicates that the channel byte count has reached 0 and a DMA has terminated. TCx is driven with the same timing as DACKx during the last DMA transfer for a buffer. If the last bus request is executed as multiple bus accesses, TCx remains asserted for the entire bus request. XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 NMI I A(E/L) H(Z) R(Z) I A(E) H(Z) R(Z) EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins can be configured in three modes. In Dedicated Mode, each pin is a dedicated external interrupt source. Dedicated inputs can be individually programmed to be level (low) or edge (falling) activated. In Expanded Mode, the 8 pins act together as an 8-bit vectored interrupt source. The interrupt pins in this mode are level activated. Since the interrupt pins are active low, the vector number requested is the one's complement of the positive logic value place on the port. This eliminates glue logic to interface to combinational priority encoders which output negative logic. In Mixed Mode, XINT7:5 are dedicated sources and XINT4:0 act as the 5 most significant bits of an expanded mode vector. The least significant bits are set to 010 internally. NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated source. 13 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 3.3. 80960CF Pinout 3.3.1 80960CF PGA PINOUT Tables 5 and 6 list the 80960CF pin names with package location. Figure 4-a depicts the complete 80960CF pinout as viewed from the top side of the component (i.e., pins facing down). Figure 4b shows the complete 80960CF pinout as viewed from the pin-side of the package (i.e., pins facing up). See Section 4.0, Electrical Specifications for specifications and recommended connections. Table 5. PGA Pin Name with Package Location (Signal Order) Address Bus Name AALocation A31 AAAAAAAAS15 A30 AAAAAAAAQ13 A29 AAAAAAAAR14 A28 AAAAAAAAQ14 A27 AAAAAAAAS16 A26 AAAAAAAAR15 A25 AAAAAAAAS17 A24 AAAAAAAAQ15 A23 AAAAAAAAR16 A22 AAAAAAAAR17 A21 AAAAAAAAQ16 A20 AAAAAAAAP15 A19 AAAAAAAAP16 A18 AAAAAAAAQ17 A17 AAAAAAAAP17 A16 AAAAAAAAN16 A15 AAAAAAAAN17 A14 AAAAAAAAM17 Data Bus Name AALocation D31 AAAAAAAAR03 D30 AAAAAAAAQ05 D29 AAAAAAAAS02 D28 AAAAAAAAQ04 D27 AAAAAAAAR02 D26 AAAAAAAAQ03 D25 AAAAAAAAS01 D24 AAAAAAAAR01 D23 AAAAAAAAQ02 D22 AAAAAAAAP03 D21 AAAAAAAAQ01 D20 AAAAAAAAP02 D19 AAAAAAAAP01 D18 AAAAAAAAN02 D17 AAAAAAAAN01 D16AAAAAAAAM01 D15 AAAAAAAAL01 D14 AAAAAAAAL02 Bus Control Name AALocation BE3 AAAAAAAAS05 BE2 AAAAAAAAS06 BE1 AAAAAAAAS07 BE0 AAAAAAAAR09 A13 AAAAAAAAL16 D13 AAAAAAAAK01 LOCK AAAAAAS14 Processor Control Name AAAALocation RESET AAAAAAAA16 FAIL AAAAAAAAAAA02 STESTAAAAAAAAB02 W/R AAAAAAAS10 DACK3 AAAAAA10 ONCE AAAAAAAAC03 ADS AAAAAAAR06 CKLIN AAAAAAAAC13 READY AAAAAS03 CLKMODE AAAAC14 BTERMAAAAAR04 PCLK1 AAAAAAAAB14 PCLK2 AAAAAAAAB13 WAIT AAAAAAAS12 BLAST AAAAAS08 DT/RAAAAAAAS11 DEN AAAAAAAS09 VSS Location C07, C08, C09, C10, C11, C12, F15, G03, G15, H03, H15, J03, J15, K03, K15, L03, L15, M03, M15, Q07, Q08, Q09, Q10, Q11 D12 AAAAAAAAJ01 D11 AAAAAAAAH01 HOLD AAAAAAR05 A10 AAAAAAAAJ17 D10 AAAAAAAAH02 HOLDA AAAAAS04 A9 AAAAAAAAAH17 D9 AAAAAAAAAG01 BREQ AAAAAAR13 A8 AAAAAAAAAG17 D8 AAAAAAAAAF01 A7 AAAAAAAAAG16 D7 AAAAAAAAAE01 D/C AAAAAAAAS13 A6 AAAAAAAAAF17 D6 AAAAAAAAAF02 DMA AAAAAAAR12 A5 AAAAAAAAAE17 D5 AAAAAAAAAD01 SUP AAAAAAAQ12 A4 AAAAAAAAAE16 D4 AAAAAAAAAE02 A3 AAAAAAAAAD17 D3 AAAAAAAAAC01 EOP/TC0 AAAA11 EOP/TC1 AAAA12 A2 AAAAAAAAAD16 D2 AAAAAAAAAD02 Location D1 AAAAAAAAAC02 A01, A03, A04, A05, B03, B04, C04, C05, D03 EOP/TC3 AAAA14 XINT7 AAAAAAC17 XINT6 AAAAAAC16 XINT5 AAAAAAB17 XINT4 AAAAAAC15 XINT3 AAAAAAB16 XINT2 AAAAAAA17 VCC XINT1 AAAAAAA15 Location XINT0 AAAAAAB15 B07, B09, B11, B12, C06, E15, F03, F16, G02, H16, J02, J16, K02, K16, M02, M16, N03, N15, Q06, R07, R08, R10, R11 VCCPLL AAAAAAAB10 14 DACK0 AAAAAB08 EOP/TC2 AAAA13 A11 AAAAAAAAK17 BOFF AAAAAAB01 DACK2 AAAAAA09 DACK1 AAAAAA08 A12 AAAAAAAAL17 D0 AAAAAAAAAE03 I/O Name AALocation DREQ3 AAAAAA07 DREQ2 AAAAAB06 DREQ1 AAAAAA06 DREQ0 AAAAAB05 No Connect NMI AAAAAAAAD15 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Table 6. PGA Pin Name with Package Location (Pin Order) Address Bus Location AAName A01 AAAAAAAAANC A02 AAAAAAAFAIL A03 AAAAAAAAANC A04 AAAAAAAAANC A05 AAAAAAAAANC A06 AAAAADREQ1 A07 AAAAADREQ3 A08 AAAAADACK1 A09 AAAAADACK2 A10 AAAAADACK3 A11 AAAEOP/TC0 A12 AAAEOP/TC1 A13 AAAEOP/TC2 A14 AAAEOP/TC3 A15 AAAAAAXINT1 A16 AAAAARESET A17 AAAAAAXINT2 Data Bus Location AAName C01 AAAAAAAAAD3 C02 AAAAAAAAAD1 C03 AAAAAAONCE C04 AAAAAAAAANC C05 AAAAAAAAANC C06 AAAAAAAAVCC C07 AAAAAAAAVSS C08 AAAAAAAAVSS C09 AAAAAAAAVSS C10 AAAAAAAAVSS C11 AAAAAAAAVSS C12 AAAAAAAAVSS C13 AAAAAACLKIN C14 AACLKMODE C15 AAAAAAXINT4 C16 AAAAAAXINT6 C17 AAAAAAXINT7 B01 AAAAAABOFF B02 AAAAASTEST B03 AAAAAAAAANC B04 AAAAAAAAANC B05 AAAAADREQ0 B06 AAAAADREQ2 B07 AAAAAAAAVCC B08 AAAAADACK0 B09 AAAAAAAAVCC B10 AAAAAVCCPLL B11 AAAAAAAAVCC B12 AAAAAAAAVCC B13 AAAAAPCLK2 B14 AAAAAPCLK1 B15 AAAAAAXINT0 B16 AAAAAAXINT3 B17 AAAAAAXINT5 D01 AAAAAAAAAD5 D02 AAAAAAAAAD2 D03 AAAAAAAAANC D15 AAAAAAAANMI D16 AAAAAAAAAA2 D17 AAAAAAAAAA3 E01 AAAAAAAAAD7 E02 AAAAAAAAAD4 E03 AAAAAAAAAD0 E15 AAAAAAAAVCC E16 AAAAAAAAAA4 E17 AAAAAAAAAA5 F01 AAAAAAAAAD8 F02 AAAAAAAAAD6 F03 AAAAAAAAVCC F15 AAAAAAAAVSS F16 AAAAAAAAVCC F17 AAAAAAAAAA6 Bus Control Location AAName G01 AAAAAAAAAD9 G02 AAAAAAAAVCC G03 AAAAAAAAVSS G15 AAAAAAAAVSS G16 AAAAAAAAAA7 G17 AAAAAAAAAA8 Processor Control Location AAAAName M01 AAAAAAAAAD16 M02 AAAAAAAAAVCC M03AAAAAAAAAAVSS M15AAAAAAAAAAVSS M16 AAAAAAAAAVCC M17AAAAAAAAAAA14 H01 AAAAAAAAD11 H02 AAAAAAAAD10 H03 AAAAAAAAVSS H15 AAAAAAAAVSS H16 AAAAAAAAVCC H17 AAAAAAAAAA9 N01AAAAAAAAAAD17 N02AAAAAAAAAAD18 N03AAAAAAAAAAVCC N15AAAAAAAAAAVCC N16 AAAAAAAAAAA16 N17 AAAAAAAAAAA15 J01 J02 J03 J15 J16 J17 AAAAAAAAD12 AAAAAAAAVCC AAAAAAAAVSS AAAAAAAAVSS AAAAAAAAVCC AAAAAAAAA10 P01 AAAAAAAAAAD19 P02 AAAAAAAAAAD20 P03 AAAAAAAAAAD22 P15 AAAAAAAAAAA20 P16 AAAAAAAAAAA19 P17 AAAAAAAAAAA17 K01 AAAAAAAAD13 K02 AAAAAAAAVCC K03 AAAAAAAAVSS K15 AAAAAAAAVSS K16 AAAAAAAAVCC K17 AAAAAAAAA11 Q01AAAAAAAAAAD21 Q02AAAAAAAAAAD23 Q03AAAAAAAAAAD26 Q04AAAAAAAAAAD28 Q05AAAAAAAAAAD30 Q06AAAAAAAAAAVCC Q07 AAAAAAAAAAVSS Q08 AAAAAAAAAAVSS Q09 AAAAAAAAAAVSS Q10 AAAAAAAAAAVSS Q11 AAAAAAAAAAVSS Q12 AAAAAAAAASUP Q13AAAAAAAAAAA30 Q14AAAAAAAAAAA28 Q15AAAAAAAAAAA24 Q16AAAAAAAAAAA21 Q17AAAAAAAAAAA18 L01 L02 L03 L15 L16 L17 AAAAAAAAD15 AAAAAAAAD14 AAAAAAAAVSS AAAAAAAAVSS AAAAAAAAA13 AAAAAAAAA12 I/O Location AAName R01 AAAAAAAAD24 R02 AAAAAAAAD27 R03 AAAAAAAAD31 R04AAAAABTERM R05 AAAAAAHOLD R06 AAAAAAAADS R07 AAAAAAAAVCC R08 AAAAAAAAVCC R09 AAAAAAAABE0 R10 AAAAAAAAVCC R11 AAAAAAAAVCC R12 AAAAAAADMA R13 AAAAAABREQ R14 AAAAAAAAA29 R15 AAAAAAAAA26 R16 AAAAAAAAA23 R17 AAAAAAAAA22 S01 AAAAAAAAD25 S02 AAAAAAAAD29 S03 AAAAAREADY S04 AAAAAHOLDA S05 AAAAAAAABE3 S06 AAAAAAAABE2 S07 AAAAAAAABE1 S08 AAAAABLAST S09 AAAAAAADEN S10 AAAAAAAW/R S11AAAAAAADT/R S12 AAAAAAAWAIT S13 AAAAAAAAD/C S14 AAAAAALOCK S15 AAAAAAAAA31 S16 AAAAAAAAA27 S17 AAAAAAAAA25 15 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 3 Figure 4a. 80960CF PGA Pinout (View from Top Side) 16 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 4 Figure 4b. 80960CF PGA Pinout (View from Bottom Side) 17 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 3.4. Mechanical Data 3.4.1 CERAMIC PGA PACKAGE 271328 - 5 Family: Ceramic Pin Grid Array Package Millimeters Symbol Inches Min Max A 3.56 4.57 A1 0.64 1.14 SOLID LID 0.025 0.045 SOLID LID A2 23 0.30 SOLID LID 0.110 0.140 SOLID LID A3 1.14 1.40 0.045 0.055 B 0.43 0.51 0.017 0.020 D 44.07 44.83 1.735 1.765 D1 40.51 40.77 1.595 1.605 e1 2.29 2.79 0.090 0.110 L 2.54 3.30 0.100 N Notes Min Max 0.140 0.180 168 S1 1.52 ISSUE IWS Notes 0.130 168 2.54 REV X 0.060 0.100 7/15/88 Figure 5. 168-Lead Ceramic PGA Package Dimensions 18 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Table 7. Ceramic PGA Package Dimension Symbols Letter or Symbol Description of Dimensions A Distance from seating plane to highest point of body A1 Distance between seating plane and base plane (lid) A2 Distance from base plane to highest point of body A3 Distance from seating plane to bottom of body B Diameter of terminal lead pin D Largest overall package dimension of length D1 A body length dimension, outer lead center to outer lead center e1 Linear spacing between true lead position centerlines L Distance from seating plane to end of lead S1 Other body dimension, outer lead center to edge of body NOTES: 1. Controlling dimension: millimeter. 2. Dimension ``e1'' (``e'') is non-cumulative. 3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415 - 0.0430 inch. 4. Dimensions ``B'', ``B1'' and ``C'' are nominal. 5. Details of Pin 1 identifier are optional. 19 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 3.5. Package Thermal Specifications The 80960CF is specified for operation when TC (the case temperature) is within the range of b 40 C- a 110 C. TC may be measured in any environment to determine whether the 80960CF is within specified operating range. The case temperature is measured at the center of the top surface, opposite the pins. Refer to Figure 7. Table 8 shows the maximum TA allowable (without exceeding TC) at various airflows and operating frequencies (fPCLK). Note that TA is greatly improved by attaching fins or a heat sink to the package. P (the maximum power consumption) is calculated by using the typical ICC as tabulated in Section 4.4, DC Specifications, and VCC of 5V. TA (the ambient temperature) can be calculated from iCA (thermal resistance from case to ambient) with the following equation: TA e TC b P*iCA Table 8. Maximum TA at Various Airflows In C (PGA Package Only) Airflow-ft/min (m/sec) fPCLK (MHz) 33 25 16 TA with Heat Sink* 0 (0) 38 50 63 200 (1.01) 57 65 74 400 (2.03) 74 79 84 600 (3.04) 76 81 86 800 (4.06) 81 85 89 TA 33 18 33 47 57 66 without 25 34 46 57 65 72 Heat Sink 16 51 60 68 74 80 *0.285x high unidirectional heat sink (Al alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). 1000 (5.07) 84 87 90 67 74 81 PGA Thermal Resistance C/Watt Airflowft./min (m/sec) Parameter 0 (0) 200 (1.01) 400 (2.03) 600 (3.07) 800 (4.06) 1000 (5.07) i Junction-to-Case (Case Measured as shown in Figure 7) 1.5 1.5 1.5 1.5 1.5 1.5 i Case-to-Ambient (No Heatsink) 17 14 11 9 7.1 6.6 i Case-to-Ambient (with Unidirectional) Heatsink)* 13 271328 - 6 9 5.5 5.0 3.9 3.4 NOTES: 1. This table applies to 80960CF PGA plugged into socket or soldered directly into board. 2. iJA e iJC a iCA. 3. iJ-CAP e 4 C/W (approx.) iJ-PIN e 4 C/W (inner pins) (approx.) iJ-PIN e 8 C/W (outer pins) (approx.) * 0.285x high unidirectional heat sink (Al alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Figure 6. 80960CF PGA Package Thermal Characteristics 20 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 3.7 Suggested Sources for 80960CF Accessories The following are some suggested sources of accessories for the 80960CF. They are neither an endorsement of any kind, nor a warranty of the performance of any of the listed products and/or companies. Sockets 1. 3M Textool Test and Interconnection Products Department P.O. Box 2963 Austin, TX 78769-2963 271328 - 7 Figure 7. Measuring 80960CF PGA Case Temperature 3.6 Stepping Register Information Upon Reset, Register G0 contains die stepping information. The following figure shows how G0 is configured. The most significant byte contains an ASCII 0. The upper middle byte contains an ASCII C. The lower middle byte contains an ASCII F. The least significant byte contains the stepping number in ASCII. G0 retains this information until it is written over by the user program. Table 9 contains a cross reference of the number in the least significant byte of register G0 to the die stepping number. ASCII DECIMAL 00 43 46 Stepping Number 0 C F Stepping Number MSB 2. Augat, Inc. Interconnection Products Group 33 Perry Avenue P.O. Box 779 Attleboro, MA 02703 (508) 222-2202 3. Concept Manufacturing Inc. (Decoupling Sockets) 43024 Christy Street Fremont, CA 94538 (415) 651-3804 Heat Sinks/Fins 1. Thermalloy, Inc. 2021 West Valley View Lane Dallas, TX 75381-0839 (214) 243-4321 2. E G & G Division 60 Audubon Road Wakefield, MA 01880 (617) 245-5900 LSB Figure 8. Register G0 Table 9. Die Stepping Cross Reference G0 Least Significant Byte Die Stepping 01 A 02 B 03 C 04 D 05 E 21 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 4.0 ELECTRICAL SPECIFICATIONS 4.1 Absolute Maximum Ratings Parameter Maximum Rating Storage Temperature Case Temperature Under Bias(2) Supply Voltage wrt. VSS Voltage on Other pins wrt VSS b 65 C to a 150 C b 40 C to a 125 C b 0.5V to a 6.5V b 0.5V to VCC a 0.5V NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability. 4.2. Operating Conditions Operating Conditions (80960CF-33, -25, -16) Symbol VCC Parameter Supply Voltage Min Max Units 80960CF-30 80960CF-25 80960CF-16 4.75 4.50 4.50 5.25 5.50 5.50 V fCLK2x Input Clock Frequency (2-x Mode) 80960CF-30 80960CF-25 80960CF-16 0 0 0 60.6 50 32 MHz MHz MHz fCLK1x Input Clock Frequency (1-x Mode) 80960CF-30 80960CF-25 80960CF-16 8 8 8 30.3 25 16 MHz MHz MHz b 40 a 110 C TC Case Temperature Under Bias 80960CF-30, -25, -16 PGA Package Notes (1) NOTES: (1) When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum frequency of 8 MHz for proper processor operation. However, in the 1-x Mode, CLKIN may still be stopped when the processor either is in a reset condition or is reset. If CLKIN is stopped, the specified RESET low time must be provided once CLKIN restarts and has stabilized. (2) Case temperatures are ``Instant On''. 4.3 Recommended Connections Power and ground connections must be made to multiple VCC and VSS (GND) pins. Every 80960CFbased circuit board should include power (VCC) and ground (VSS) planes for power distribution. Every VCC pin must be connected to the power plane, and every VSS pin must be connected to the ground plane. Pins identified as ``N.C.'' must not be connected in the system. Liberal decoupling capacitance should be placed near the 80960CF. The processor can cause transient power surges when its numerous output buffers transition, particularly when connected to large capacitive loads. 22 Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance can be reduced by shortening board traces between the processor and decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages will offer the lowest possible inductance. For reliable operation, always connect unused inputs to an appropriate signal level. In particular, any unused interrupt (XINT, NMI) or DMA (DREQ) input should be connected to VCC through a pull-up resistor, as should BTERM if not used. Pull-up resistors should be in the range of 20 KX for each pin tied high. If READY or HOLD are not used, the unused input should be connected to ground. N.C. pins must always remain unconnected. Refer to the i960 CA Microprocessor Reference Manual for more information. SPECIAL ENVIRONMENT 80960CF-30, -25, -16 4.4. DC Specifications DC Characteristics (80960CF-30, -25, -16 under the conditions described in Section 4.2, Operating Conditions.) Symbol Parameter Min Max Units VIL Input Low Voltage for all pins except RESET b 0.3 0.8 V 2.0 VCC a 0.3 V 0.45 V Notes VIH Input High Voltage for all pins except RESET VOL Output Low Voltage VOH Output High Voltage VILR Input Low Voltage for RESET b 0.3 1.5 V VIHR Input High Voltage for RESET 3.5 VCC a 0.3 V g 15 mA 0V s VIN s VCC (1) ILI1 ILI2 ILI3 IOH e b 1mA IOH e b 200mA 2.4 VCC b 0.5 Input Leakage Current for each pin except : BTERM, ONCE, DREQ3:0, STEST, EOP3:0/TC3:0, NMI, XINT7:0, READY, HOLD, BOFF, CLKMODE IOL e 5 mA V V Input Leakage Current for: BTERM, ONCE, DREQ3:0, STEST, EOP3:0/TC3:0, NMI, XINT7:0, BOFF 0 b 325 mA VIN e 0.45V (2) Input Leakage Current for: READY, HOLD, CLKMODE 0 500 mA VIN e 2.4V (3) ILO Output Leakage Current g 15 mA 0.45V s VOUT s VCC ICC Supply Current (80960CF-30) ICC Max ICC Typ 1150 960 mA (4) (5) Supply Current (80960CF-25) ICC Max ICC Typ 950 775 mA (4) (5) Supply Current (80960CF-16) ICC Max ICC Typ 750 575 mA (4) (5) ONCE-mode Supply Current 150 mA 12 pF FC e 1 MHz ICC ICC IONCE CIN Input Capacitance for: CLKIN, RESET, ONCE, READY, HOLD, DREQ3:0, BOFF XINT7:0, NMI, BTERM, CLKMODE 0 COUT Output Capacitance of each output pin 12 pF FC e 1 MHz, (6) CI/O I/O Pin Capacitance 12 pF FC e 1 MHz NOTES: (1) No Pull-up or pull-down. (2) These pins have internal pullup resistors. (3) These pins have internal pulldown resistors. (4) Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions described in Section 4.5.1, AC Test Conditions. (5) ICC Typical is not tested. (6) Output Capacitance is the capacitive load of a floating output. (7) CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted. 23 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 4.5 AC Specifications AC Characteristics 80960CF-30 (80960CF-30 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) See notes which follow this table. Symbol Parameter Min Max Units Notes 0 60.6 MHz (1) 33 16.5 125 % ns ns (1,12) (1) INPUT CLOCK(10) TF CLKIN Frequency TC CLKIN Period In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) TCS CLKIN Period Stability In 1-x Mode (fCLK1x) g 0.1% D (1,13) TCH CLKIN High Time In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 6 6 62.5 % ns ns (1,12) (1) TCL CLKIN Low Time In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 6 6 62.5 % ns ns (1,12) (1) TCR CLKIN Rise Time 0 6 ns (1) TCF CLKIN Fall Time 0 6 ns (1) b2 2 25 ns ns (1,3,13,14) (1,3) ns ns (1,13) (1,3) OUTPUT CLOCKS(9) TCP T CLKIN to PCLK2:1 Delay PCLK2:1 Period In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 2 In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) TC 2TC TPH PCLK2:1 High Time (T/2) b 2 T/2 ns (1,13) TPL PCLK2:1 Low Time (T/2) b 2 T/2 ns (1,13) TPR PCLK2:1 Rise Time 1 4 ns (1,3) TPF PCLK2:1 Fall Time 1 4 ns (1,3) 3 3 6 3 4 5 3 4 4 4 3 T/2 a 3 2 3 14 16 18 18 16 16 16 16 16 18 16 T/2 a 14 14 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 22 ns (6) SYNCHRONOUS OUTPUTS(10) TOV TOH TOF Output Valid Delay, Output Hold TOV1, TOH1 A31:2 BE3:0 TOV2, TOH2 TOV3, TOH3 ADS TOV4, TOH4 W/R TOV5, TOH5 D/C, SUP, DMA BLAST, WAIT TOV6, TOH6 TOV7, TOH7 DEN TOV8, TOH8 HOLDA, BREQ LOCK TOV9, TOH9 DACK3:0 TOV10, TOH10 TOV11, TOH11 D31:0 TOV12, TOH12 DT/R TOV13, TOH13 FAIL EOP/TC3:0 TOV14, TOH14 Output Float for all outputs (6, 11) (6, 11) SYNCHRONOUS INPUTS(10) TIS TIH 24 Input Setup TIS1 TIS2 TIS3 TIS4 D31:0 BOFF BTERM/READY HOLD 3 17 7 7 ns ns ns ns (1,11) (1,11) (1,11) (1,11) Input Hold TIH1 TIH2 TIH3 TIH4 D31:0 BOFF BTERM/READY HOLD 5 5 2 3 ns ns ns ns (1,11) (1,11) (1,11) (1,11) SPECIAL ENVIRONMENT 80960CF-30, -25, -16 AC Characteristics 80960CF-30 (80960CF-30 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) See notes which follow this table. (Continued) Symbol Parameter Min Max Units Notes RELATIVE OUTPUT TIMINGS(9,7) TAVSH1 A31:2 Valid to ADS Rising Tb4 Ta4 ns TAVSH2 BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising Tb6 Ta6 ns TAVEL1 A31:2 Valid to DEN Falling Tb4 Ta4 ns TAVEL2 BE3:0, W/R, SUP, INST, DMA, DACK3:0 Valid to DEN Falling Tb6 TNLQV WAIT Falling to Output Data Valid TDVNH Output Data Valid to WAIT Rising TNLNH WAIT Falling to WAIT Rising TNHQX Output Data Hold after WAIT Rising TEHTV TTVEL Ta6 g6 ns ns N*T b 6 N*T a 6 N*T g 4 ns (4) ns (4) (N a 1) * T b 6 (N a 1) * T a 6 ns (5) DT/R Hold after DEN High T/2 b 6 % ns (6) DT/R Valid to DEN Falling T/2 b 4 T/2 a 4 ns (7) RELATIVE INPUT TIMINGS(7) TIS5 RESET Input Setup (2x Clock Mode) 6 ns (14) TIH5 RESET Input Hold (2x Clock Mode) 5 ns (14) TIS6 DREQ3:0 Input Setup 12 ns (8) TIH6 DREQ3:0 Input Hold 7 ns (8) TIS7 XINT7:0, NMI Input Setup 7 ns (8) TIH7 XINT7:0, NMI Input Hold 3 ns (8) TIS8 RESET Input Setup (1x Clock Mode) 3 ns (15) TIH8 RESET Input Hold (1x Clock Mode) T/4 a 1 ns (15) NOTES: 1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions. 2. See Figure 22 for capacitive derating information for output delays and hold times. 3. See Figure 23 for capacitive derating information for rise and fall times. 4. Where N is the number of NRAD, NRDD, NWAD, or NWDD wait states that are programmed in the Bus Controller Region Table. When there are no wait states in an access, WAIT never goes active. 5. N e Number of wait states inserted with READY. 6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. See Notes 1, 2 and 3. 8. Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in order to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1 the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor. 9. These specifications are guaranteed by the processor. 10. These specifications must be met by the system for proper operation of the processor. 11. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3 to adjust the timing for PCLK2:1 loading. 12. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in reset, the input clock may stop even in 1-x mode. 13. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than g 0.1% between adjacent cycles. 14. In 2x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 28a.) 15. In 1x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must be deasserted while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN. (See Figure 28b.) 25 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 AC Characteristics 80960CF-25 (80960CF-25 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Notes 0 50 MHz (1) 40 20 125 % ns ns (1,12) (1) INPUT CLOCK(10) TF CLKIN Frequency TC CLKIN Period In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) TCS CLKIN Period Stability In 1-x Mode (fCLK1x) g 0.1% D (1,13) TCH CLKIN High Time In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 8 8 62.5 % ns ns (1,12) (1) TCL CLKIN Low Time In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 8 8 62.5 % ns ns (1,12) (1) TCR CLKIN Rise Time 0 6 ns (1) TCF CLKIN Fall Time 0 6 ns (1) b2 2 25 ns ns (1,3,13,14) (1,3) ns ns (1,13) (1,3) OUTPUT CLOCKS(9) TCP CLKIN to PCLK2:1 Delay In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 2 T PCLK2:1 Period In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) TC 2TC TPH PCLK2:1 High Time (T/2) b 3 T/2 ns (1,13) TPL PCLK2:1 Low Time (T/2) b 3 T/2 ns (1,13) TPR PCLK2:1 Rise Time 1 4 ns (1,3) TPF PCLK2:1 Fall Time 1 4 ns (1,3) 3 3 6 3 4 5 3 4 4 4 3 T/2 a 3 2 3 16 18 20 20 18 18 18 18 18 20 18 T/2 a 16 16 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns (6, 11) 3 22 ns (6) SYNCHRONOUS OUTPUTS(10) TOV TOH Output Valid Delay, Output Hold TOV1, TOH1 TOV2, TOH2 TOV3, TOH3 TOV4, TOH4 TOV5, TOH5 TOV6, TOH6 TOV7, TOH7 TOV8, TOH8 TOV9, TOH9 TOV10, TOH10 TOV11, TOH11 TOV12, TOH12 TOV13, TOH13 TOV14, TOH14 TOF Output Float for all outputs (6, 11) A31:2 BE3:0 ADS W/R D/C,SUP,DMA BLAST, WAIT DEN HOLDA, BREQ LOCK DACK3:0 D31:0 DT/R FAIL EOP3:0/TC3:0 SYNCHRONOUS INPUTS(10) TIS TIH 26 Input Setup TIS1 TIS2 TIS3 TIS4 D31:0 BOFF BTERM/READY HOLD 5 19 9 9 ns ns ns ns (1,11) (1,11) (1,11) (1,11) Input Hold TIH1 TIH2 TIH3 TIH4 D31:0 BOFF BTERM/READY HOLD 5 7 2 5 ns ns ns ns (1,11) (1,11) (1,11) (1,11) SPECIAL ENVIRONMENT 80960CF-30, -25, -16 AC Characteristics 80960CF-25 (80960CF-25 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) (Continued) Symbol Parameter Min Max Units Notes RELATIVE OUTPUT TIMINGS(9,7) TAVSH1 A31:2 Valid to ADS Rising Tb4 Ta4 ns TAVSH2 BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising Tb6 Ta6 ns TAVEL1 A31:2 Valid to DEN Falling Tb4 Ta4 ns TAVEL2 BE3:0, W/R, SUP, INST, DMA, DACK3:0 Valid to DEN Falling Tb6 Ta6 TNLQV WAIT Falling to Output Data Valid TDVNH Output Data Valid to WAIT Rising TNLNH WAIT Falling to WAIT Rising TNHQX Output Data Hold after WAIT Rising TEHTV DT/R Hold after DEN High TTVEL DT/R Valid to DEN Falling g6 ns ns N*T b 6 N*T a 6 N*T g 4 ns (4) ns (4) (N a 1) * T a 6 ns (5) T/2 b 6 % ns (6) T/2 b 4 T/2 a 4 ns (7) 8 ns (14) (14) (N a 1) * T b 6 RELATIVE INPUT TIMINGS(7) TIS5 RESET Input Setup (2x Clock Mode TIH5 RESET Input Hold (2x Clock Mode) 7 ns TIS6 DREQ3:0 Input Setup 14 ns (8) TIH6 DREQ3:0 Input Hold 9 ns (8) TIS7 XINT7:0, NMI Input Setup 9 ns (8) TIH7 XINT7:0, NMI Input Hold 5 ns (8) TIS8 RESET Input Setup (1x Clock Mode) 3 ns (15) TIH8 RESET Input Hold (1x Clock Mode) T/4 a 1 ns (15) NOTES: (1) See Section 4.5.2, AC Timing Waveforms for waveforms and definitions. (2) See Figure 22 for capacitive derating information for output delays and hold times. (3) See Figure 23 for capacitive derating information for rise and fall times. (4) Where N is the number of NRAD, NRDD, NWAD, or NWDD wait states that are programmed in the Bus Controller Region Table. When there are no wait states in an access, WAIT never goes active. (5) N e Number of wait states inserted with READY. (6) Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity. (7) See Notes 1, 2 and 3. (8) Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in order to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1 the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor. (9) These specifications are guaranteed by the processor. (10) These specifications must be met by the system for proper operation of the processor. (11) This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3 to adjust the timing for PCLK2:1 loading. (12) In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in reset, the input clock may stop even in 1-x mode. (13) When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than g 0.1% between adjacent cycles. (14) In 2x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 28a.) (15) In 1x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must be deasserted while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN. (See Figure 28b.) 27 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 AC Characteristics 80960CF-16 (80960CF-16 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) (Continued) Symbol Parameter Min Max Units Notes 0 32 MHz (1) 62.5 31.25 125 % ns ns (1,12) (1) INPUT CLOCK(10) TF CLKIN Frequency TC CLKIN Period In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) TCS CLKIN Period Stability In 1-x Mode (fCLK1x) g 0.1% D (1,13) TCH CLKIN High Time In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 10 10 62.5 % ns ns (1,12) (1) TCL CLKIN Low Time In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 10 10 62.5 % ns ns (1,12) (1) TCR CLKIN Rise Time 0 6 ns (1) TCF CLKIN Fall Time 0 6 ns (1) b2 2 25 ns ns (1,3,13,14) (1,3) ns ns (1,13) (1,3) OUTPUT CLOCKS(9) TCP T CLKIN to PCLK2:1 Delay PCLK2:1 Period In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 2 In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) TC 2TC TPH PCLK2:1 High Time (T/2) b 4 T/2 ns (1,13) TPL PCLK2:1 Low Time (T/2) b 4 T/2 ns (1,13) TPR PCLK2:1 Rise Time 1 4 ns (1,3) TPF PCLK2:1 Fall Time 1 4 ns (1,3) 3 3 6 3 4 5 3 4 4 4 3 T/2 a 3 2 3 18 20 22 22 20 20 20 20 20 22 20 T/2 a 18 18 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns (6, 11) 3 22 ns (6) SYNCHRONOUS OUTPUTS(10) TOV TOH Output Valid Delay, Output Hold TOV1, TOH1 A31:2 BE3:0 TOV2, TOH2 TOV3, TOH3 ADS W/R TOV4, TOH4 TOV5, TOH5 D/C, SUP, DMA BLAST, WAIT TOV6, TOH6 TOV7, TOH7 DEN TOV8, TOH8 HOLDA, BREQ LOCK TOV9, TOH9 DACK3:0 TOV10, TOH10 TOV11, TOH11 D31:0 DT/R TOV12, TOH12 TOV13, TOH13 FAIL EOP3:0/TC3:0 TOV14, TOH14 TOF Output Float for all outputs (6, 11) SYNCHRONOUS INPUTS(10) TIS TIH 28 Input Setup TIS1 TIS2 TIS3 TIS4 D31:0 BOFF BTERM/READY HOLD 5 21 9 9 ns ns ns ns (1,11) (1,11) (1,11) (1,11) Input Hold TIH1 TIH2 TIH3 TIH4 D31:0 BOFF BTERM/READY HOLD 5 7 2 5 ns ns ns ns (1,11) (1,11) (1,11) (1,11) SPECIAL ENVIRONMENT 80960CF-30, -25, -16 AC Characteristics 80960CF-16 (80960CF-16 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) (Continued) Symbol Parameter Min Max Units Tb4 Ta4 ns Notes RELATIVE OUTPUT TIMINGS(9,7) TAVSH1 A31:2 Valid to ADS Rising TAVSH2 BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising Tb6 Ta6 ns TAVEL1 A31:2 Valid to DEN Falling Tb6 Ta6 ns TAVEL2 BE3:0, W/R, SUP, INST, DMA, DACK3:0 Valid to DEN Falling Tb6 Ta6 ns TNLQV WAIT Falling to Output Data Valid TDVNH Output Data Valid to WAIT Rising TNLNH WAIT Falling to WAIT Rising TNHQX Output Data Hold after WAIT Rising TEHTV TTVEL g6 ns N*T b 6 N*T a 6 N*T g 4 ns (4) ns (4) (N a 1) * T b 6 (N a 1) * T a 6 ns (5) DT/R Hold after DEN High T/2 b 6 % ns (6) DT/R Valid to DEN Falling T/2 b 4 T/2 a 4 ns (7) RELATIVE INPUT TIMINGS(7) TIS5 RESET Input Setup (2x Clock Mode) 10 ns (14) TIH5 RESET Input Hold (2x Clock Mode) 9 ns (14) TIS6 DREQ3:0 Input Setup 16 ns (8) TIH6 DREQ3:0 Input Hold 11 ns (8) TIS7 XINT7:0, NMI Input Setup 9 ns (8) TIH7 XINT7:0, NMI Input Hold 5 ns (8) TIS8 RESET Input Setup (1x Clock Mode) 3 ns (15) TIH8 RESET Input Hold (1x Clock Mode) T/4 a 1 ns (15) NOTES: (1) See Section 4.5.2, AC Timing Waveforms for waveforms and definitions. (2) See Figure 22 for capacitive derating information for output delays and hold times. (3) See Figure 23 for capacitive derating information for rise and fall times. (4) Where N is the number of NRAD, NRDD, NWAD, or NWDD wait states that are programmed in the Bus Controller Region Table. When there are no wait states in an access, WAIT never goes active. (5) N e Number of wait state inserted with READY. (6) Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity. (7) See Notes 1, 2 and 3. (8) Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in order to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1 the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor. (9) These specifications are guaranteed by the processor. (10) These specifications must be met by the system for proper operation of the processor. (11) This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Figure 22 to adjust the timing for PCLK2:1 loading. (12) In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in reset, the input clock may stop even in 1-x mode. (13) When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than g 0.1% between adjacent cycles. (14) In 2x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 28a.) (15) In 1x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must be deasserted while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN. (See Figure 28b.) 29 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 The AC Specifications in Section 4.5 are tested with the 50 pf load shown in Figure 9. See Figure 16 to see how timings vary with load capacitance. 4.5.1. AC TEST CONDITIONS Specifications are measured at the 1.5V crossing point, unless otherwise indicated. Input waveforms are assumed to have a rise-and-fall time of s 2 ns from 0.8V to 2.0V. See Section 4.5.2, AC Timing Waveforms for AC spec definitions, test points and illustrations. CL e 50 pf for all signals 271328 - 8 Figure 9. AC Test Load 4.5.2. AC TIMING WAVEFORMS 271328 - 9 Figure 10a. Input and Output Clocks Waveform 271328 - 10 Figure 10b. CLKIN Waveform 30 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 11 Figure 11. Output Delay and Float Waveform 271328 - 12 Figure 12a. Input Setup and Hold Waveform 271328 - 13 271328 - 14 Figure 12b. NMI, XINT7:0 Input Setup and Hold Waveform 31 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 15 Figure 13. Hold Acknowledge Timings 271328 - 16 Figure 14. Bus Back-Off (BOFF) Timings 32 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 17 Figure 15. Relative Timings Waveforms 4.5.3 DERATING CURVES 271328 - 18 NOTE: PCLK Load e 50 pF Figure 16. Output Delay or Hold vs Load Capacitance 33 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 (a) All outputs except: LOCK, DMA, SUP, HOLDA, BREQ, DACK3:0, EOP3:0/TC3:0, FAIL (b) LOCK, DMA, EOP3:0/TC3:0, FAIL SUP, HOLDA, BREQ, DACK3:0, 271328 - 19 Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC 271328 - 20 ICCICC under test conditions Figure 18. ICC vs Frequency and Temperature 34 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE The following table lists the condition of each processor output pin while HOLDA is asserted (low). Table 11. Hold Acknowledge and Backoff Conditions The following table lists the condition of each processor output pin while RESET is asserted (low). Table 10. Reset Conditions Pins State During Reset (HOLDA inactive)1 Pins State During HOLDA A31:A2 Floating D31:D0 Floating A31:A2 Floating BE3:0 Floating D31:D0 Floating W/R Floating BE3:0 Driven high (Inactive) ADS Floating W/R Driven low (Read) WAIT Floating ADS Driven high (Inactive) BLAST Floating WAIT Driven high (Inactive) DT/R Floating BLAST Driven low (Active) DEN Floating DT/R Driven low (Receive) LOCK Floating DEN Driven high (Inactive) BREQ Driven (high or low) LOCK Driven high (Inactive) D/C Floating BREQ Driven low (Inactive) DMA Floating D/C Floating SUP Floating DMA Floating FAIL Driven high (Inactive) SUP Floating DACK3 Driven high (Inactive) FAIL Driven low (Active) DACK2 Driven high (Inactive) DACK3 Driven high (Inactive) DACK1 Driven high (Inactive) DACK2 Driven high (Inactive) DACK0 Driven high (Inactive) DACK1 Driven high (Inactive) EOP/TC3 Driven if output DACK0 Driven high (Inactive) EOP/TC2 Driven if output EOP/TC3 Floating (set to input mode) EOP/TC1 Driven if output EOP/TC2 Floating (set to input mode) EOP/TC0 Driven if output EOP/TC1 Floating (set to input mode) EOP/TC0 Floating (set to input mode) NOTE: (1) With regard to bus output pin state only, the Hold Acknowledge state takes precedence over the reset state. Although asserting the RESET pin will internally reset the processor, the processor's bus output pins will not enter the reset state if it has granted Hold Acknowledge to a previous HOLD request (HOLDA is active). Furthermore, the processor will grant new HOLD requests and enter the Hold Acknowledge state even while in reset. For example, if HOLDA is not active and the processor is in the reset state, then HOLD is asserted, the processor's bus pins will enter the Hold Acknowledge state and HOLDA will be granted. The processor will not be able to perform memory accesses until the HOLD request is removed, even if the RESET pin is brought high. This operation is provided to simplify boot-up synchronization among multiple processors sharing the same bus. 35 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 BUS WAVEFORMS 271328- 21 6.0 Figure 19. Cold Reset Waveform 36 271328- 22 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Figure 20. Warm Reset Waveform 37 271328- 23 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Figure 21. Entering the ONCE State 38 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 24 NOTE: Case 1 and Case 2 show two possible polarities of PCLK2:1. Figure 22a. Clock Synchronization in the 2x Clock Mode 271328 - 25 NOTE: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2XCLK. 2XCLK is an internal signal generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising edge of CLKIN. The RESET pin is sampled when PCLK is high. Figure 22b. Clock Synchronization in the 1x Clock Mode 39 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 26 Figure 23. Non-Burst, Non-Pipelined Requests without Wait States 40 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 27 Figure 24. Non-Burst, Non-Pipelined Read Request with Wait States 41 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 28 Figure 25. Non-Burst, Non-Pipelined Write Request with Wait States 42 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 29 Figure 26. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus 43 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 30 Figure 27. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus 44 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 31 Figure 28. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus 45 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 32 Figure 29. Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus 46 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 33 Figure 30. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus 47 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 34 Figure 31. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus 48 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 35 Figure 32. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus 49 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 36 Figure 33. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus 50 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 37 Figure 34. Burst, Pipelined Read Request without Wait States, 32-Bit Bus 51 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 38 Figure 35. Burst, Pipelined Read Requests with Wait States, 32-Bit Bus 52 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 39 Figure 36. Burst, Pipelined Read Requests with Wait States, 16-Bit Bus 53 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Region Table Entry 271328 - 40 Figure 37. Burst, Pipelined Read Requests with Wait States, 8-Bit Bus 54 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 41 Figure 38. Using External READY 55 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 42 NOTE: READY adds memory access time to data transfers, whether or not the bus access is a burst access. BTERM interrupts a bus access, whether or not the bus access has more data transfers pending. Either the READY signal or the BTERM signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access. Figure 39. Terminating a Burst with BTERM 56 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 43 Figure 40. BOFF Functional Timing 271328 - 44 Figure 41. HOLD Functional Timing 57 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 45 NOTES: 1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-by and some packing and unpacking modes, in which loads are followed by loads, or stores are followed by stores. 2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high. Applications are non fly-by transfers and adjacent load-stores or store-loads. 3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus accesses (defined by ADS and BLAST. Refer to User's Manual for ``access'', ``request'' definition. Figure 42. DREQ and DACK Functional Timing 271328 - 46 NOTE: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge triggered. EOP must be held for a minimum of 2 clock cycles then EOP must be deasserted within 15 clock cycles. Figure 43. EOP Functional Timing 58 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 47 NOTE: Terminal Count becomes active during the last bus request of a buffer transfer. If the last LOAD/STORE bus request is executed as multiple bus accesses, the TC will be active for the entire bus request. Refer to the User's Manual for further information. Figure 44. Terminal Count Functional Timing 271328 - 48 Figure 45. FAIL Functional Timing 59 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 49 Figure 46. A Summary of Aligned and Unaligned Transfers for Little Endian Regions 60 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 271328 - 50 Figure 47. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) 61 271328- 51 SPECIAL ENVIRONMENT 80960CF-30, -25, -16 Figure 48. Idle Bus Operation 62