SPECIAL ENVIRONMENT 80960CF-30, 80960CF- - Intel

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changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

32-BIT HIGH-PERFORMANCE SUPERSCALAR

PROCESSOR

#Socket and Object Code Compatible with 80960CA

#Two Instructions/Clock Sustained Execution

#Four 59 Mbytes/s DMA Channels with Data Chaining

#Demultiplexed 32-bit Burst Bus with Pipelining

Y32-bit Parallel Architecture

Ð Two Instructions/clock Execution

Ð Load/Store Architecture

Ð Sixteen 32-bit Global Registers

Ð Sixteen 32-bit Local Registers

Ð Manipulate 64-bit Bit Fields

Ð 11 Addressing Modes

Ð Full Parallel Fault Model

Ð Supervisor Protection Model

YFast Procedure Call/Return Model

Ð Full Procedure Call in 4 clocks

YOn-Chip Register Cache

Ð Caches Registers on Call/Ret

Ð Minimum of 6 Frames provided

Ð Up to 15 Programmable Frames

YOn-Chip Instruction Cache

Ð 4 Kbyte Two-Way Set Associative

Ð 128-bit Path to Instruction Sequencer

Ð Cache-Lock Modes

Ð Cache-Off Mode

YOn-Chip Data Cache

Ð 1 Kbyte Direct-Mapped,

Write Through

Ð 128 bits per Clock Access on

Cache Hit

YProduct Grades Available

Ð SE3: b40§Ctoa

110§C

YHigh Bandwidth On-Chip Data RAM

Ð 1 Kbytes On-Chip RAM for Data

Ð Sustain 128 bits per clock access

YFour On-Chip DMA Channels

Ð 59 Mbytes/s Fly-by Transfers

Ð 32 Mbytes/s Two-Cycle Transfers

Ð Data Chaining

Ð Data Packing/Unpacking

Ð Programmable Priority Method

Y32-Bit Demultiplexed Burst Bus

Ð 128-bit Internal Data Paths to

and

from Registers

Ð Burst Bus for DRAM Interfacing

Ð Address Pipelining Option

Ð Fully Programmable Wait States

Ð Supports 8, 16 or 32-bit Bus Widths

Ð Supports Unaligned Accesses

Ð Supervisor Protection Pin

YSelectable Big or Little Endian Byte

Ordering

YHigh-Speed Interrupt Controller

Ð Up to 248 External Interrupts

Ð 32 Fully Programmable Priorities

Ð Multi-mode 8-bit Interrupt Port

Ð Four Internal DMA Interrupts

Ð Separate, Non-maskable Interrupt Pin

Ð Context Switch in 750 ns Typical

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–1

Figure 1. 80960CF Die Photo

Special Environment 80960CF-30, -25, -16

32-Bit High Performance Superscalar Processor

CONTENTS PAGE

1.0 PURPOSE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

2.0 i960 CF PROCESSOR

OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

2.1 The C-Series Core ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

2.2 Pipelined, Burst Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

2.3 Flexible DMA Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

2.4 Priority Interrupt Controller ÀÀÀÀÀÀÀÀÀÀÀ 6

2.5 Instruction Set Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

3.0 PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀ 8

3.1 Package Introduction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

3.2 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

3.3 80960CF Pinout ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

3.4 Mechanical Data ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18

3.5 Package Thermal Specifications ÀÀÀÀ 20

3.6 Stepping Register Information ÀÀÀÀÀÀ 21

3.7 Suggested Sources for 80960CF

Accessories ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

4.0 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀ 22

4.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀ 22

4.2 Operating Conditions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

4.3 Recommended Connections ÀÀÀÀÀÀÀÀ 22

4.4 DC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

4.5 AC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

5.0 RESET, BACKOFF AND HOLD

ACKNOWLEDGE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35

6.0 BUS WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36

CONTENTS PAGE

FIGURES

Figure 1 80960CF Die Photo ÀÀÀÀÀÀÀÀÀÀÀÀ 2

Figure 2 80960CF Block Diagram ÀÀÀÀÀÀÀ 5

Figure 3 Example Pin Description

Entry ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

Figure 4a 80960CF PGA Pinout (View

from Top Side) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16

Figure 4b 80960CF PGA Pinout (View

from Bottom Side) ÀÀÀÀÀÀÀÀÀÀÀÀ 17

Figure 5 168-Lead Ceramic PGA

Package Dimensions ÀÀÀÀÀÀÀÀÀ 18

Figure 6 80960CF PGA Package

Thermal Characteristics ÀÀÀÀÀÀÀ 20

Figure 7 Measuring 80960CF PGA

Case Temperature ÀÀÀÀÀÀÀÀÀÀÀÀ 21

Figure 8 Register G0 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

Figure 9 AC Test Load ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

Figure 10a Input and Output Clocks

Waveform ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

Figure 10b CLKIN Waveform ÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

Figure 11 Output Delay and Float

Waveform ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31

Figure 12a Input Setup and Hold

Waveform ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31

Figure 12b NMI, XINT7:0 Input Setup

and Hold Waveform ÀÀÀÀÀÀÀÀÀÀ 31

Figure 13 Hold Acknowledge

Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32

Figure 14 Bus Back-Off (BOFF)

Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32

CONTENTS PAGE

Figure 15 Relative Timings

Waveforms ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

Figure 16 Output Delay or Hold vs Load

Capacitance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

Figure 17 Rise and Fall Time Derating at

Highest Operating

Temperature and Minimum

VCC ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

Figure 18 ICC vs Frequency and

Temperature ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

Figure 19 Cold Reset Waveform ÀÀÀÀÀÀÀÀÀ 36

Figure 20 Warm Reset Waveform ÀÀÀÀÀÀÀÀ 37

Figure 21 Entering the ONCE State ÀÀÀÀÀÀ 38

Figure 22a Clock Synchronization in the

2x Clock Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39

Figure 22b Clock Synchronization in the

1x Clock Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39

Figure 23 Non-Burst, Non-Pipelined

Requests without Wait

States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40

Figure 24 Non-Burst, Non-Pipelined

Read Request with Wait

States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41

Figure 25 Non-Burst, Non-Pipelined

Write Request with Wait

States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42

Figure 26 Burst, Non-Pipelined Read

Request without Wait States,

32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43

Figure 27 Burst, Non-Pipelined Read

Request with Wait States,

32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44

Figure 28 Burst, Non-Pipelined Write

Request without Wait States,

32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45

Figure 29 Burst, Non-Pipelined Write

Request with Wait States,

32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 46

Figure 30 Burst, Non-Pipelined Read

Request with Wait States,

16-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 47

CONTENTS PAGE

Figure 31 Burst, Non-Pipelined Read

Request with Wait States,

8-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48

Figure 32 Non-Burst, Pipelined Read

Request without Wait States,

32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 49

Figure 33 Non-Burst, Pipelined Read

Request with Wait States,

32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50

Figure 34 Burst, Pipelined Read

Request without Wait States,

32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51

Figure 35 Burst, Pipelined Read

Requests with Wait States,

32-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 52

Figure 36 Burst, Pipelined Read

Requests with Wait States,

16-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53

Figure 37 Burst, Pipelined Read

Requests with Wait States,

8-Bit Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 54

Figure 38 Using External READY ÀÀÀÀÀÀÀÀ 55

Figure 39 Terminating a Burst with

BTERM ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 56

Figure 40 BOFF Functional Timing ÀÀÀÀÀÀ 57

Figure 41 HOLD Functional Timing ÀÀÀÀÀÀ 57

Figure 42 DREQ and DACK Functional

Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 58

Figure 43 EOP Functional Timing ÀÀÀÀÀÀÀ 58

Figure 44 Terminal Count Functional

Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59

Figure 45 FAIL Functional Timing ÀÀÀÀÀÀÀ 59

Figure 46 A Summary of Aligned and

Unaligned Transfers for Little

Endian Regions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 60

Figure 47 A Summary of Aligned and

Unaligned Transfers for Little

Endian Regions

(Continued) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 61

Figure 48 Idle Bus Operation ÀÀÀÀÀÀÀÀÀÀÀÀ 62

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

1.0 PURPOSE

This document previews electrical characterizations

of Intel’s i960 CF embedded microprocessor (avail-

able in 33, 25 and 16 MHz). For a detailed descrip-

tion of any i960 CF processor functional topicÐoth-

er than parametric performanceÐrefer to the latest

i960 CA Microprocessor Reference Manual (Order

No. 270710) and the

i960 CF Reference Manual Ad-

dendum

(Order No. 272188).

2.0 i960 CF PROCESSOR OVERVIEW

Intel’s i960 CF microprocessor is the performance

follow-on product to the i960 CA processor. The

i960 CF product is socket- and object code-compati-

ble with the CA; this makes CA-to-CF design up-

grades straightforward. The i960 CF processor’s in-

struction cache is 4 Kbytes (CA device has 1 Kbyte);

CF data cache is 1 Kbyte (CA device has no data

cache). This extra cache on the CF product adds a

significant performance boost over the CA. The

80960CF is object code compatible with the 32-bit

80960 Core Architecture while including Special

Function Register extensions to control on-chip pe-

ripherals, and instruction set extensions to shift 64-

bit operands and configure on-chip hardware. Multi-

ple 128-bit internal busses, on-chip instruction cach-

ing and a sophisticated instruction scheduler allow

the processor to sustain execution of two instruc-

tions every clock, and peak at execution of three

instructions per clock.

A 32-bit demultiplexed and pipelined burst bus pro-

vides a 132 Mbyte/s bandwidth to a system’s high-

speed external memory sub-system. In addition, the

80960CF’s on-chip caching of instructions, proce-

dure context and critical program data substantially

decouples system performance from the wait states

associated with accesses to the system’s slower,

cost sensitive, main memory sub-system.

The 80960CF bus controller also integrates full wait

state and bus width control for highest system per-

formance with minimal system design complexity.

Unaligned access and Big Endian byte order support

reduces the cost of porting existing applications to

the 80960CF.

The processor also integrates four complete data-

chaining DMA channels and a high-speed interrupt

controller on-chip. The DMA channels perform: sin-

gle-cycle or two-cycle transfers, data packing and

unpacking, and data chaining. Block transfers, in ad-

dition to source or destination synchronized trans-

fers, are provided.

The interrupt controller provides full programmability

of 248 interrupt sources into 32 priority levels with a

typical interrupt task switch (‘‘latency’’) time of

750 ns.

271328–2

Figure 2. 80960CF Block Diagram

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

2.1. The C-Series Core

The C-Series core is a very high performance micro-

architectural implementation of the 80960 Core Ar-

chitecture. The C-Series core can sustain execution

of two instructions per clock (66 MIPs at 33 MHz).

To achieve this level of performance, Intel has incor-

porated state-of-the-art silicon technology and inno-

vative microarchitectural constructs into the imple-

mentation of the C-Series core. Factors that contrib-

ute to the core’s performance include:

Ð Parallel instruction decoding allows issue of up

to three instructions per clock.

Ð Most instructions execute in a single clock.

Ð Parallel instruction decode allows sustained,

simultaneous execution of two single-clock in-

structions every clock cycle.

Ð Efficient instruction pipeline minimizes pipeline

break losses.

Ð Register and resource scoreboarding allow

simultaneous multi-clock instruction execution.

Ð Branch look-ahead and prediction allows many

branches to execute with no pipeline break.

Ð Local Register Cache integrated on-chip caches

Call/Return context.

Ð Two-way set associative, 4 Kbyte integrated in-

struction cache.

Ð Direct mapped, 1 Kbyte data cache, write

through, write allocate.

Ð 1 Kbyte integrated Data RAM sustains a four-

word (128-bit) access every clock cycle.

2.2. Pipelined, Burst Bus

A 32-bit high performance bus controller interfaces

the 80960CF to external memory and peripherals.

The Bus Control Unit features a maximum transfer

rate of 132 Mbytes per second (at 33 MHz). Internal-

ly programmable wait states and 16 separately con-

figurable memory regions allow the processor to in-

terface with a variety of memory subsystems with a

minimum of system complexity and a maximum of

performance. The Bus Controller’s main features in-

clude:

Ð Demultiplexed, Burst Bus to exploit most efficient

DRAM access modes.

Ð Address Pipelining to reduce memory cost while

maintaining performance.

Ð 32-, 16- and 8-bit modes for I/O interfacing ease.

Ð Full internal wait state generation to reduce sys-

tem cost.

Ð Little and Big Endian support to ease application

development.

Ð Unaligned access support for code portability.

Ð Three-deep request queue to decouple the bus

from the core.

2.3. Flexible DMA Controller

A four channel DMA controller provides high speed

DMA control for data transfers involving peripherals

and memory. The DMA provides advanced features

such as data chaining, byte assembly and disassem-

bly, and a high performance fly-by mode capable of

transfer speed of up to 59 Mbytes per second at

33 MHz. The DMA controller features a performance

and flexibility which is only possible by integrating

the DMA controller and the 80960CF core.

2.4. Priority Interrupt Controller

A programmable-priority interrupt controller man-

ages up to 248 external sources through the 8-bit

external interrupt port. The Interrupt Unit also han-

dles the four internal sources from the DMA control-

ler, and a single non-maskable interrupt input. The

8-bit interrupt port can also be configured to provide

individual interrupt sources that are level or edge

triggered.

Interrupts in the 80960CF are prioritized and sig-

naled within 270 ns of the request. If the interrupt is

of higher priority than the processor priority, the con-

text switch to the interrupt routine typically is com-

plete in another 480 ns. The interrupt unit provides

the mechanism for the low latency and high through-

put interrupt service which is essential for embedded

applications.

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

2.5. Instruction Set Summary

The following table summarizes the 80960CF instruction set by logical groupings. See the

i960 CA Microproc-

essor Reference Manual

for a complete description of the instruction set.

Data Arithmetic Logical Bit, Bit Field

Movement and Byte

Load Add And Set Bit

Store Subtract Not And Clear Bit

Move Multiply And Not Not Bit

Load Address Divide Or Alter Bit

Remainder Exclusive Or Scan for Bit

Modulo Not Or Span over Bit

Shift Or Not Extract

*Extended Nor Modify

Shift Exclusive Nor Scan Byte for Equal

Extended Not

Multiply Nand

Extended

Divide

Add with

Carry

Subtract with

Carry

Rotate

Comparison Branch Call and Return Fault

Compare Unconditional Call Conditional

Conditional Branch Call Extended Fault

Compare Conditional Call System Synchronize

Compare and Branch Return Faults

Increment Compare and Branch and Link

Compare and Branch

Decrement

Test Condition Code

Check Bit

Debug Processor Atomic

Management

Modify Trace Modify Atomic Add

Controls Process Atomic Modify

Mark Controls

Force Mark Modify

Arithmetic

Controls

*System Control

*DMA Control

Flush Local

Registers

NOTE:

Instructions marked by (*) are 80960CF extensions to the 80960 instruction set.

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

3.0 PACKAGE INFORMATION

3.1. Package Introduction

This section describes the pins, pinouts and thermal

characteristics for the 80960CF in the 168-pin Ce-

ramic Pin Grid Array (PGA) package. For complete

package specifications and information, see the Intel

Packaging Outlines and Dimensions Guide

(Order

No. 231369).

3.2. Pin Descriptions

The 80960CF pins are described in this section. Ta-

ble 1 presents the legend for interpreting the pin de-

scriptions in the following tables.

Pins associated with the 32-bit demultiplexed proc-

essor bus are described in Table 2. Pins associated

with basic processor configuration and control are

described in Table 3. Pins associated with the

80960CF DMA Controller and Interrupt Unit are de-

scribed in Table 4.

Figure 3 provides an example pin description table

entry. ‘‘I/O’’ signifies that data pins are input-output.

‘‘S’’ indicates pins are synchronous to PCLK2:1.

‘‘H(Z)’’ indicates that these pins float while the proc-

essor bus is in a Hold Acknowledge state. ‘‘R(Z)’’

indicates that the pins also float while RESET is low.

All pins float while the processor is in the ONCE

mode.

Table 1. Pin Description Nomenclature

Symbol Description

I Input only pin

O Output only pin

I/O Pin can be either an input or output

- Pins ‘‘must be’’ connected as

described

S(...) Synchronous. Inputs must meet setup

and hold times relative to PCLK2:1 for

proper operation. All outputs are

synchronous to PCLK2:1.

S(E) Edge sensitive input

S(L) Level sensitive input

A(...) Asynchronous. Inputs may be

asynchronous to PCLK2:1.

A(E) Edge sensitive input

A(L) Level sensitive input

H(...) While the processor’s bus is in the

Hold Acknowledge or Bus Backoff

state, the pin:

H(1) is driven to VCC

H(0) is driven to VSS

H(Z) floats

H(Q) continues to be a valid output

R(...) While the processor’s RESET pin is

low, the pin

R(1) is driven to VCC

R(0) is driven to VSS

R(Z) floats

R(Q) continues to be a valid output

Name Type Description

D31:0 I/O DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configuration.

The least significant bit of the data is carried on D0 and the most significant on D31. When

S(L)

the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit bus

H(Z) widths, D15:0 are used. For 32-bit bus widths the full data bus is used.

R(Z)

Figure 3. Example Pin Description Entry

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Table 2. 80960CF Pin DescriptionÐExternal Bus Signals

Name Type Description

A31:2 O ADDRESS BUS carries the physical address upper 30 bits. A31 is the most

significant address bit and A2 is the least significant. During a bus access, A31:2

identify all external addresses to word (4-byte) boundaries. The byte enable

H(Z) signals indicate the selected byte in each word. During burst accesses, A3 and A2

R(Z) increment to indicate successive data cycles.

D31:0 I / O DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width

configuration. The least significant bit of the data is carried on D0 and the most

S(L)

significant on D31. When the bus is configured for 8-bit data, the lower 8 data

H(Z) lines, D7:0 are used. For 16-bit bus widths, D15:0 are used. For 32-bit bus widths

R(Z) the full data bus is used.

BE3 O BYTE ENABLES select which of the four bytes addressed by A31:2 are active

during an access to a memory region configured for a 32-bit data-bus width. BE3

BE2 S

applies to D31:24; BE2 applies to D23:16; BE1 applies to D15:8; and BE0 applies

BE1 H(Z) to D7:0.

BE0 R(1) 32-bit bus: BE3 –Byte Enable 3 –enable D31:24

BE2 –Byte Enable 2 –enable D23:16

BE1 –Byte Enable 1 –enable D15:8

BE0 –Byte Enable 0 –enable D7:0

For accesses to a memory region configured for a 16-bit data-bus width, the

processor directly encodes BE3, BE1 and BE0 to provided BHE, A1 and BLE

respectively.

16-bit bus: BE3 –Byte High Enable (BHE) –enable D15:8

BE2 –Not used (is driven high or low)

BE1 –Address Bit 1 (A1)

BE0 –Byte Low Enable (BLE) –enable D7:0

For accesses to a memory region configured for an 8-bit data bus width, the

processor directly encodes BE1 and BE0 to provide A1 and A0 respectively.

8-bit bus: BE3 – Not used (is driven high or low)

BE2 –Not used (is driven high or low)

BE1 –Address Bit 1 (A1)

BE0 – Address Bit 0 (A0)

W/R O WRITE/READ is asserted for read requests and deasserted for write requests.

The W/R signal changes in the same clock cycle as ADS. It remains valid for the

entire access in non-pipelined regions. In pipelined regions, W/R is not

H(Z) guaranteed valid in the last cycle of a read access.

R(0)

ADS O ADDRESS STROBE indicates valid address and the start of a new bus access.

ADS is asserted for the first clock of a bus access.

H(Z)

R(1)

READY I READY is an input which signals the termination of a data transfer. READY is

used to indicate that read data on the bus is valid, or that a write-data transfer has

S(L)

completed. The READY signal works in conjunction with the internally

H(Z) programmed wait-state generator. If READY is enabled in a region, the pin is

R(Z) sampled after the programmed number of wait-states has expired. If the READY

pin is deasserted, wait states continue to be inserted until READY becomes

asserted. This is true for the NRAD,N

RDD,N

WAD, and NWDD wait states. The

NXDA wait states cannot be extended.

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Table 2. 80960CF Pin DescriptionÐExternal Bus Signals (Continued)

Name Type Description

BTERM I BURST TERMINATEÐThe burst terminate signal breaks up a burst access and

causes another address cycle to occur. The BTERM signal works in conjunction

S(L)

with the internally programmed wait-state generator. If READY and BTERM are

H(Z)

enabled in a region, the BTERM pin is sampled after the programmed number of

R(Z) wait states has expired. When BTERM is asserted, a new ADS signal is generated

and the access is completed. The READY input is ignored when BTERM is

asserted. BTERM must be externally synchronized to satisfy the BTERM setup

and hold times.

WAIT O WAIT indicates internal wait state generator status. WAIT is asserted when wait

states are being caused by the internal wait state generator and not by the

READY or BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT

H(Z)

can also be thought of as a READY output that the processor provides when it is

R(1) inserting wait states.

BLAST O BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the

last data transfer of burst and non-burst accesses after the wait state counter

reaches zero. BLAST remains asserted until the clock following the last cycle of

H(Z)

the last data transfer of a bus access. If the READY or BTERM input is used to

R(0) extend wait states, the BLAST signal remains asserted until READY or BTERM

terminates the access.

DT/R O DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is

used in conjunction with DEN to provide control for data transceivers attached to

the external bus. When DT/R is asserted, the signal indicates that the processor

H(Z)

receives data. Conversely, when deasserted, the processor sends data. DT/R

R(0) changes only while DEN is high.

DEN O DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the

start of the bus request first data cycle and is deasserted at the end of the last

data cycle. DEN is used in conjunction with DT/R to provide control for data

H(Z)

transceivers attached to the external bus. DEN remains asserted for sequential

R(1) reads from pipelined memory regions. DEN is deasserted when DT/R changes.

LOCK O BUS LOCK indicates that an atomic read-modify-write operation is in progress.

LOCK may be used to prevent external agents from accessing memory which is

currently involved in an atomic operation. LOCK is asserted in the first clock of an

H(Z)

atomic operation, and deasserted in the clock cycle following the last bus access

R(1) for the atomic operation. To allow the most flexibility for a memory system

enforcement of locked accesses, the processor acknowledges a bus hold request

when LOCK is asserted. The processor performs DMA transfers while LOCK is

active.

HOLD I HOLD REQUEST signals that an external agent requests access to the external

bus. The processor asserts HOLDA after completing the current bus request.

S(L)

HOLD, HOLDA and BREQ are used together to arbitrate access to the

H(Z)

processor’s external bus by external bus agents.

R(Z)

BOFF I BUS BACKOFF ÐThe backoff pin, when asserted, suspends the current access

and causes the bus pins to float. When deasserted, the ADS signal is asserted on

S(L)

the next clock cycle and the access is resumed.

H(Z)

R(Z)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Table 2. 80960CF Pin DescriptionÐExternal Bus Signals (Continued)

Name Type Description

HOLDA O HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has

relinquished control of the external bus. When HOLDA is asserted, the external

address bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA

H(1) and BREQ are used together to arbitrate access to the processor’s external bus

R(Q) by external bus agents. Since the processor grants HOLD requests and enters the

Hold Acknowledge state even while RESET is asserted, HOLDA pin state is

independent of the RESET pin.

BREQ O BUS REQUEST is asserted when the bus controller has a request pending. BREQ

can be used by external bus arbitration logic in conjunction with HOLD and

HOLDA to determine when to return mastership of the external bus to the

H(Q) processor.

R(0)

D/C O DATA OR CODE is asserted for a data request and deasserted for instruction

requests. D/C has the same timing as W/R.

H(Z)

R(Z)

DMA O DMA ACCESS indicates whether the bus request was initiated by the DMA

controller. DMA is asserted for any DMA request. DMA is deasserted for all other

requests.

H(Z)

R(Z)

SUP O SUPERVISOR ACCESS indicates whether the bus request is issued while in

supervisor mode. SUP is asserted when the request has supervisor privileges, and

is deasserted otherwise. SUP can be used to isolate supervisor code and data

H(Z) structures from non-supervisor requests.

R(Z)

Table 3. 80960CF Pin DescriptionÐProcessor Control Signals

Name Type Description

RESET I RESET causes the chip to reset. When RESET is asserted, all external signals return

to the reset state. When RESET is deasserted, initialization begins. When the 2-x clock

A(L)

mode is selected, RESET must remain asserted for 16 PCLK2:1 cycles before being

H(Z) deasserted in order to guarantee correct processor initialization. When the 1-x clock

R(Z) mode is selected, RESET must remain asserted for 10,000 PCLK2:1 cycles before

N(Z) being deasserted in order to guarantee correct initialization. The CLKMODE pin

selects 1-x or 2-x input clock division of the CLKIN pin.

The processor’s Hold Acknowledge bus state functions while the chip is reset. If the

processor’s bus is in the Hold Acknowledge state when RESET is asserted, the

processor will internally reset, but maintains the Hold Acknowledge state on external

pins until the Hold request is removed. If a hold request is made while the processor is

in the reset state, the processor bus grants HOLDA and enters the Hold Acknowledge

state.

FAIL O FAIL indicates failure of the processor’s self-test performed at initialization. When

RESET is deasserted and the processor begins initialization, the FAIL pin is asserted.

An internal self-test is performed as part of the initialization process. If this self-test

H(Q) passes, the FAIL pin is deasserted otherwise it remains asserted. The FAIL pin is

R(0) reasserted while the processor performs an external bus self-confidence test. If this

self-test passes, the processor deasserts the FAIL pin and branches to the user’s

initialization routine; otherwise the FAIL pin remains asserted. Internal self-test and the

use of the FAIL pin can be disabled with the STEST pin.

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Table 3. 80960CF Pin DescriptionÐProcessor Control Signals (Continued)

Name Type Description

STEST I SELF TEST causes the processor’s internal self-test feature to be enabled or

disabled at initialization. STEST is read on the rising edge of RESET. When asserted,

S(L)

the processor’s internal self-test and external bus confidence tests are performed

H(Z) during processor initialization. When deasserted, only the external bus confidence

R(Z) tests are performed during initialization.

ONCE I ON CIRCUIT EMULATION causes all outputs to be floated when asserted. ONCE is

continuously sampled while RESET is low, and is latched on the rising edge of

A(L)

RESET. To place the processor in the ONCE state:

H(Z)

(1) assert RESET and ONCE (order does not matter)

R(Z)

(2) wait for at least 16 CLKIN periods in 2-x mode, or 10,000 CLKIN periods in 1-x

mode, after VCC and CLKIN are within operating specifications

(3) deassert RESET

(4) wait at least 32 CLKIN periods

(The processor is now latched in the ONCE state as long as RESET is high.)

To exit the ONCE state, bring VCC and CLKIN to operating conditions, then assert

RESET and bring ONCE high prior to deasserting RESET.

CLKIN must operate within the specified operating conditions of the processor until

step 4 above is completed. The CLKIN may then be changed to DC to achieve the

lowest possible ONCE mode leakage current.

ONCE can be used by emulator products or for board testers to effectively make an

installed processor transparent in the board.

CLKIN I CLOCK INPUT is an input for the external clock needed to run the processor. The

external clock is internally divided as prescribed by the CLKMODE pin to produce

A(E)

PCLK2:1.

H(Z)

R(Z)

CLKMODE I CLOCK MODE selects the division factor applied to the external clock input (CLKIN).

When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the

A(L)

processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to create

H(Z) PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high or low in

R(Z) a system, as the clock mode is not latched by the processor. If left unconnected, the

processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode.

PCLK2 O PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and

outputs of the processor. All inputs and output timings are specified in relation to

PCLK1 S

PCLK2 and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are

H(Q) provided to allow flexibility in the system’s allocation of capacitive loading on the

R(Q) clock. PCLK2:1 may also be connected at the processor to form a single clock signal.

VSS Ð GROUND connections consist of 24 pins which must be connected externally to a

VSS board plane.

VCC Ð POWER connections consist of 24 pins which must be connected externally to a VCC

board plane.

VCCPLL ÐV

CCPLL is a separate VCC supply pin for the phase lock loop used in 1x clock mode.

Connecting a simple low pass filter to VCCPLL may help reduce clock jitter (TCP)in

noisy environments. Otherwise, VCCPLL should be connected to VCC.

N/C Ð NO CONNECT pins must not be connected in a system.

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Table 4. 80960CF Pin DescriptionÐDMA and Interrupt Unit Control Signals

Name Type Description

DREQ3 I DMA REQUEST causes a DMA transfer to be requested. Each of the four signals

request a transfer on a single channel. DREQ0 requests channel 0, DREQ1 requests

DREQ2 A(L)

channel 1, etc. When two or more channels are requested simultaneously, the

DREQ1 H(Z) channel with the highest priority is serviced first. Channel priority mode is

DREQ0 R(Z) programmable.

DACK3 O DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of the

four signals acknowledge a transfer for a single channel. DACK0 acknowledges

DACK2 S

channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted when the

DACK1 H(1) requesting device of a DMA is accessed.

DACK0 R(1)

EOP3/TC3 I / O END OF PROCESS/TERMINAL COUNT can be programmed as either an input

(EOP3:0) or as an output (TC3:0), but not both. Each pin is individually

EOP2/TC2 A(L)

programmable. When programmed as an input, EOPx causes the termination of a

EOP1/TC1 H(Z/Q) current DMA transfer for the channel corresponding to the EOPx pin. EOP0

EOP0/TC0 R(Z) corresponds to channel 0, EOP1 corresponds to channel 1, etc. When a channel is

configured for source

and

destination chaining, the EOP pin for that channel causes

termination of only the current buffer transferred and causes the next buffer to be

transferred. EOP3:0 are asynchronous inputs.

When programmed as an output, the channel’s TCx pin indicates that the channel

byte count has reached 0 and a DMA has terminated. TCx is driven with the same

timing as DACKx during the last DMA transfer for a buffer. If the last bus request is

executed as multiple bus accesses, TCx remains asserted for the entire bus request.

XINT7 I EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins can be

configured in three modes.

XINT6 A(E/L)

In Dedicated Mode, each pin is a dedicated external interrupt source. Dedicated

XINT5 H(Z)

inputs can be individually programmed to be level (low) or edge (falling) activated.

XINT4 R(Z)

In Expanded Mode, the 8 pins act together as an 8-bit vectored interrupt source. The

XINT3 interrupt pins in this mode are level activated. Since the interrupt pins are active low,

XINT2 the vector number requested is the one’s complement of the positive logic value

XINT1 place on the port. This eliminates glue logic to interface to combinational priority

XINT0 encoders which output negative logic.

In Mixed Mode, XINT7:5 are dedicated sources and XINT4:0 act as the 5 most

significant bits of an expanded mode vector. The least significant bits are set to 010

internally.

NMI I NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.

NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated

A(E)

source.

H(Z)

R(Z)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

3.3. 80960CF Pinout

3.3.1 80960CF PGA PINOUT

Tables 5 and 6 list the 80960CF pin names with

package location. Figure 4-a depicts the complete

80960CF pinout as viewed from the top side of the

component (i.e., pins facing down). Figure 4b shows

the complete 80960CF pinout as viewed from the

pin-side of the package (i.e., pins facing up). See

Section 4.0, Electrical Specifications for specifica-

tions and recommended connections.

Table 5. PGA Pin Name with Package Location (Signal Order)

Address Bus Data Bus Bus Control Processor Control I/O

Name ÀÀLocation Name ÀÀLocation Name ÀÀLocation Name ÀÀÀÀLocation Name ÀÀLocation

A31 ÀÀÀÀÀÀÀÀS15 D31 ÀÀÀÀÀÀÀÀR03 BE3 ÀÀÀÀÀÀÀÀS05 RESET ÀÀÀÀÀÀÀA16 DREQ3 ÀÀÀÀÀA07

A30 ÀÀÀÀÀÀÀÀQ13 D30 ÀÀÀÀÀÀÀÀQ05 BE2 ÀÀÀÀÀÀÀÀS06 DREQ2 ÀÀÀÀÀB06

A29 ÀÀÀÀÀÀÀÀR14 D29 ÀÀÀÀÀÀÀÀS02 BE1 ÀÀÀÀÀÀÀÀS07 FAILÀÀÀÀÀÀÀÀÀÀA02 DREQ1 ÀÀÀÀÀA06

A28 ÀÀÀÀÀÀÀÀQ14 D28 ÀÀÀÀÀÀÀÀQ04 BE0 ÀÀÀÀÀÀÀÀR09 DREQ0 ÀÀÀÀÀB05

A27 ÀÀÀÀÀÀÀÀS16 D27 ÀÀÀÀÀÀÀÀR02 STESTÀÀÀÀÀÀÀÀB02

A26 ÀÀÀÀÀÀÀÀR15 D26ÀÀÀÀÀÀÀÀQ03 W/R ÀÀÀÀÀÀÀS10 DACK3 ÀÀÀÀÀA10

A25 ÀÀÀÀÀÀÀÀS17 D25 ÀÀÀÀÀÀÀÀS01 ONCE ÀÀÀÀÀÀÀÀC03 DACK2 ÀÀÀÀÀA09

A24 ÀÀÀÀÀÀÀÀQ15 D24 ÀÀÀÀÀÀÀÀR01 ADS ÀÀÀÀÀÀÀR06 DACK1 ÀÀÀÀÀA08

A23 ÀÀÀÀÀÀÀÀR16 D23ÀÀÀÀÀÀÀÀQ02 CKLIN ÀÀÀÀÀÀÀÀC13 DACK0 ÀÀÀÀÀB08

A22 ÀÀÀÀÀÀÀÀR17 D22 ÀÀÀÀÀÀÀÀP03 READY ÀÀÀÀÀS03 CLKMODE ÀÀÀÀC14

A21 ÀÀÀÀÀÀÀÀQ16 D21 ÀÀÀÀÀÀÀÀQ01 BTERMÀÀÀÀÀR04 PCLK1 ÀÀÀÀÀÀÀÀB14 EOP/TC0 ÀÀÀA11

A20 ÀÀÀÀÀÀÀÀP15 D20 ÀÀÀÀÀÀÀÀP02 PCLK2ÀÀÀÀÀÀÀÀB13 EOP/TC1 ÀÀÀA12

A19 ÀÀÀÀÀÀÀÀP16 D19 ÀÀÀÀÀÀÀÀP01 WAITÀÀÀÀÀÀÀS12 EOP/TC2 ÀÀÀA13

A18 ÀÀÀÀÀÀÀÀQ17 D18 ÀÀÀÀÀÀÀÀN02 BLAST ÀÀÀÀÀS08 VSS EOP/TC3 ÀÀÀA14

A17 ÀÀÀÀÀÀÀÀP17 D17 ÀÀÀÀÀÀÀÀN01

Location

A16 ÀÀÀÀÀÀÀÀN16 D16ÀÀÀÀÀÀÀÀM01 DT/RÀÀÀÀÀÀÀS11 C07, C08, C09, XINT7 ÀÀÀÀÀÀC17

C10, C11, C12,

A15 ÀÀÀÀÀÀÀÀN17 D15 ÀÀÀÀÀÀÀÀL01 DEN ÀÀÀÀÀÀÀS09 XINT6 ÀÀÀÀÀÀC16

F15, G03, G15,

A14ÀÀÀÀÀÀÀÀM17 D14 ÀÀÀÀÀÀÀÀL02 XINT5 ÀÀÀÀÀÀB17

H03, H15, J03,

J15, K03, K15,

A13 ÀÀÀÀÀÀÀÀL16 D13 ÀÀÀÀÀÀÀÀK01 LOCK ÀÀÀÀÀÀS14 XINT4 ÀÀÀÀÀÀC15

L03, L15, M03,

A12 ÀÀÀÀÀÀÀÀL17 D12 ÀÀÀÀÀÀÀÀJ01 XINT3 ÀÀÀÀÀÀB16

M15, Q07, Q08,

Q09, Q10, Q11

A11 ÀÀÀÀÀÀÀÀK17 D11 ÀÀÀÀÀÀÀÀH01 HOLD ÀÀÀÀÀÀR05 XINT2 ÀÀÀÀÀÀA17

A10 ÀÀÀÀÀÀÀÀJ17 D10 ÀÀÀÀÀÀÀÀH02 HOLDA ÀÀÀÀÀS04 VCC XINT1 ÀÀÀÀÀÀA15

A9 ÀÀÀÀÀÀÀÀÀH17 D9 ÀÀÀÀÀÀÀÀÀG01 BREQ ÀÀÀÀÀÀR13

Location

XINT0 ÀÀÀÀÀÀB15

A8 ÀÀÀÀÀÀÀÀÀG17 D8 ÀÀÀÀÀÀÀÀÀF01 B07, B09,

B11, B12, C06,

A7 ÀÀÀÀÀÀÀÀÀG16 D7 ÀÀÀÀÀÀÀÀÀE01 D/C ÀÀÀÀÀÀÀÀS13 NMI ÀÀÀÀÀÀÀÀD15

E15, F03, F16,

A6 ÀÀÀÀÀÀÀÀÀF17 D6 ÀÀÀÀÀÀÀÀÀF02 DMA ÀÀÀÀÀÀÀR12 G02, H16, J02,

J16, K02, K16, M02,

A5 ÀÀÀÀÀÀÀÀÀE17 D5 ÀÀÀÀÀÀÀÀÀD01 SUP ÀÀÀÀÀÀÀQ12 M16, N03, N15,

A4 ÀÀÀÀÀÀÀÀÀE16 D4 ÀÀÀÀÀÀÀÀÀE02 Q06, R07, R08,

R10, R11

VCCPLL ÀÀÀÀÀÀÀB10

A3 ÀÀÀÀÀÀÀÀÀD17 D3 ÀÀÀÀÀÀÀÀÀC01 BOFF ÀÀÀÀÀÀB01 No Connect

A2 ÀÀÀÀÀÀÀÀÀD16 D2 ÀÀÀÀÀÀÀÀÀD02

Location

D1 ÀÀÀÀÀÀÀÀÀC02 A01, A03, A04, A05,

B03, B04, C04, C05,

D03

D0 ÀÀÀÀÀÀÀÀÀE03

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Table 6. PGA Pin Name with Package Location (Pin Order)

Address Bus Data Bus Bus Control Processor Control I/O

Location ÀÀName Location ÀÀName Location ÀÀName Location ÀÀÀÀName Location ÀÀName

A01 ÀÀÀÀÀÀÀÀÀNC C01 ÀÀÀÀÀÀÀÀÀD3 G01 ÀÀÀÀÀÀÀÀÀD9 M01 ÀÀÀÀÀÀÀÀÀD16 R01 ÀÀÀÀÀÀÀÀD24

A02 ÀÀÀÀÀÀÀFAIL C02 ÀÀÀÀÀÀÀÀÀD1 G02 ÀÀÀÀÀÀÀÀVCC M02 ÀÀÀÀÀÀÀÀÀVCC R02 ÀÀÀÀÀÀÀÀD27

A03 ÀÀÀÀÀÀÀÀÀNC C03 ÀÀÀÀÀÀONCE G03 ÀÀÀÀÀÀÀÀVSS M03ÀÀÀÀÀÀÀÀÀÀVSS R03 ÀÀÀÀÀÀÀÀD31

A04 ÀÀÀÀÀÀÀÀÀNC C04 ÀÀÀÀÀÀÀÀÀNC G15 ÀÀÀÀÀÀÀÀVSS M15ÀÀÀÀÀÀÀÀÀÀVSS R04ÀÀÀÀÀBTERM

A05 ÀÀÀÀÀÀÀÀÀNC C05 ÀÀÀÀÀÀÀÀÀNC G16 ÀÀÀÀÀÀÀÀÀA7 M16 ÀÀÀÀÀÀÀÀÀVCC R05 ÀÀÀÀÀÀHOLD

A06 ÀÀÀÀÀDREQ1 C06 ÀÀÀÀÀÀÀÀVCC G17 ÀÀÀÀÀÀÀÀÀA8 M17ÀÀÀÀÀÀÀÀÀÀA14 R06 ÀÀÀÀÀÀÀADS

A07 ÀÀÀÀÀDREQ3 C07 ÀÀÀÀÀÀÀÀVSS R07 ÀÀÀÀÀÀÀÀVCC

A08 ÀÀÀÀÀDACK1 C08 ÀÀÀÀÀÀÀÀVSS H01 ÀÀÀÀÀÀÀÀD11 N01ÀÀÀÀÀÀÀÀÀÀD17 R08 ÀÀÀÀÀÀÀÀVCC

A09 ÀÀÀÀÀDACK2 C09 ÀÀÀÀÀÀÀÀVSS H02 ÀÀÀÀÀÀÀÀD10 N02 ÀÀÀÀÀÀÀÀÀÀD18 R09 ÀÀÀÀÀÀÀÀBE0

A10 ÀÀÀÀÀDACK3 C10 ÀÀÀÀÀÀÀÀVSS H03 ÀÀÀÀÀÀÀÀVSS N03ÀÀÀÀÀÀÀÀÀÀVCC R10 ÀÀÀÀÀÀÀÀVCC

A11 ÀÀÀEOP/TC0 C11 ÀÀÀÀÀÀÀÀVSS H15 ÀÀÀÀÀÀÀÀVSS N15ÀÀÀÀÀÀÀÀÀÀVCC R11 ÀÀÀÀÀÀÀÀVCC

A12 ÀÀÀEOP/TC1 C12 ÀÀÀÀÀÀÀÀVSS H16 ÀÀÀÀÀÀÀÀVCC N16 ÀÀÀÀÀÀÀÀÀÀA16 R12 ÀÀÀÀÀÀÀDMA

A13 ÀÀÀEOP/TC2 C13 ÀÀÀÀÀÀCLKIN H17 ÀÀÀÀÀÀÀÀÀA9 N17 ÀÀÀÀÀÀÀÀÀÀA15 R13 ÀÀÀÀÀÀBREQ

A14 ÀÀÀEOP/TC3 C14 ÀÀCLKMODE R14 ÀÀÀÀÀÀÀÀA29

A15 ÀÀÀÀÀÀXINT1 C15 ÀÀÀÀÀÀXINT4 J01 ÀÀÀÀÀÀÀÀD12 P01 ÀÀÀÀÀÀÀÀÀÀD19 R15 ÀÀÀÀÀÀÀÀA26

A16 ÀÀÀÀÀRESET C16 ÀÀÀÀÀÀXINT6 J02 ÀÀÀÀÀÀÀÀVCC P02 ÀÀÀÀÀÀÀÀÀÀD20 R16 ÀÀÀÀÀÀÀÀA23

A17 ÀÀÀÀÀÀXINT2 C17 ÀÀÀÀÀÀXINT7 J03 ÀÀÀÀÀÀÀÀVSS P03 ÀÀÀÀÀÀÀÀÀÀD22 R17 ÀÀÀÀÀÀÀÀA22

J15 ÀÀÀÀÀÀÀÀVSS P15 ÀÀÀÀÀÀÀÀÀÀA20

B01 ÀÀÀÀÀÀBOFF D01 ÀÀÀÀÀÀÀÀÀD5 J16 ÀÀÀÀÀÀÀÀVCC P16 ÀÀÀÀÀÀÀÀÀÀA19 S01 ÀÀÀÀÀÀÀÀD25

B02 ÀÀÀÀÀSTEST D02 ÀÀÀÀÀÀÀÀÀD2 J17 ÀÀÀÀÀÀÀÀA10 P17 ÀÀÀÀÀÀÀÀÀÀA17 S02 ÀÀÀÀÀÀÀÀD29

B03 ÀÀÀÀÀÀÀÀÀNC D03ÀÀÀÀÀÀÀÀÀNC S03 ÀÀÀÀÀREADY

B04 ÀÀÀÀÀÀÀÀÀNC D15 ÀÀÀÀÀÀÀÀNMI K01 ÀÀÀÀÀÀÀÀD13 Q01ÀÀÀÀÀÀÀÀÀÀD21 S04 ÀÀÀÀÀHOLDA

B05 ÀÀÀÀÀDREQ0 D16 ÀÀÀÀÀÀÀÀÀA2 K02 ÀÀÀÀÀÀÀÀVCC Q02ÀÀÀÀÀÀÀÀÀÀD23 S05 ÀÀÀÀÀÀÀÀBE3

B06 ÀÀÀÀÀDREQ2 D17 ÀÀÀÀÀÀÀÀÀA3 K03 ÀÀÀÀÀÀÀÀVSS Q03ÀÀÀÀÀÀÀÀÀÀD26 S06 ÀÀÀÀÀÀÀÀBE2

B07 ÀÀÀÀÀÀÀÀVCC K15 ÀÀÀÀÀÀÀÀVSS Q04ÀÀÀÀÀÀÀÀÀÀD28 S07 ÀÀÀÀÀÀÀÀBE1

B08 ÀÀÀÀÀDACK0 E01 ÀÀÀÀÀÀÀÀÀD7 K16 ÀÀÀÀÀÀÀÀVCC Q05ÀÀÀÀÀÀÀÀÀÀD30 S08 ÀÀÀÀÀBLAST

B09 ÀÀÀÀÀÀÀÀVCC E02 ÀÀÀÀÀÀÀÀÀD4 K17 ÀÀÀÀÀÀÀÀA11 Q06ÀÀÀÀÀÀÀÀÀÀVCC S09 ÀÀÀÀÀÀÀDEN

B10 ÀÀÀÀÀVCCPLL E03 ÀÀÀÀÀÀÀÀÀD0 Q07 ÀÀÀÀÀÀÀÀÀÀVSS S10 ÀÀÀÀÀÀÀW/R

B11 ÀÀÀÀÀÀÀÀVCC E15 ÀÀÀÀÀÀÀÀVCC L01 ÀÀÀÀÀÀÀÀD15 Q08 ÀÀÀÀÀÀÀÀÀÀVSS S11ÀÀÀÀÀÀÀDT/R

B12 ÀÀÀÀÀÀÀÀVCC E16 ÀÀÀÀÀÀÀÀÀA4 L02 ÀÀÀÀÀÀÀÀD14 Q09 ÀÀÀÀÀÀÀÀÀÀVSS S12 ÀÀÀÀÀÀÀWAIT

B13 ÀÀÀÀÀPCLK2 E17 ÀÀÀÀÀÀÀÀÀA5 L03 ÀÀÀÀÀÀÀÀVSS Q10 ÀÀÀÀÀÀÀÀÀÀVSS S13 ÀÀÀÀÀÀÀÀD/C

B14 ÀÀÀÀÀPCLK1 L15 ÀÀÀÀÀÀÀÀVSS Q11 ÀÀÀÀÀÀÀÀÀÀVSS S14 ÀÀÀÀÀÀLOCK

B15 ÀÀÀÀÀÀXINT0 F01 ÀÀÀÀÀÀÀÀÀD8 L16 ÀÀÀÀÀÀÀÀA13 Q12 ÀÀÀÀÀÀÀÀÀSUP S15 ÀÀÀÀÀÀÀÀA31

B16 ÀÀÀÀÀÀXINT3 F02 ÀÀÀÀÀÀÀÀÀD6 L17 ÀÀÀÀÀÀÀÀA12 Q13ÀÀÀÀÀÀÀÀÀÀA30 S16 ÀÀÀÀÀÀÀÀA27

B17 ÀÀÀÀÀÀXINT5 F03 ÀÀÀÀÀÀÀÀVCC Q14ÀÀÀÀÀÀÀÀÀÀA28 S17 ÀÀÀÀÀÀÀÀA25

F15 ÀÀÀÀÀÀÀÀVSS Q15ÀÀÀÀÀÀÀÀÀÀA24

F16 ÀÀÀÀÀÀÀÀVCC Q16ÀÀÀÀÀÀÀÀÀÀA21

F17 ÀÀÀÀÀÀÀÀÀA6 Q17ÀÀÀÀÀÀÀÀÀÀA18

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–3

Figure 4a. 80960CF PGA Pinout (View from Top Side)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–4

Figure 4b. 80960CF PGA Pinout (View from Bottom Side)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

3.4. Mechanical Data

3.4.1 CERAMIC PGA PACKAGE

271328–5

Family: Ceramic Pin Grid Array Package

Symbol Millimeters Inches

Min Max Notes Min Max Notes

A 3.56 4.57 0.140 0.180

A10.64 1.14 SOLID LID 0.025 0.045 SOLID LID

A223 0.30 SOLID LID 0.110 0.140 SOLID LID

A31.14 1.40 0.045 0.055

B 0.43 0.51 0.017 0.020

D 44.07 44.83 1.735 1.765

D140.51 40.77 1.595 1.605

e12.29 2.79 0.090 0.110

L 2.54 3.30 0.100 0.130

N 168 168

S11.52 2.54 0.060 0.100

ISSUE IWS REV X 7/15/88

Figure 5. 168-Lead Ceramic PGA Package Dimensions

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Table 7. Ceramic PGA Package Dimension Symbols

Letter or Description of Dimensions

Symbol

A Distance from seating plane to highest point of body

A1Distance between seating plane and base plane (lid)

A2Distance from base plane to highest point of body

A3Distance from seating plane to bottom of body

B Diameter of terminal lead pin

D Largest overall package dimension of length

D1A body length dimension, outer lead center to outer lead center

e1Linear spacing between true lead position centerlines

L Distance from seating plane to end of lead

S1Other body dimension, outer lead center to edge of body

NOTES:

1. Controlling dimension: millimeter.

2. Dimension ‘‘e1’’ (‘‘e’’) is non-cumulative.

3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415–0.0430 inch.

4. Dimensions ‘‘B’’, ‘‘B1’’ and ‘‘C’’ are nominal.

5. Details of Pin 1 identifier are optional.

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

3.5. Package Thermal Specifications

The 80960CF is specified for operation when TC

(the case temperature) is within the range of

b40§C–a110§C. TCmay be measured in any envi-

ronment to determine whether the 80960CF is within

specified operating range. The case temperature is

measured at the center of the top surface, opposite

the pins. Refer to Figure 7.

TA(the ambient temperature) can be calculated

from iCA (thermal resistance from case to ambient)

with the following equation:

TAeTCbP*iCA

Table 8 shows the maximum TAallowable (without

exceeding TC) at various airflows and operating fre-

quencies (fPCLK).

Note that TAis greatly improved by attaching fins or

a heat sink to the package. P (the maximum power

consumption) is calculated by using the typical ICC

as tabulated in Section 4.4, DC Specifications, and

VCC of 5V.

Table 8. Maximum TAat Various Airflows In §C (PGA Package Only)

Airflow-ft/min (m/sec)

fPCLK 0 200 400 600 800 1000

(MHz) (0) (1.01) (2.03) (3.04) (4.06) (5.07)

TA33 38 57 74 76 81 84

with 25 50 65 79 81 85 87

Heat Sink*16 63 74 84 86 89 90

TA33 18 33 47 57 66 67

without 25 34 46 57 65 72 74

Heat Sink 16 51 60 68 74 80 81

*0.285×high unidirectional heat sink (Al alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).

PGA Thermal ResistanceÐ§C/Watt

Parameter

AirflowÐft./min (m/sec)

0 200 400 600 800 1000

(0) (1.01) (2.03) (3.07) (4.06) (5.07)

iJunction-to-Case

(Case Measured 1.5 1.5 1.5 1.5 1.5 1.5

as shown in Figure 7)

iCase-to-Ambient 17 14 11 9 7.1 6.6

(No Heatsink)

iCase-to-Ambient

(with Unidirectional) 13 9 5.5 5.0 3.9 3.4

Heatsink)*

NOTES:

1. This table applies to 80960CF PGA plugged into socket or soldered directly

into board.

2. iJA eiJC aiCA.

3. iJ-CAP e4§C/W (approx.)

iJ-PIN e4§C/W (inner pins) (approx.)

iJ-PIN e8§C/W (outer pins) (approx.)

*0.285×high unidirectional heat sink (Al alloy 6061, 50 mil fin width, 150 mil

center-to-center fin spacing).

271328–6

Figure 6. 80960CF PGA Package Thermal Characteristics

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–7

Figure 7. Measuring 80960CF PGA Case

Temperature

3.6 Stepping Register Information

Upon Reset, Register G0 contains die stepping in-

formation. The following figure shows how G0 is

configured. The most significant byte contains an

ASCII 0. The upper middle byte contains an ASCII C.

The lower middle byte contains an ASCII F. The

least significant byte contains the stepping number

in ASCII. G0 retains this information until it is written

over by the user program.

Table 9 contains a cross reference of the number in

the least significant byte of register G0 to the die

stepping number.

ASCII 00 43 46 Stepping Number

DECIMAL 0 C F Stepping Number

MSB LSB

Figure 8. Register G0

Table 9. Die Stepping Cross Reference

G0 Least Die Stepping

Significant Byte

01 A

02 B

03 C

04 D

05 E

3.7 Suggested Sources for 80960CF

Accessories

The following are some suggested sources of ac-

cessories for the 80960CF. They are neither an

endorsement of any kind, nor a warranty of the

performance of any of the listed products and/or

companies.

Sockets

1. 3M Textool Test and Interconnection Products

Department

P.O. Box 2963

Austin, TX 78769-2963

2. Augat, Inc.

Interconnection Products Group

33 Perry Avenue

P.O. Box 779

Attleboro, MA 02703

(508) 222-2202

3. Concept Manufacturing Inc.

(Decoupling Sockets)

43024 Christy Street

Fremont, CA 94538

(415) 651-3804

Heat Sinks/Fins

1. Thermalloy, Inc.

2021 West Valley View Lane

Dallas, TX 75381-0839

(214) 243-4321

2. E G & G Division

60 Audubon Road

Wakefield, MA 01880

(617) 245-5900

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

4.0 ELECTRICAL SPECIFICATIONS

4.1 Absolute Maximum Ratings

Parameter Maximum Rating

Storage Temperature b65 §Ctoa

150 §C

Case Temperature Under Bias(2) b40 §Ctoa

125 §C

Supply Voltage wrt. VSS b0.5V to a6.5V

Voltage on Other pins wrt VSS b0.5V to VCC a0.5V

NOTICE: This data sheet contains information on

products in the sampling and initial production phases

of development. It is valid for the devices indicated in

the revision history. The specifications are subject to

change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

4.2. Operating Conditions

Operating Conditions (80960CF-33, -25, -16)

Symbol Parameter Min Max Units Notes

VCC Supply Voltage 80960CF-30 4.75 5.25

80960CF-25 4.50 5.50 V

80960CF-16 4.50 5.50

fCLK2x Input Clock Frequency (2-x Mode) 80960CF-30 0 60.6 MHz

80960CF-25 0 50 MHz

80960CF-16 0 32 MHz

fCLK1x Input Clock Frequency (1-x Mode) 80960CF-30 8 30.3 MHz

80960CF-25 8 25 MHz (1)

80960CF-16 8 16 MHz

TCCase Temperature Under Bias PGA Package b40 a110 §C

80960CF-30, -25, -16

NOTES:

(1) When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum

frequency of 8 MHz for proper processor operation. However, in the 1-x Mode, CLKIN may still be stopped when the

processor either is in a reset condition or is reset. If CLKIN is stopped, the specified RESET low time must be provided once

CLKIN restarts and has stabilized.

(2) Case temperatures are ‘‘Instant On’’.

4.3 Recommended Connections

Power and ground connections must be made to

multiple VCC and VSS (GND) pins. Every 80960CF-

based circuit board should include power (VCC) and

ground (VSS) planes for power distribution. Every

VCC pin must be connected to the power plane, and

every VSS pin must be connected to the ground

plane. Pins identified as ‘‘N.C.’’ must not be con-

nected in the system.

Liberal decoupling capacitance should be placed

near the 80960CF. The processor can cause tran-

sient power surges when its numerous output buff-

ers transition, particularly when connected to large

capacitive loads.

Low inductance capacitors and interconnects are

recommended for best high frequency electrical per-

formance. Inductance can be reduced by shortening

board traces between the processor and decoupling

capacitors as much as possible. Capacitors specifi-

cally designed for PGA packages will offer the low-

est possible inductance.

For reliable operation, always connect unused in-

puts to an appropriate signal level. In particular, any

unused interrupt (XINT, NMI) or DMA (DREQ) input

should be connected to VCC through a pull-up resis-

tor, as should BTERM if not used. Pull-up resistors

should be in the range of 20 KXfor each pin tied

high. If READY or HOLD are not used, the unused

input should be connected to ground. N.C. pins

must always remain unconnected. Refer to the

i960 CA Microprocessor Reference Manual

for more

information.

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

4.4. DC Specifications

DC Characteristics

(80960CF-30, -25, -16 under the conditions described in Section 4.2, Operating Conditions.)

Symbol Parameter Min Max Units Notes

VIL Input Low Voltage for all pins except RESET b0.3 0.8 V

VIH Input High Voltage for all pins except RESET 2.0 VCC a0.3 V

VOL Output Low Voltage 0.45 V IOLe5mA

OH Output High Voltage IOH eb

1mA 2.4 V

IOH eb

200mAV

CC b0.5 V

VILR Input Low Voltage for RESET b0.3 1.5 V

VIHR Input High Voltage for RESET 3.5 VCC a0.3 V

ILI1 Input Leakage Current for each pin

except

BTERM, ONCE, DREQ3:0, STEST,

EOP3:0/TC3:0, NMI, XINT7:0,

READY, HOLD, BOFF, CLKMODE g15 mA0V

INsVCC (1)

ILI2 Input Leakage Current for:

BTERM, ONCE, DREQ3:0, STEST,

EOP3:0/TC3:0, NMI, XINT7:0, BOFF 0 b325 mAV

IN e0.45V (2)

ILI3 Input Leakage Current for:

READY, HOLD, CLKMODE 0 500 mAV

IN e2.4V (3)

ILO Output Leakage Current g15 mA 0.45VsVOUTsVCC

ICC Supply Current (80960CF-30)

ICC Max 1150 mA (4)

ICC Typ 960 (5)

ICC Supply Current (80960CF-25)

ICC Max 950 mA (4)

ICC Typ 775 (5)

ICC Supply Current (80960CF-16)

ICC Max 750 mA (4)

ICC Typ 575 (5)

IONCE ONCE-mode Supply Current 150 mA

CIN Input Capacitance for:

CLKIN, RESET, ONCE,

READY, HOLD, DREQ3:0, BOFF

XINT7:0, NMI, BTERM, CLKMODE 0 12 pF FCe1 MHz

COUT Output Capacitance of each output pin 12 pF FCe1 MHz, (6)

CI/O I/O Pin Capacitance 12 pF FCe1 MHz

NOTES:

(1) No Pull-up or pull-down.

(2) These pins have internal pullup resistors.

(3) These pins have internal pulldown resistors.

(4) Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions

described in Section 4.5.1, AC Test Conditions.

(5) ICC Typical is not tested.

(6) Output Capacitance is the capacitive load of a floating output.

(7) CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted.

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

4.5 AC Specifications

AC Characteristics Ð 80960CF-30

(80960CF-30 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,

AC Test Conditions.) See notes which follow this table.

Symbol Parameter Min Max Units Notes

INPUT CLOCK(10)

TFCLKIN Frequency 0 60.6 MHz (1)

TCCLKIN Period In 1-x Mode (fCLK1x) 33 125 ns (1,12)

In 2-x Mode (fCLK2x) 16.5 %ns (1)

TCS CLKIN Period Stability In 1-x Mode (fCLK1x)g0.1% D(1,13)

TCH CLKIN High Time In 1-x Mode (fCLK1x) 6 62.5 ns (1,12)

In 2-x Mode (fCLK2x)6 %ns (1)

TCL CLKIN Low Time In 1-x Mode (fCLK1x) 6 62.5 ns (1,12)

In 2-x Mode (fCLK2x)6 %ns (1)

TCR CLKIN Rise Time 0 6 ns (1)

TCF CLKIN Fall Time 0 6 ns (1)

OUTPUT CLOCKS(9)

TCP CLKIN to PCLK2:1 Delay In 1-x Mode (fCLK1x)b2 2 ns (1,3,13,14)

In 2-x Mode (fCLK2x) 2 25 ns (1,3)

T PCLK2:1 Period In 1-x Mode (fCLK1x)T

Cns (1,13)

In 2-x Mode (fCLK2x)2T

Cns (1,3)

TPH PCLK2:1 High Time (T/2) b2 T/2 ns (1,13)

TPL PCLK2:1 Low Time (T/2) b2 T/2 ns (1,13)

TPR PCLK2:1 Rise Time 1 4 ns (1,3)

TPF PCLK2:1 Fall Time 1 4 ns (1,3)

SYNCHRONOUS OUTPUTS(10)

TOV Output Valid Delay, Output Hold (6, 11)

TOH TOV1,T

OH1 A31:2 3 14 ns

TOV2,T

OH2 BE3:0 316ns

OV3,T

OH3 ADS 618ns

OV4,T

OH4 W/R 318ns

OV5,T

OH5 D/C, SUP, DMA 416ns

OV6,T

OH6 BLAST, WAIT 516ns

OV7,T

OH7 DEN 316ns

OV8,T

OH8 HOLDA, BREQ 4 16 ns

TOV9,T

OH9 LOCK 416ns

OV10,T

OH10 DACK3:0 418ns

OV11,T

OH11 D31:0 3 16 ns

TOV12,T

OH12 DT/R T/2 a3 T/2 a14 ns

TOV13,T

OH13 FAIL 2 14 ns (6, 11)

TOV14,T

OH14 EOP/TC3:0 318ns

OF Output Float for all outputs 3 22 ns (6)

SYNCHRONOUS INPUTS(10)

TIS Input Setup

TIS1 D31:0 3 ns (1,11)

TIS2 BOFF 17 ns (1,11)

TIS3 BTERM/READY 7 ns (1,11)

TIS4 HOLD 7 ns (1,11)

TIH Input Hold

TIH1 D31:0 5 ns (1,11)

TIH2 BOFF 5 ns (1,11)

TIH3 BTERM/READY 2 ns (1,11)

TIH4 HOLD 3 ns (1,11)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

AC Characteristics Ð 80960CF-30

(80960CF-30 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,

AC Test Conditions.) See notes which follow this table. (Continued)

Symbol Parameter Min Max Units Notes

RELATIVE OUTPUT TIMINGS(9,7)

TAVSH1 A31:2 Valid to ADS Rising T b4T

4ns

AVSH2 BE3:0, W/R, SUP, D/C,

DMA, DACK3:0 Valid to ADS Rising T b6T

6ns

AVEL1 A31:2 Valid to DEN Falling T b4T

4ns

AVEL2 BE3:0, W/R, SUP, INST,

DMA, DACK3:0 Valid to DEN Falling T b6T

6ns

NLQV WAIT Falling to Output Data Valid g6ns

DVNH Output Data Valid to WAIT Rising N*Tb6N*T

6 ns (4)

TNLNH WAIT Falling to WAIT Rising N*Tg4 ns (4)

TNHQX Output Data Hold after WAIT Rising (N a1) *Tb6(N

1) *Ta6 ns (5)

TEHTV DT/R Hold after DEN High T/2 b6%ns (6)

TTVEL DT/R Valid to DEN Falling T/2 b4 T/2 a4 ns (7)

RELATIVE INPUT TIMINGS(7)

TIS5 RESET Input Setup (2x Clock Mode) 6 ns (14)

TIH5 RESET Input Hold (2x Clock Mode) 5 ns (14)

TIS6 DREQ3:0 Input Setup 12 ns (8)

TIH6 DREQ3:0 Input Hold 7 ns (8)

TIS7 XINT7:0, NMI Input Setup 7 ns (8)

TIH7 XINT7:0, NMI Input Hold 3 ns (8)

TIS8 RESET Input Setup (1x Clock Mode) 3 ns (15)

TIH8 RESET Input Hold (1x Clock Mode) T/4 a1 ns (15)

NOTES:

1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.

2. See Figure 22 for capacitive derating information for output delays and hold times.

3. See Figure 23 for capacitive derating information for rise and fall times.

4. Where N is the number of NRAD,N

RDD,N

WAD,orN

WDD wait states that are programmed in the Bus Controller Region

Table. When there are no wait states in an access, WAIT never goes active.

5. N eNumber of wait states inserted with READY.

6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.

7. See Notes 1, 2 and 3.

8. Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in order

to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1

the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising

edges to be seen by the processor.

9. These specifications are guaranteed by the processor.

10. These specifications must be met by the system for proper operation of the processor.

11. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3 to adjust the timing for

PCLK2:1 loading.

12. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When

the processor is in reset, the input clock may stop even in 1-x mode.

13. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than

g0.1% between adjacent cycles.

14. In 2x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.

However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup

and hold times to the falling edge of the CLKIN. (See Figure 28a.)

15. In 1x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.

However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must be deasserted

while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN. (See Figure 28b.)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

AC Characteristics Ð 80960CF-25

(80960CF-25 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,

AC Test Conditions.)

Symbol Parameter Min Max Units Notes

INPUT CLOCK(10)

TFCLKIN Frequency 0 50 MHz (1)

TCCLKIN Period In 1-x Mode (fCLK1x) 40 125 ns (1,12)

In 2-x Mode (fCLK2x)20 %ns (1)

TCS CLKIN Period Stability In 1-x Mode (fCLK1x)g0.1% D(1,13)

TCH CLKIN High Time In 1-x Mode (fCLK1x) 8 62.5 ns (1,12)

In 2-x Mode (fCLK2x)8 %ns (1)

TCL CLKIN Low Time In 1-x Mode (fCLK1x) 8 62.5 ns (1,12)

In 2-x Mode (fCLK2x)8 %ns (1)

TCR CLKIN Rise Time 0 6 ns (1)

TCF CLKIN Fall Time 0 6 ns (1)

OUTPUT CLOCKS(9)

TCP CLKIN to PCLK2:1 Delay In 1-x Mode (fCLK1x)b2 2 ns (1,3,13,14)

In 2-x Mode (fCLK2x) 2 25 ns (1,3)

T PCLK2:1 Period In 1-x Mode (fCLK1x)T

Cns (1,13)

In 2-x Mode (fCLK2x)2T

Cns (1,3)

TPH PCLK2:1 High Time (T/2) b3 T/2 ns (1,13)

TPL PCLK2:1 Low Time (T/2) b3 T/2 ns (1,13)

TPR PCLK2:1 Rise Time 1 4 ns (1,3)

TPF PCLK2:1 Fall Time 1 4 ns (1,3)

SYNCHRONOUS OUTPUTS(10)

TOV Output Valid Delay, Output Hold (6, 11)

TOH TOV1,T

OH1 A31:2 3 16 ns

TOV2,T

OH2 BE3:0 318ns

OV3,T

OH3 ADS 620ns

OV4,T

OH4 W/R 320ns

OV5,T

OH5 D/C,SUP,DMA 418ns

OV6,T

OH6 BLAST, WAIT 518ns

OV7,T

OH7 DEN 318ns

OV8,T

OH8 HOLDA, BREQ 4 18 ns

TOV9,T

OH9 LOCK 418ns

OV10,T

OH10 DACK3:0 420ns

OV11,T

OH11 D31:0 3 18 ns

TOV12,T

OH12 DT/R T/2 a3 T/2 a16 ns

TOV13,T

OH13 FAIL 216ns

OV14,T

OH14 EOP3:0/TC3:0 3 20 ns (6, 11)

TOF Output Float for all outputs 3 22 ns (6)

SYNCHRONOUS INPUTS(10)

TIS Input Setup

TIS1 D31:0 5 ns (1,11)

TIS2 BOFF 19 ns (1,11)

TIS3 BTERM/READY 9 ns (1,11)

TIS4 HOLD 9 ns (1,11)

TIH Input Hold

TIH1 D31:0 5 ns (1,11)

TIH2 BOFF 7 ns (1,11)

TIH3 BTERM/READY 2 ns (1,11)

TIH4 HOLD 5 ns (1,11)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

AC Characteristics Ð 80960CF-25

(80960CF-25 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,

AC Test Conditions.) (Continued)

Symbol Parameter Min Max Units Notes

RELATIVE OUTPUT TIMINGS(9,7)

TAVSH1 A31:2 Valid to ADS Rising T b4T

4ns

AVSH2 BE3:0, W/R, SUP, D/C,

DMA, DACK3:0 Valid to ADS Rising T b6T

6ns

AVEL1 A31:2 Valid to DEN Falling T b4T

4ns

AVEL2 BE3:0, W/R, SUP, INST,

DMA, DACK3:0 Valid to DEN Falling T b6T

6ns

NLQV WAIT Falling to Output Data Valid g6ns

DVNH Output Data Valid to WAIT Rising N*Tb6N*T

6 ns (4)

TNLNH WAIT Falling to WAIT Rising N*Tg4 ns (4)

TNHQX Output Data Hold after WAIT Rising (N a1) *Tb6(N

1) *Ta6 ns (5)

TEHTV DT/R Hold after DEN High T/2 b6%ns (6)

TTVEL DT/R Valid to DEN Falling T/2 b4 T/2 a4 ns (7)

RELATIVE INPUT TIMINGS(7)

TIS5 RESET Input Setup (2x Clock Mode 8 ns (14)

TIH5 RESET Input Hold (2x Clock Mode) 7 ns (14)

TIS6 DREQ3:0 Input Setup 14 ns (8)

TIH6 DREQ3:0 Input Hold 9 ns (8)

TIS7 XINT7:0, NMI Input Setup 9 ns (8)

TIH7 XINT7:0, NMI Input Hold 5 ns (8)

TIS8 RESET Input Setup (1x Clock Mode) 3 ns (15)

TIH8 RESET Input Hold (1x Clock Mode) T/4 a1 ns (15)

NOTES:

(1) See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.

(2) See Figure 22 for capacitive derating information for output delays and hold times.

(3) See Figure 23 for capacitive derating information for rise and fall times.

(4) Where N is the number of NRAD,N

RDD,N

WAD,orN

WDD wait states that are programmed in the Bus Controller Region

Table. When there are no wait states in an access, WAIT never goes active.

(5) N eNumber of wait states inserted with READY.

(6) Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.

(7) See Notes 1, 2 and 3.

(8) Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in

order to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of

PCLK2:1 the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1

rising edges to be seen by the processor.

(9) These specifications are guaranteed by the processor.

(10) These specifications must be met by the system for proper operation of the processor.

(11) This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3 to adjust the timing for

PCLK2:1 loading.

(12) In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When

the processor is in reset, the input clock may stop even in 1-x mode.

(13) When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than

g0.1% between adjacent cycles.

(14) In 2x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.

However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and

hold times to the falling edge of the CLKIN. (See Figure 28a.)

(15) In 1x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.

However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must be deasserted

while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN. (See Figure 28b.)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

AC Characteristics Ð 80960CF-16

(80960CF-16 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,

AC Test Conditions.) (Continued)

Symbol Parameter Min Max Units Notes

INPUT CLOCK(10)

TFCLKIN Frequency 0 32 MHz (1)

TCCLKIN Period In 1-x Mode (fCLK1x) 62.5 125 ns (1,12)

In 2-x Mode (fCLK2x) 31.25 %ns (1)

TCS CLKIN Period Stability In 1-x Mode (fCLK1x)g0.1% D(1,13)

TCH CLKIN High Time In 1-x Mode (fCLK1x) 10 62.5 ns (1,12)

In 2-x Mode (fCLK2x)10 %ns (1)

TCL CLKIN Low Time In 1-x Mode (fCLK1x) 10 62.5 ns (1,12)

In 2-x Mode (fCLK2x)10 %ns (1)

TCR CLKIN Rise Time 0 6 ns (1)

TCF CLKIN Fall Time 0 6 ns (1)

OUTPUT CLOCKS(9)

TCP CLKIN to PCLK2:1 Delay In 1-x Mode (fCLK1x)b2 2 ns (1,3,13,14)

In 2-x Mode (fCLK2x) 2 25 ns (1,3)

T PCLK2:1 Period In 1-x Mode (fCLK1x)T

Cns (1,13)

In 2-x Mode (fCLK2x)2T

Cns (1,3)

TPH PCLK2:1 High Time (T/2) b4 T/2 ns (1,13)

TPL PCLK2:1 Low Time (T/2) b4 T/2 ns (1,13)

TPR PCLK2:1 Rise Time 1 4 ns (1,3)

TPF PCLK2:1 Fall Time 1 4 ns (1,3)

SYNCHRONOUS OUTPUTS(10)

TOV Output Valid Delay, Output Hold (6, 11)

TOH TOV1,T

OH1 A31:2 3 18 ns

TOV2,T

OH2 BE3:0 320ns

OV3,T

OH3 ADS 622ns

OV4,T

OH4 W/R 322ns

OV5,T

OH5 D/C, SUP, DMA 420ns

OV6,T

OH6 BLAST, WAIT 520ns

OV7,T

OH7 DEN 320ns

OV8,T

OH8 HOLDA, BREQ 4 20 ns

TOV9,T

OH9 LOCK 420ns

OV10,T

OH10 DACK3:0 422ns

OV11,T

OH11 D31:0 3 20 ns

TOV12,T

OH12 DT/R T/2 a3 T/2 a18 ns

TOV13,T

OH13 FAIL 218ns

OV14,T

OH14 EOP3:0/TC3:0 3 22 ns (6, 11)

TOF Output Float for all outputs 3 22 ns (6)

SYNCHRONOUS INPUTS(10)

TIS Input Setup

TIS1 D31:0 5 ns (1,11)

TIS2 BOFF 21 ns (1,11)

TIS3 BTERM/READY 9 ns (1,11)

TIS4 HOLD 9 ns (1,11)

TIH Input Hold

TIH1 D31:0 5 ns (1,11)

TIH2 BOFF 7 ns (1,11)

TIH3 BTERM/READY 2 ns (1,11)

TIH4 HOLD 5 ns (1,11)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

AC Characteristics Ð 80960CF-16

(80960CF-16 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1,

AC Test Conditions.) (Continued)

Symbol Parameter Min Max Units Notes

RELATIVE OUTPUT TIMINGS(9,7)

TAVSH1 A31:2 Valid to ADS Rising T b4T

4ns

AVSH2 BE3:0, W/R, SUP, D/C,

DMA, DACK3:0 Valid to ADS Rising T b6T

6ns

AVEL1 A31:2 Valid to DEN Falling T b6T

6ns

AVEL2 BE3:0, W/R, SUP, INST,

DMA, DACK3:0 Valid to DEN Falling T b6T

6ns

NLQV WAIT Falling to Output Data Valid g6ns

DVNH Output Data Valid to WAIT Rising N*Tb6N*T

6 ns (4)

TNLNH WAIT Falling to WAIT Rising N*Tg4 ns (4)

TNHQX Output Data Hold after WAIT Rising (N a1) *Tb6(N

1) *Ta6 ns (5)

TEHTV DT/R Hold after DEN High T/2 b6%ns (6)

TTVEL DT/R Valid to DEN Falling T/2 b4 T/2 a4 ns (7)

RELATIVE INPUT TIMINGS(7)

TIS5 RESET Input Setup (2x Clock Mode) 10 ns (14)

TIH5 RESET Input Hold (2x Clock Mode) 9 ns (14)

TIS6 DREQ3:0 Input Setup 16 ns (8)

TIH6 DREQ3:0 Input Hold 11 ns (8)

TIS7 XINT7:0, NMI Input Setup 9 ns (8)

TIH7 XINT7:0, NMI Input Hold 5 ns (8)

TIS8 RESET Input Setup (1x Clock Mode) 3 ns (15)

TIH8 RESET Input Hold (1x Clock Mode) T/4 a1 ns (15)

NOTES:

(1) See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.

(2) See Figure 22 for capacitive derating information for output delays and hold times.

(3) See Figure 23 for capacitive derating information for rise and fall times.

(4) Where N is the number of NRAD,N

RDD,N

WAD,orN

WDD wait states that are programmed in the Bus Controller Region

Table. When there are no wait states in an access, WAIT never goes active.

(5) N eNumber of wait state inserted with READY.

(6) Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.

(7) See Notes 1, 2 and 3.

(8) Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in

order to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of

PCLK2:1 the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1

rising edges to be seen by the processor.

(9) These specifications are guaranteed by the processor.

(10) These specifications must be met by the system for proper operation of the processor.

(11) This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Figure 22 to adjust the timing for

PCLK2:1 loading.

(12) In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When

the processor is in reset, the input clock may stop even in 1-x mode.

(13) When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than

g0.1% between adjacent cycles.

(14) In 2x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.

However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and

hold times to the falling edge of the CLKIN. (See Figure 28a.)

(15) In 1x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation.

However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must be deasserted

while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN. (See Figure 28b.)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

4.5.1. AC TEST CONDITIONS

CLe50 pf for all signals 271328–8

Figure 9. AC Test Load

The AC Specifications in Section 4.5 are tested with

the 50 pf load shown in Figure 9. See Figure 16 to

see how timings vary with load capacitance.

Specifications are measured at the 1.5V crossing

point, unless otherwise indicated. Input waveforms

are assumed to have a rise-and-fall time of s2ns

from 0.8V to 2.0V. See Section 4.5.2, AC Timing

Waveforms for AC spec definitions, test points and

illustrations.

4.5.2. AC TIMING WAVEFORMS

271328–9

Figure 10a. Input and Output Clocks Waveform

271328–10

Figure 10b. CLKIN Waveform

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–11

Figure 11. Output Delay and Float Waveform

271328–12

Figure 12a. Input Setup and Hold Waveform

271328–13

271328–14

Figure 12b. NMI, XINT7:0 Input Setup and Hold Waveform

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–15

Figure 13. Hold Acknowledge Timings

271328–16

Figure 14. Bus Back-Off (BOFF) Timings

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–17

Figure 15. Relative Timings Waveforms

4.5.3 DERATING CURVES

271328–18

NOTE:

PCLK Load e50 pF

Figure 16. Output Delay or Hold vs Load Capacitance

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–19

(a) All outputs except: LOCK, DMA, SUP, HOLDA, BREQ, (b) LOCK, DMA, SUP, HOLDA, BREQ, DACK3:0,

DACK3:0, EOP3:0/TC3:0, FAIL EOP3:0/TC3:0, FAIL

Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC

271328–20

ICCÐICC under test conditions

Figure 18. ICC vs Frequency and Temperature

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

5.0 RESET, BACKOFF AND HOLD

ACKNOWLEDGE

The following table lists the condition of each proc-

essor output pin while RESET is asserted (low).

Table 10. Reset Conditions

Pins State During Reset

(HOLDA inactive)1

A31:A2 Floating

D31:D0 Floating

BE3:0 Driven high (Inactive)

W/R Driven low (Read)

ADS Driven high (Inactive)

WAIT Driven high (Inactive)

BLAST Driven low (Active)

DT/R Driven low (Receive)

DEN Driven high (Inactive)

LOCK Driven high (Inactive)

BREQ Driven low (Inactive)

D/C Floating

DMA Floating

SUP Floating

FAIL Driven low (Active)

DACK3 Driven high (Inactive)

DACK2 Driven high (Inactive)

DACK1 Driven high (Inactive)

DACK0 Driven high (Inactive)

EOP/TC3 Floating (set to input mode)

EOP/TC2 Floating (set to input mode)

EOP/TC1 Floating (set to input mode)

EOP/TC0 Floating (set to input mode)

NOTE:

(1) With regard to bus output pin state only, the Hold Ac-

knowledge state takes precedence over the reset state. Al-

though asserting the RESET pin will internally reset the

processor, the processor’s bus output pins will not enter

the reset state if it has granted Hold Acknowledge to a pre-

vious HOLD request (HOLDA is active). Furthermore, the

processor will grant new HOLD requests and enter the

Hold Acknowledge state even while in reset.

For example, if HOLDA is not active and the processor is

in the reset state, then HOLD is asserted, the processor’s

bus pins will enter the Hold Acknowledge state and

HOLDA will be granted. The processor will not be able to

perform memory accesses until the HOLD request is re-

moved, even if the RESET pin is brought high. This opera-

tion is provided to simplify boot-up synchronization among

multiple processors sharing the same bus.

The following table lists the condition of each proc-

essor output pin while HOLDA is asserted (low).

Table 11. Hold Acknowledge

and Backoff Conditions

Pins State During HOLDA

A31:A2 Floating

D31:D0 Floating

BE3:0 Floating

W/R Floating

ADS Floating

WAIT Floating

BLAST Floating

DT/R Floating

DEN Floating

LOCK Floating

BREQ Driven (high or low)

D/C Floating

DMA Floating

SUP Floating

FAIL Driven high (Inactive)

DACK3 Driven high (Inactive)

DACK2 Driven high (Inactive)

DACK1 Driven high (Inactive)

DACK0 Driven high (Inactive)

EOP/TC3 Driven if output

EOP/TC2 Driven if output

EOP/TC1 Driven if output

EOP/TC0 Driven if output

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

6.0 BUS WAVEFORMS

Figure 19. Cold Reset Waveform

271328–21

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Figure 20. Warm Reset Waveform

271328–22

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Figure 21. Entering the ONCE State

271328–23

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–24

NOTE:

Case 1 and Case 2 show two possible polarities of PCLK2:1.

Figure 22a. Clock Synchronization in the 2x Clock Mode

271328–25

NOTE:

In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2XCLK. 2XCLK is an internal signal generat-

ed by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising edge of CLKIN.

The RESET pin is sampled when PCLK is high.

Figure 22b. Clock Synchronization in the 1x Clock Mode

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–26

Figure 23. Non-Burst, Non-Pipelined Requests without Wait States

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–27

Figure 24. Non-Burst, Non-Pipelined Read Request with Wait States

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–28

Figure 25. Non-Burst, Non-Pipelined Write Request with Wait States

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–29

Figure 26. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–30

Figure 27. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–31

Figure 28. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–32

Figure 29. Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–33

Figure 30. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–34

Figure 31. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–35

Figure 32. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–36

Figure 33. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–37

Figure 34. Burst, Pipelined Read Request without Wait States, 32-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–38

Figure 35. Burst, Pipelined Read Requests with Wait States, 32-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–39

Figure 36. Burst, Pipelined Read Requests with Wait States, 16-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Region Table Entry

271328–40

Figure 37. Burst, Pipelined Read Requests with Wait States, 8-Bit Bus

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–41

Figure 38. Using External READY

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–42

NOTE:

READY adds memory access time to data transfers, whether or not the bus access is a burst access. BTERM interrupts

a bus access, whether or not the bus access has more data transfers pending. Either the READY signal or the BTERM

signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access.

Figure 39. Terminating a Burst with BTERM

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–43

Figure 40. BOFF Functional Timing

271328–44

Figure 41. HOLD Functional Timing

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–45

NOTES:

1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-by and some packing and unpacking

modes, in which loads are followed by loads, or stores are followed by stores.

2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high. Applications are non

fly-by transfers and adjacent load-stores or store-loads.

3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus accesses (defined

by ADS and BLAST. Refer to User’s Manual for ‘‘access’’, ‘‘request’’ definition.

Figure 42. DREQ and DACK Functional Timing

271328–46

NOTE:

EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests.

EOP is NOT edge triggered. EOP must be held for a minimum of 2 clock cycles then EOP must be deasserted

within 15 clock cycles.

Figure 43. EOP Functional Timing

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–47

NOTE:

Terminal Count becomes active during the last bus request of a buffer transfer. If the last LOAD/STORE bus request is

executed as multiple bus accesses, the TC will be active for the entire bus request. Refer to the User’s Manual for

further information.

Figure 44. Terminal Count Functional Timing

271328–48

Figure 45. FAIL Functional Timing

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–49

Figure 46. A Summary of Aligned and Unaligned Transfers for Little Endian Regions

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

271328–50

Figure 47. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued)

SPECIAL ENVIRONMENT 80960CF-30, -25, -16

Figure 48. Idle Bus Operation

271328–51