Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
Document Number: MPC17531A
Rev. 4.0, 5/2009
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005 - 2009. All rights reserved.
700 mA Dual H-Bridge Motor
Driver with 3.0 V Compatible
Logic I/O
The 17531A is a monolithic dual H-Bridge power IC ideal for
portable electronic applications containing bipolar step motors and/or
brush DC-motors (e.g., cameras and disk drive head positioners).
The 17531A operates from 2.0 V to 8.6 V using the internal charge
pump, with independent control of each H-Bridge via parallel MCU
interface. The device features built-in shoot-through current protection
and an undervoltage shutdown function.
The 17531A has four operating modes: Forward, Reverse, Brake,
and Tri-Stated (High Impedance). The 17531A has a low total RDS(ON)
of 1.2 Ω (max @ 25°C).
The 17531A efficiently drives many types of micromotors with low
power dissipation owing to its low output resistance and high output
slew rates. The H-Bridge outputs can be independently pulse width
modulated (PWM’ed) at up to 200 kHz for speed/torque and current
control.
Features
• Low Total RDS(ON) 0.8 W (Typ), 1.2 Ω (Max) @ 25°C
• Output Current 0.7 A (DC)
• Shoot-Through Current Protection Circuit
• PWM Control Input Frequency up to 200 kHz
• Built-In Charge Pump Circuit
• Low Power Consumption
• Undervoltage Detection and Shutdown Circuit
• Power Save Mode with Current Draw ≤ 2.0 μA
• Pb-Free Packaging Designated by Suffix Codes EV and EP
Figure 1. 17531A Simplified Application Diagram
DUAL H-BRIDGE
VMFP SUFFIX
EV SUFFIX (PB-FREE)
98ASA10616D
20-TERMINAL VMFP
17531A
ORDERING INFORMATION
Device Temperature
Range (TA)Package
MPC17531AEV/EL -20°C to 65°C 20 VMFP
MPC17531AEP/R2 24 QFN
QFN SUFFIX
EP SUFFIX (PB-FREE)
98ARL10577D
24-TERMINAL QFN
CRES
C1L
C1H
C2L
C2H
IN2B
PSAVE
IN2A
IN1A
OUT2B
OUT2A
OUT1B
OUT1A
VM
GND
MCU
IN1B
3.0 V 5.0 V
17531A
Bipolar
Step
Motor
N
S
VDD
Analog Integrated Circuit Device Data
2Freescale Semiconductor
17531A
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Figure 2. 17531A Simplified Internal Block Diagram
VM1
OUT2B
OUT2A
OUT1A
PGND2
IN1A
C2H
IN1B
C1H
C2L
C1L
VDD
Low-
Shutdown
Charge
Level Shifter
VM2
OUT1B
IN2A
IN2B
PSAVE
LGND
PGND1
Control
Predriver
Pump
Voltage
H-Bridge
H-Bridge
Logic
CRES
VDD
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
17531A
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
Figure 3. 17531A, 20-Terminal VMFP Connections
Table 1. 17531A, 20-Terminal VMFP Definitions
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10.
Terminal
Number
Terminal
Name Formal Name Definition
1VDD Logic Supply Control circuit power supply terminal.
2IN1A Logic Input Control 1A Logic input control of OUT1A (refer to Table 6, Truth Table, page 9).
3IN1B Logic Input Control 1B Logic input control of OUT1B (refer to Table 6, Truth Table, page 9).
4PSAVE Power Save Logic input controlling power save mode.
5OUT2A H-Bridge Output 2A Output A of H-Bridge channel 2.
6PGND1 Power Ground 1 High-current power ground 1.
7OUT1A H-Bridge Output 1A Output A of H-Bridge channel 1.
8VM1 Motor Drive Power Supply 1 Positive power source connection for H-Bridge 1 (Motor Drive Power Supply).
9CRES Predriver Power Supply Internal triple charge pump output as predriver power supply.
10 C2H Charge Pump 2H Charge pump bucket capacitor 2 (positive pole).
11 C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole).
12 C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole).
13 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole).
14 OUT1B H-Bridge Output 1B Output B of H-Bridge channel 1.
15 PGND2 Power Ground 2 High-current power ground 2.
16 OUT2B H-Bridge Output 2B Output B of H-Bridge channel 2.
17 VM2 Motor Drive Power Supply 2 Positive power source connection for H-Bridge 2 (Motor Drive Power Supply).
18 IN2B Logic Input Control 2B Logic input control of OUT2B (refer to Table 6, Truth Table, page 9).
19 IN2A Logic Input Control 2A Logic input control of OUT2A (refer to Table 6, Truth Table, page 9).
20 LGND Logic Ground Low-current logic signal ground.
VDD
IN1B
OUT1A
VM1
CRES
C2H
PSAVE
OUT2A
PGND1
IN1A
LGND
VM2
OUT2B
PGND2
OUT1B
C2L
C1L
C1H
IN2A
IN2B
4
5
6
7
8
9
10
2
3
20
18
14
13
12
11
17
16
15
19
1
Analog Integrated Circuit Device Data
4Freescale Semiconductor
17531A
TERMINAL CONNECTIONS
Figure 4. 17531A, 24-Terminal QFN Connections
Table 2. 17531A, 24-Terminal QFN Definitions
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10.
Terminal
Number
Terminal
Name Formal Name Definition
1, 6, 7, 17 NC No Connect This terminal is not used.
2PSAVE Power Save Logic input controlling power save mode.
3OUT2A H-Bridge Output 2A Output A of H-Bridge channel 2.
4PGND1 Power Ground 1 High-current power ground 1.
5OUT1A H-Bridge Output 1A Output A of H-Bridge channel 1.
8VM1 Motor Drive Power Supply 1 Positive power source connection for H-Bridge 1 (Motor Drive Power Supply).
9 CRES Predriver Power Supply Internal triple charge pump output as pre-driver power supply.
10 C2H Charge Pump 2H Charge pump bucket capacitor 2 (positive pole).
11 C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole).
12 C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole).
13 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole).
14 OUT1B H-Bridge Output 1B Output B of H-Bridge channel 1.
15 PGND2 Power Ground 2 High-current power ground 2.
16 OUT2B H-Bridge Output 2B Output B of H-Bridge channel 2.
18 VM2 Motor Drive Power Supply 2 Positive power source connection for H-Bridge 2 (Motor Drive Power Supply).
19 IN2B Logic Input Control 2B Logic input control of OUT2B (refer to Table 6, Truth Table, page 9).
20 IN2A Logic Input Control 2A Logic input control of OUT2A (refer to Table 6, Truth Table, page 9).
21 LGND Logic Ground Low-current logic signal ground.
22 VDD Logic Supply Control circuit power supply terminal.
23 IN1A Logic Input Control 1A Logic input control of OUT1A (refer to Table 6, Truth Table, page 9).
24 IN1B Logic Input Control 1B Logic input control of OUT1B (refer to Table 6, Truth Table, page 9).
NC
PSAVE
OUT2A
PGND1
OUT1A
NC
NC
VM1
CRES
C2H
C1H
C1L
C2L
OUT1B
PGND2
OUT2B
NC
VM2
IN2B
IN2A
LGND
VDD
IN1B
IN1A
1
2
3
4
5
6
789101112
13
14
15
16
17
18
192021222324
MPC17530EP
Transparent Top View of Package
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
17531A
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit
Motor Supply Voltage VM-0.5 to 11.0 V
Charge Pump Output Voltage VCRES -0.5 to 14.0 V
Logic Supply Voltage VDD -0.5 to 5.0 V
Signal Input Voltage VIN -0.5 to VDD
+ 0.5 V
Driver Output Current
Continuous
Peak (1)
IO
IOPK
0.7
1.4
A
ESD Voltage
Human Body Model (2)
Machine Model (3)
VESD1
VESD2
±1200
± 150
V
Operating Junction Temperature TJ-20 to 150 °C
Operating Ambient Temperature TA-20 to 65 °C
Storage Temperature Range TSTG -65 to 150 °C
Thermal Resistance (4) RθJA 50 °C/W
Power Dissipation (5)
WMFP
QFN
PD
1.0
2.5
W
Terminal Soldering Temperature (6) TSOLDER 260 °C
Notes
1. TA = 25°C. Pulse width = 10 ms at 200 ms intervals.
2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
3. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
4. For QFN only, mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB).
5. TA = 25°C.
6. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
Analog Integrated Circuit Device Data
6Freescale Semiconductor
17531A
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER INPUT
Motor Supply Voltage (Using Internal Charge Pump) (7) VM-CP 2.0 5.0 8.6 V
Motor Supply Voltage (VCRES Applied Externally) (8) VM-NCP – – 10 V
Gate Drive Voltage - Motor Supply Voltage (VCRES Applied Externally) (9) VCRES - VM5.0 6.0 – V
Logic Supply Voltage VDD 2.7 3.0 3.6 V
Driver Quiescent Supply Current
No Signal Input
Power Save Mode
IQM
IQM-PSAVE
–
–
–
–
100
1.0
μA
Logic Quiescent Supply Current
No Signal Input (10)
Power Save Mode
IQVDD
IQVDD-
PSAVE
–
–
–
–
1.0
1.0
mA
Operating Power Supply Current
Logic Supply Current (11)
Charge Pump Circuit Supply Current (12)
I
VDD
ICRES
–
–
–
–
3.0
0.7
mA
Low VDD Detection Voltage (13) VDDDET 1.0 1.6 2.5 V
Driver Output ON Resistance (14) RDS(ON) –0.8 1.2 Ohms
GATE DRIVE
Gate Drive Voltage (12)
No Current Load
VCRES
12 13 13.5
V
Gate Drive Ability (Internally Supplied)
ICRES = -1.0 mA
VCRESload
8.5 9.2 –
V
Recommended External Capacitance (C1L – C1H, C2L – C2H, CRES – GND) CCP 0.01 0.1 1.0 μF
Notes
7. Gate drive voltage VCRES is generated internally. 2 x VDD + VM must be < VCRES max (13.5 V).
8. No internal charge pump used. VCRES is applied from an external source.
9. RDS(ON) is not guaranteed if VCRES - VM < 5.0 V. Also, function is not guaranteed if VCRES - VM < 3.0 V.
10. IQVDD includes the current to pre-driver circuit.
11. I
VDD includes the current to predriver circuit at fIN = 100 kHz.
12. At fIN = 20 kHz.
13. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. VCRES is
applied from an external source. 2 x VDD + VM must be < VCRES max (13.5 V).
14. IO = 0.7 A source + sink.
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
17531A
STATIC ELECTRICAL CHARACTERISTICS
CONTROL LOGIC
Logic Input Voltage VIN 0 – VDD V
Logic Inputs (2.7 V < VDD
< 3.3 V)
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
PSAVE Terminal Input Current Low
VIH
VIL
IIH
IIL
IIL- PSAVE
VDD
x 0.7
–
–
-1.0
–
–
–
–
–
50
–
VDD
x 0.3
1.0
–
100
V
V
μA
μA
μA
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
8Freescale Semiconductor
17531A
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
INPUT
Pulse Input Frequency f
IN – – 200 kHz
Input Pulse Rise Time (15) t
R– – 1.0
(16)
μs
Input Pulse Fall Time (17) t F – – 1.0
(16)
μs
OUTPUT
Propagation Delay Time (18)
Turn-ON Time
Turn-OFF Time
t
PLH
t
PHL
–
–
0.1
0.1
0.5
0.5
μs
Charge Pump Wake-Up Time (19) t
VGON –1.0 3.0 ms
Low-Voltage Detection Time t VDDDET – – 10 ms
Notes
15. Time is defined between 10% and 90%.
16. That is, the input waveform slope must be steeper than this.
17. Time is defined between 90% and 10%.
18. Output load is 8.0 Ω DC.
19. CCP = 0.1 μF.
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
17531A
TIMING DIAGRAMS
TIMING DIAGRAMS
Figure 5. tPLH, tPHL, and tPZH Timing Figure 6. Low-Voltage Detection Timing
Figure 7. Charge Pump Timing
10%
50%
OUTA,
OUTB
90%
tPLH tPHL
IN1,
IN2,
PSAVE
tVDDDET
0%
VDD
IM
50%
tVDDDET
0.8 V
2.5 V
VDDDETon VDDDEToff
90%
(<1.0 μA)
t
VGON
V
DD
V
C
RES
11 V
Table 6. Truth Table
INPUT OUTPUT Charge Pump and Low
Voltage Detector
PSAVE IN1A
IN2A
IN1B
IN2B
OUT1A
OUT2A
OUT1B
OUT2B
L L L L L RUN
L H L H L RUN
L L H L H RUN
L H H Z Z RUN
H X X Z Z STOP
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
PSAVE terminal is pulled up to VDD with internal resistance.
Analog Integrated Circuit Device Data
10 Freescale Semiconductor
17531A
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17531A is a monolithic dual H-Bridge ideal for
portable electronic applications to control bipolar step motors
and brush DC motors such as those found in camera len
assemblies, camera shutters, and optical disk drives. The
device features an on-board charge pump, as well as built-in
shoot-through current protection and undervoltage
shutdown.
The 17531A has four operating modes: Forward, Reverse,
Brake, and Tri-Stated (High Impedance). The MOSFETs
comprising the output bridge have a total source + sink
RDS(ON) ≤ 1.2 Ω.
The 17531A can simultaneously drive two brush DC
motors or one bipolar step motor. The drivers are designed to
be PWM’ed at frequencies up to 200 kHz.
FUNCTIONAL TERMINAL DESCRIPTION
LOGIC SUPPLY (VDD)
The VDD terminal carries the logic supply voltage and
current into the logic sections of the IC. VDD has an
undervoltage threshold. If the supply voltage drops below the
undervoltage threshold, the output power stage switches to a
tri-state condition. When the supply voltage returns to a level
that is above the threshold, the power stage automatically
resumes normal operation according to the established
condition of the input terminals.
LOGIC INPUT CONTROL (IN1A, IN1B, IN2A, AND
IN2B)
These logic input terminals control each H-Bridge output.
IN1A logic HIGH = OUT1A HIGH. However, if all inputs are
taken HIGH, the outputs bridges are both tri-stated (refer to
Table 6, Truth Table, page 9).
POWER SAVE (PSAVE)
The PSAVE terminal is a HIGH = TRUE power save mode
input. When PSAVE = HIGH, all H-Bridge outputs (OUT1A,
OUT1B, OUT2A, and OUT2B) are tri-stated (High-Z),
regardless of logic inputs (IN1A, IN1B, IN2A, and IN2B)
states, and the internal charge pump and low voltage
detection current are shut off to save power.
H-BRIDGE OUTPUT (OUT1A, OUT1B, OUT2A, AND
OUT2B)
These terminals provide connection to the outputs of each
of the internal H-Bridges (see Figure 2, 17531A Simplified
Internal Block Diagram, page 2).
MOTOR DRIVE POWER SUPPLY (VM1 AND VM2)
The VM terminals carry the main supply voltage and
current into the power sections of the IC. This supply then
becomes controlled and/or modulated by the IC as it delivers
the power to the loads attached between the OUTput
terminals. All VM terminals must be connected together on
the printed circuit board.
CHARGE PUMP (C1L AND C1H, C2L AND C2H)
These two pairs of terminals, the C1L and C1H and the
C2L and C2H, connect to the external bucket capacitors
required by the internal charge pump. The typical value for
the bucket capacitors is 0.1 μF.
PREDRIVER POWER SUPPLY (CRES)
The CRES terminal is the output of the internal charge
pump. Its output voltage is approximately three times of VDD
voltage. The VCRES voltage is power supply for the internal
predriver circuit of H-Bridges.
POWER GROUND (PGND)
Power ground terminals. They must be tied together on the
PCB.
LOGIC GROUND (LGND)
Logic ground terminal.
Analog Integrated Circuit Device Data
Freescale Semiconductor 11
17531A
TYPICAL APPLICATIONS
FUNCTIONAL TERMINAL DESCRIPTION
TYPICAL APPLICATIONS
Figure 8 shows a typical application for the 17531A. When
applying the gate voltage to the CRES terminal from an
external source, be sure to connect it via a resistor equal to,
or greater than, RG = VCRES / 0.02 Ω.
The internal charge pump of this device is generated from
the VDD supply; therefore, care must be taken to provide
sufficient gate-source voltage for the high-side MOSFETs
when VM >> VDD (e.g., VM = 5.0 V, VDD = 3.3 V), in order to
ensure full enhancement of the high-side MOSFET channels.
Figure 8. 17531A Typical Application Diagram
CEMF SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially
damaging CEMF spikes induced when commutating currents
in inductive loads. Typical practice is to provide snubbing of
voltage transients via placing a capacitor or zener at the
supply terminal (VM) (see Figure 9).
PCB LAYOUT
When designing the printed circuit board (PCB), connect
sufficient capacitance between power supply and ground
terminals to ensure proper filtering from transients. For all
high-current paths, use wide copper traces and shortest
possible distances.
Figure 9. CEMF Snubbing Techniques
MCU
17531A
3.3 V
GND
C1L
C1H
C2L
C2H
CRES
IN1B
IN2A
IN2B
PSAVE
VM
VDD
OUT1B
OUT2B
OUT1A
IN1A OUT2A
5.0 V
NC
NC
NC
NC
VCRES < 14 V
RG > VCRES/0.02 Ω
0.01 μF
RG
NC = No Connect
17531A
GND
C1L
C1H
C2L
C2H
CRES
VM
VDD
OUT
OUT
17531A
3.3 V
GND
C1L
C1H
C2L
C2H
CRES
VM
VDD
OUT
OUT
5.0 V
3.3 V 5.0 V
Analog Integrated Circuit Device Data
12 Freescale Semiconductor
17531A
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” drawing number listed below.
EV (Pb-FREE) SUFFIX
20-LEAD VMFP
PLASTIC PACKAGE
98ASA10816D
ISSUE A
Analog Integrated Circuit Device Data
Freescale Semiconductor 13
17531A
PACKAGING
PACKAGE DIMENSIONS
EV (Pb-FREE) SUFFIX
20-LEAD VMFP
PLASTIC PACKAGE
98ASA10816D
ISSUE A
Analog Integrated Circuit Device Data
14 Freescale Semiconductor
17531A
PACKAGING
PACKAGE DIMENSIONS
EV (Pb-FREE) SUFFIX
20-LEAD VMFP
PLASTIC PACKAGE
98ASA10816D
ISSUE A
Analog Integrated Circuit Device Data
Freescale Semiconductor 15
17531A
PACKAGING
PACKAGE DIMENSIONS
Analog Integrated Circuit Device Data
16 Freescale Semiconductor
17531A
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
24-LEAD QFN
PLASTIC PACKAGE
98ARL10577D
ISSUE A
Analog Integrated Circuit Device Data
Freescale Semiconductor 17
17531A
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
24-LEAD QFN
PLASTIC PACKAGE
98ARL10577D
ISSUE A
Analog Integrated Circuit Device Data
18 Freescale Semiconductor
17531A
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
24-LEAD QFN
PLASTIC PACKAGE
CASE 1508-01
ISSUE A
Analog Integrated Circuit Device Data
Freescale Semiconductor 19
17531A
REVISION HISTORY
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES
2.0 9/2005 • Implemented Revision History page
• Converted to Freescale format
3.0 2/2008 • Corrected Table 2, Pin Definitions on page 4.
4.0 5/2009 • Corrected Note 7, in Static Electrical Characteristics table.
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© Freescale Semiconductor, Inc. 2009. All rights reserved.
MPC17531A
Rev. 4.0
5/2009
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fabricate any integrated circuits or integrated circuits based on the
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