FEATURES FUNCTIONAL BLOCK DIAGRAM Envelope threshold detection and latching Broad input frequency range: dc to 6 GHz 1.0 dB input range: 45 dB 1.0 dB input level: -30 dBm to +15 dBm at 100 MHz Programmable threshold and latch reset function Propagation delay: 12 ns typical from RFIN to Q/Q latch All functions temperature and supply stable Operates at 3.3 V from -40C to +105C Quiescent current: 3.5 mA typical Power-down current: 100 A typical 16-lead, 3 mm x 3 mm LFCSP package VPOS ENBL 5 14 7 VIN- RST 16 15 ADL5910 DECL 4 - ENVELOPE DETECTOR RFIN 1 11 3 GND VCAL R Q 12 Q S Q 13 Q + 2 6 8 DNC 9 10 13837-001 Data Sheet DC to 6 GHz, 45 dB Envelope Threshold Detector/Trigger ADL5910 Figure 1. APPLICATIONS Wireless power amplifier input and output protection Wireless receiver input protection RF pulse detection and triggering GENERAL DESCRIPTION The ADL59101 is a radio frequency (RF) detector that operates from dc to 6 GHz. It provides a programmable envelope threshold detection function. The envelope threshold detection function compares the voltage from an internal envelope detector with a user defined input voltage. When the voltage from the envelope detector exceeds the user defined threshold voltage, an internal comparator captures and latches the event to a set or reset (SR) flip flop. The response time from the RF input signal exceeding the user 1 programmed threshold to the output latching is 12 ns. The latched event is held on the flip flop until a reset pulse is applied. The RF input of the ADL5910 is dc-coupled, allowing operation down to arbitrarily low ac frequencies. It operates on a 3.3 V supply and consumes 3.5 mA. Power-down mode reduces this current to 100 A when a logic low is applied to the ENBL pin. The ADL5910 is supplied in a 3 mm x 3 mm, 16-lead LFCSP for operation over the wide temperature range of -40C to +105C. Protected by U.S. Patent 9,379,675. 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ADL5910 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Basic Connections ...................................................................... 11 Applications ....................................................................................... 1 Q and Q Response Time ........................................................... 12 Functional Block Diagram .............................................................. 1 Setting the VIN- Threshold Detection Voltage ........................ 13 General Description ......................................................................... 1 Applications Information .............................................................. 16 Revision History ............................................................................... 2 A Complete Input Protection Circuit ...................................... 16 Specifications..................................................................................... 3 Reset on Enable or at Power-Up ............................................... 17 Absolute Maximum Ratings ............................................................ 7 Improving Frequency Flatness ................................................. 17 Thermal Resistance ...................................................................... 7 Evaluation Board ............................................................................ 19 ESD Caution .................................................................................. 7 Outline Dimensions ....................................................................... 22 Pin Configuration and Function Descriptions ............................. 8 Ordering Guide .......................................................................... 22 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 11 REVISION HISTORY 4/2017--Revision 0: Initial Version Rev. 0 | Page 2 of 22 Data Sheet ADL5910 SPECIFICATIONS VPOS = 3.3 V, continuous wave (CW) input, TA = 25C, and rms capacitance (CRMS) = 10 nF, unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Frequency Range f = 10 MHz 1.0 dB Input Range 1.0 dB Input Level Maximum Minimum VIN- Setpoint Voltage Threshold Variation vs. Temperature f = 30 MHz 1.0 dB Input Range 1.0 dB Input Level Maximum Minimum VIN- Setpoint Voltage Threshold Variation vs. Temperature f = 100 MHz 1.0 dB Input Range 1.0 dB Input Level Maximum Minimum VIN- Setpoint Voltage Threshold Variation vs. Temperature Test Conditions/Comments Min Typ DC Max Unit 6 GHz 45 dB For threshold detection at 10 dBm For threshold detection at 0 dBm For threshold detection at -10 dBm -40C < TA < +85C, RF input power on the RFIN pin (PIN) 10 dBm 15 -30 743 240 80 0.2 dBm dBm mV mV mV dB -40C < TA < +85C, PIN 0 dBm -40C < TA < +85C, PIN -10 dBm -40C < TA < +105C, PIN 10 dBm -40C < TA < +105C, PIN 0 dBm -40C < TA < +105C, PIN -10 dBm -0.3/0 1 -0.5/01 0.2 -0.3/01 -0.5/01 dB dB dB dB dB 45 dB For threshold detection at 10 dBm For threshold detection at 0 dBm For threshold detection at -10 dBm -40C < TA < +85C, PIN 10 dBm 15 -30 723 238 80 0/0.21 dBm dBm V mV mV dB -40C < TA < +85C, PIN 0 dBm -40C < TA < +85C, PIN -10 dBm -40C < TA < +105C, PIN 10 dBm -40C < TA < +105C, PIN 0 dBm -40C < TA < +105C, PIN -10 dBm -0.4/-0.21 -0.4/01 0/0.21 -0.4/-0.21 -0.4/01 dB dB dB dB dB 45 dB For threshold detection at 10 dBm For threshold detection at 0 dBm For threshold detection at -10 dBm -40C < TA < +85C, PIN 10 dBm 15 -30 742 239 81 0.1 dBm dBm mV mV mV dB -40C < TA < +85C, PIN 0 dBm -40C < TA < +85C, PIN -10 dBm -40C < TA < +105C, PIN 10 dBm -40C < TA < +105C, PIN 0 dBm -40C < TA < +105C, PIN -10 dBm -0.4/-0.21 -0.5/01 0.1 -0.4/-0.21 -0.5/01 dB dB dB dB dB Three-point calibration at -25 dBm, -10 dBm, and +10 dBm Three-point calibration at -25 dBm, -10 dBm, and +10 dBm Three-point calibration at -25 dBm, -10 dBm, and +10 dBm Rev. 0 | Page 3 of 22 ADL5910 Parameter f = 900 MHz 1.0 dB Input Range 1.0 dB Input Level Maximum Minimum VIN- Setpoint Voltage Threshold Variation vs. Temperature f = 1900 MHz 1.0 dB Input Range 1.0 dB Input Level Maximum Minimum VIN- Setpoint Voltage Threshold Variation vs. Temperature f = 2600 MHz 1.0 dB Input Range 1.0 dB Input Level Maximum Minimum VIN- Setpoint Voltage Threshold Variation vs. Temperature Data Sheet Test Conditions/Comments Min Typ Max Unit 45 dB For threshold detection at 10 dBm For threshold detection at 0 dBm For threshold detection at -10 dBm -40C < TA < +85C, PIN 10 dBm 17 -28 752 241 81 0.1 dBm dBm mV mV mV dB -40C < TA < +85C, PIN 0 dBm -40C < TA < +85C, PIN -10 dBm -40C < TA < +105C, PIN 10 dBm -40C < TA < +105C, PIN 0 dBm -40C < TA < +105C, PIN -10 dBm -0.2/+0.11 0.1/0.31 0.1 -0.2/+0.11 0.1/0.31 dB dB dB dB dB 45 dB For threshold detection at 10 dBm For threshold detection at 0 dBm For threshold detection at -10 dBm -40C < TA < +85C, PIN 10 dBm 17 -28 774 241 78 -0.2/+0.11 dBm dBm mV mV mV dB -40C < TA < +85C, PIN 0 dBm -40C < TA < +85C, PIN -10 dBm -40C < TA < +105C, PIN 10 dBm -40C < TA < +105C, PIN 0 dBm -40C < TA < +105C, PIN -10 dBm -0.1/01 0.2 -0.2/+0.11 -0.1/01 0.2 dB dB dB dB dB 43.5 dB For threshold detection at 10 dBm For threshold detection at 0 dBm For threshold detection at -10 dBm -40C < TA < +85C, PIN 10 dBm 16 -27.5 775 236 76 -0.3/+0.11 dBm dBm mV mV mV dB -40C < TA < +85C, PIN 0 dBm -40C < TA < +85C, PIN -10 dBm -40C < TA < +105C, PIN 10 dBm -40C < TA < +105C, PIN 0 dBm -40C < TA < +105C, PIN -10 dBm -0.2/01 -0.4/-0.11 -0.3/+0.11 -0.2/01 -0.4/-0.11 dB dB dB dB dB Three-point calibration at -20 dBm, 0 dBm, and +10 dBm Three-point calibration at -20 dBm, 0 dBm, and +10 dBm Three-point calibration at -20 dBm, 0 dBm, and +10 dBm Rev. 0 | Page 4 of 22 Data Sheet Parameter f = 3500 MHz 1.0 dB Input Range Input Level, 1.0 dB Maximum Minimum VIN- Setpoint Voltage Threshold Variation vs. Temperature f = 5800 MHz 1.0 dB Input Range 1.0 dB Input Level Maximum Minimum VIN- Setpoint Voltage Threshold Variation vs. Temperature THRESHOLD DETECT OUTPUT Propagation Delay Output Voltage Low High RESET INTERFACE RST Input Voltage Low High RST Input Bias Current Reset Time COMPARATOR INTERFACE VIN- Input Range VIN- Input Bias Current VIN- for Comparator Disable VCAL INTERFACE VCAL Output Voltage ADL5910 Test Conditions/Comments Min Typ Max Unit 42 dB For threshold detection at 10 dBm For threshold detection at 0 dBm For threshold detection at -10 dBm -40C < TA < +85C, PIN 10 dBm 17 -25 608 177 55 0.2 dBm dBm mV mV mV dB -40C < TA < +85C, PIN 0 dBm -40C < TA < +85C, PIN -10 dBm -40C < TA < +105C, PIN 10 dBm -40C < TA < +105C, PIN 0 dBm -40C < TA < +105C, PIN -10 dBm 0.1 -0.5/-0.11 0.2 0.1 -0.5/-0.11 dB dB dB dB dB 37 dB 19 -18 334 92 29 0.2 dBm dBm mV mV mV dB 0.4 -0.6/+0.41 0.2 0.4 -0.6/+0.41 dB dB dB dB dB 12 12 ns ns Three-point calibration at -18 dBm, 0 dBm, and +10 dBm Three-point calibration at -10 dBm, 0 dBm, and +10 dBm For threshold detection at 10 dBm For threshold detection at 0 dBm For threshold detection at -10 dBm -40C < TA < +85C, PIN 10 dBm -40C < TA < +85C, PIN 0 dBm -40C < TA < +85C, PIN -10 dBm -40C < TA < +105C, PIN 10 dBm -40C < TA < +105C, PIN 0 dBm -40C < TA < +105C, PIN -10 dBm Q, Q, and RST pins, 900 MHz input frequency From RFIN to Q/Q latch RFIN pin = off to 10 dBm, VIN- = 400 mV (5 dB overdrive) RFIN pin = off to -5 dBm, VIN- = 75 mV (5 dB overdrive) Q, Q IOL = 1 mA IOH = 1 mA RST pin 300 mV V 0.6 V V nA ns 3.0 2 20 15 RST at 50% to Q low and Q high VIN- pin 0 to 1.5 -20 V A V 750 825 1.5 mV mV V VPOS VCAL pin RFIN pin = off RFIN pin = -10 dBm, 900 MHz RFIN pin = 10 dBm, 900 MHz Rev. 0 | Page 5 of 22 ADL5910 Parameter POWER-DOWN INTERFACE Voltage Level To Enable To Disable Input Bias Current POWER SUPPLY INTERFACE Supply Voltage Quiescent Current Power-Down Current 1 Data Sheet Test Conditions/Comments ENBL pin Min Typ 2 0 VENBL = 2.2 V VPOS pin Max Unit VPOS 0.6 V V nA 3.45 V mA mA A <20 3.15 TA = 25C, no signal at RFIN TA = 105C, no signal at RFIN ENBL = low The slash indicates a range. For example, -0.3/0 means -0.3 to 0. Rev. 0 | Page 6 of 22 3.3 3.5 4 100 Data Sheet ADL5910 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Supply Voltage, VPOS Input Average RF Power1 Equivalent Voltage, Sine Wave Input Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating 5.5 V 25 dBm 5.62 V peak 150C -40C to +105C -65C to +150C 300C Table 3. Thermal Resistance Package Type CP-16-22 JA1 80.05 JC2 4.4 Unit C/W Thermal impedance simulated value is based on no airflow with the exposed pad soldered to a 4-layer JEDEC board. 2 Thermal impedance from junction to exposed pad on underside of package. 1 Drive this parameter from a 50 source. It is input ac-coupled with an external 82.5 shunt resistor, and VPOS = 3.3 V. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. 0 | Page 7 of 22 ADL5910 Data Sheet 13 Q 14 ENBL 16 VIN- 15 RST PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFIN 1 12 Q DNC 2 ADL5910 11 GND VCAL 3 TOP VIEW (Not to Scale) 10 DNC 9 DNC NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE. 13837-002 DNC 8 VPOS 7 DNC 6 VPOS 5 DECL 4 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic RFIN 2, 6, 8, 9, 10 3 DNC VCAL 4 5, 7 DECL VPOS 11 12, 13 GND Q, Q 14 15 ENBL RST 16 VIN- EPAD Description RF Input. The RFIN pin is dc-coupled and is not internally matched. A broadband 50 match is achieved using an external 82.5 shunt resistor with a 0.47 F ac coupling capacitor placed between the shunt resistor and the RF input. Smaller ac coupling capacitor values can be used if low frequency operation is not required. Do Not Connect. Do not connect to these pins. Threshold Calibration. The voltage on this pin determines the correct threshold voltage that must be applied to Pin 16 (VIN-) to set a particular RF power threshold. This process has two steps: first, measure the output voltage on VCAL with no RF signal applied to RFIN (this voltage is typically 750 mV). Next, apply the RF input power to RFIN, which causes the circuit to trip and again measure the voltage on the VCAL pin. The difference between these two voltages is equal to the threshold voltage that must be applied to VIN- during operation. Internal Decoupling. Bypass this pin to ground using a 4.02 resistor connected in series with a 100 nF capacitor. Power Supply. The supply voltage range = 3.3 V 10%. Place power supply decoupling capacitors on Pin 5. There is no requirement for power supply decoupling capacitors on Pin 7. Device Ground. Connect the GND pin to system ground using a low impedance path. Differential Digital Outputs of Threshold Detection Flip Flop. Q latches high when the output of the internal envelope detector exceeds the threshold voltage on the internal comparator VIN- input. Device Enable. Connect the ENBL pin to logic high to enable the device. Flip Flop Reset. Taking RST high clears the latched flip flop output, setting the Q and Q outputs to low and high, respectively. Inverting Input to the Threshold Detection Comparator. The voltage on this pin is compared to the output voltage of the internal envelope detector, which is driven by the RF input level. If the output voltage of the envelope detector exceeds the voltage on VIN-, the flip flop latches the Q output to high and the Q output to low. Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane. Rev. 0 | Page 8 of 22 Data Sheet ADL5910 TYPICAL PERFORMANCE CHARACTERISTICS VPOS = 3.3 V, input levels referred to 50 source. Input RF signal is a sine wave (CW), unless otherwise noted. 10 VIN- (V) 1 0.01GHz 0.03GHz 0.1GHz 0.9GHz 1.9GHz 2.6GHz 3.6GHz 5.8GHz RFIN 3 2pF 0pF 0.1 0.01 10pF 100pF Q 0 5 10 15 20 PIN (dBm) CH2 1.0V M10ns 20GSPS CH3 100mV T 50ps/pt Figure 3. VIN- vs. PIN at Various Frequencies RFIN RFIN 3 M10ns 20GSPS T 20ps/pt A CH2 1.52V 13837-033 2 Q CH2 1.0V M10ns 20GSPS A CH2 1.52V CH3 1.0V Figure 4. Q Output Response, PIN = Off to 6 dBm, VIN- (400 mV) Set to Trigger at 5 dBm (Overdrive Level = 1 dB) 13837-036 Q CH2 1.0V CH3 500mV Figure 7. Q Output Response, PIN = Off to 10 dBm, VIN- (400 mV) Set to Trigger at 5 dBm (Overdrive Level = 5 dB) RFIN RFIN 3 3 CH2 1.0V CH3 100mV M10ns 20GSPS T 20ps/pt A CH2 1.52V 2 Q CH2 1.0V CH3 100mV Figure 5. Q Output Response, PIN = Off to -9 dBm, Overdrive Threshold Voltage Set to Trigger at -10 dBm (Overdrive Level = 1 dB, VIN- = 75 mV) M10ns 20GSPS A CH2 1.52V 13837-037 Q 13837-034 2 400mV Figure 6. Q Output Response vs. Load Capacitance, PIN = Off to -10 dBm, Overdrive Threshold Voltage Set to Trigger at -11 dBm (Overdrive Level = 1 dB, VIN- = 65 mV) 3 2 A CH2 13837-035 2 -5 13837-039 0.001 -40 -35 -30 -25 -20 -15 -10 Figure 8. Q Output Response, PIN = Off to -5 dBm, Overdrive Threshold Voltage Set to Trigger at -10 dBm (Overdrive Level = 5 dB, VIN- = 75 mV) Rev. 0 | Page 9 of 22 ADL5910 Data Sheet 10 5 INPUT RETURN LOSS (dB) NO EXTERNAL SHUNT 0 RESISTOR ON RFIN RST PULSE 1 Q -5 -10 -15 WITH 82.5 SHUNT RESISTOR ON RFIN -20 -25 -30 CH2 1.0V M20ns 10GSPS A CH1 1.36V -40 Figure 9. Response of Q Output to RST 25 Figure 11. Input Return Loss vs. RF Frequency (With and Without External 82.5 Shunt Resistor on RFIN) from 10 MHz to 6 GHz -40C +25C +85C +105C 15 10 5 0 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 PIN (dBm) 13837-040 SUPPLY CURRENT (mA) 20 RF FREQUENCY 13837-013 CH1 1.0V 13837-038 -35 2 Figure 10. Supply Current vs. PIN for Various Temperatures Rev. 0 | Page 10 of 22 Data Sheet ADL5910 THEORY OF OPERATION BASIC CONNECTIONS The ADL5910 is a threshold detector with a 45 dB of detection range at 1.9 GHz and a useable range up to 6 GHz. It features no error ripple over its range, low temperature drift, and very low power consumption. 5 14 VIN- RST 16 15 7 ADL5910 DECL 4 ENVELOPE DETECTOR 1 11 3 GND VCAL R Q 12 Q S Q 13 Q A single-ended input at the RFIN pin drives the ADL5910. Because the input is dc-coupled, an external ac coupling capacitor must be used. A 470 nF capacitor is recommended for applications that require frequency coverage from 6 GHz down to tens of kilohertz. For applications that do not need such low frequency coverage, a larger value of capacitance can be used. + 2 8 6 9 13837-044 RFIN - 10 DNC Figure 12. Functional Block Diagram In addition to the ac-coupling capacitor, an external 82.5 shunt resistor is required to provide a wideband input match. Figure 11 shows a comparison of the input return loss, with and without the external shunt resistor. The output of the envelope detector drives the noninverting input of a threshold detecting comparator. The inverting input of this comparator is typically driven by a fixed external dc voltage. When the output of the envelope detector exceeds the voltage on the inverting input of the comparator, the comparator goes high. This excursion is then captured and held by an SR flip flop. The state of this flip flop is then held until the level sensitive RST pin is taken high. VIN- = Slope x (VRFIN - Intercept) (1) R x log -1 PIN 10 - Intercept VIN - = Slope x 10 3 (2) The DECL pin provides a bypass capacitor connection for an on-chip regulator. The DECL pin is connected to ground with a 4.02 resistor and a 0.1 F capacitor. The ENBL pin configures the device enable interface. Connecting the ENBL pin to a logic high signal (2 V to VPOS) enables the device, and connecting the pin to a logic low signal (0 V to 0.6 V) disables the device. The exposed pad is internally connected to GND and must be soldered to a low impedance ground plane. THRESHOLD VOLTAGE INPUT VPOS 3.3V 100pF 0.1F ENABLE/ DISABLE RESET INPUT ENBL VPOS 5 14 RST VIN- 7 15 16 ADL5910 - 470nF RFIN RFIN ENVELOPE DETECTOR 1 R Q 12 S Q 13 Q Q Q Q + 82.5 11 GND 4 3 VCAL 2 DECL 10 9 6 8 DNC 4.02 CALIBRATION VOLTAGE OUTPUT 0.1F Figure 13. Basic Connections Rev. 0 | Page 11 of 22 13837-050 VPOS ENBL The ADL5910 requires a single supply of 3.3 V. The supply is connected to the VPOS supply pins. Decouple these pins using two capacitors with values equal or similar to those shown in Figure 13. Place these capacitors as close to Pin 5 as possible. Connect Pin 11 (GND) and the exposed pad to a ground plane with low electrical and thermal impedance. ADL5910 Data Sheet A threshold voltage is applied to the VIN- input that corresponds to the RF power level at which the circuit trips. When the level on RFIN drives the envelope detector to an output voltage that exceeds the programmed threshold, the comparator output goes high causing the Q output to latch high and the Q output to latch low. The levels on Q and Q can be reset by setting the RST pin high (note that the RST function is level triggered, not edge triggered). Q and Q are held at low and high states, respectively, as long as RST is high, even if the RF input level is exceeding the programmed threshold voltage. RST must be taken low for the threshold detection circuit to reactivate. RFIN 3 Figure 14 shows the response of the Q output when the input power exceeds the programmed threshold by approximately 1 dB. The response time from the input power exceeding the threshold to the Q output reaching 50% of its final value is approximately 12 ns. CH2 1.0V CH3 200mV M10ns 20GS/s A CH2 400mV 13837-052 Q 2 Q AND Q RESPONSE TIME Figure 15. Q Output Response, PIN = Off to -5 dBm, Overdrive Threshold Voltage Set to Trigger at -10 dBm (Overdrive Level = 5 dB, VIN- = 75 mV) Figure 16 shows the response of the Q output, which goes low when the input threshold is exceeded. As shown in Figure 16, the response time of Q is equal to that of the Q output. RFIN 3 RFIN 3 Q 2 M10ns 20GS/s A CH2 1.52V 13837-051 CH2 1.0V CH3 100mV Figure 14. Q Output Response at 900 MHz, PIN = Off to -9 dBm, Overdrive Threshold Voltage Set to Trigger at -10 dBm (Overdrive Level = 1 dB) The response time of the Q and Q outputs is somewhat dependent on the level of overdrive with higher overdrive levels, giving a slightly faster response time. Figure 15 shows the response of the Q output when the RF input level overdrives the threshold by 5 dB, which reduces the response time to approximately 12 ns. Overdrive levels beyond 5 dB tend not to reduce the response time below this level. Capacitive loading on Q also affects the response time, as shown in Figure 6. CH2 1.0V CH3 100mV M10ns 20GS/s A CH2 1.36V 13837-053 2 Q Figure 16. Q Output Response, PIN = Off to -7 dBm, Overdrive Threshold Voltage Set to Trigger at -10 dBm (Overdrive Level = 3 dB) Rev. 0 | Page 12 of 22 Data Sheet ADL5910 SETTING THE VIN- THRESHOLD DETECTION VOLTAGE Figure 17 shows the typical relationship between the voltage on the VIN- pin and the RF input power on the RFIN pin This data is also presented in Table 5. 10 VIN- (V) 1 0.01GHz 0.03GHz 0.1GHz 0.9GHz 1.9GHz 2.6GHz 3.6GHz 5.8GHz 0.1 0.001 -40 -35 -30 -25 -20 -15 -10 -5 PIN (dBm) 0 5 10 15 20 13837-054 0.01 Figure 17. Relationship Between the Voltage on the VIN- Pin (VIN-) and the RF Input Power on the RFIN Pin (PIN) Use Figure 17 and Table 5 to set the threshold voltage on the VIN- pin. However, because the relationship between the threshold voltage on VIN- and the resulting RF threshold power varies from device to device, there is an error level of up to 2.5 dB. For example, if the voltage on VIN- is set to cause the circuit to trip when the input power exceeds 0 dBm at 900 MHz (VIN- = 241 mV from Table 5), the trip point can vary from device to device by 2.5 dB at frequencies at or above 100 MHz and +2.5 dB to -5.5 dB for frequencies below 100 MHz. In Table 5, no recommended voltages are provided for input power levels less than -25 dBm from 10 MHz to 3.5 GHz and less than -20 dBm at 5.8 GHz because of the increased temperature drift at these input power levels. Likewise, from 10 MHz to 3.5 GHz, no recommended voltages are provided for input power levels more than 13 dBm because at this power level the response of the ADL5910 starts to become more nonlinear. To set the threshold detect level more precisely, there are two calibration options. A single-point calibration is accomplished easily by applying the threshold trip power level and then adjusting VIN- until Q trips high. Initially, set VIN- to a high level such as 2 V, and then assert RST high and back to low to ensure that Q is low. Next, apply the RF input threshold power level to RFIN. Then, reduce the voltage on VIN- until the Q output goes high. Use this resulting voltage to set the threshold level when the equipment is in operation. Rev. 0 | Page 13 of 22 ADL5910 Data Sheet Table 5. Recommended Typical Values for Threshold Voltage (VIN-) When Operating Uncalibrated Input Threshold Power (dBm) -25.0 -24.0 -23.0 -22.0 -21.0 -20.0 -19.0 -18.0 -17.0 -16.0 -15.0 -14.0 -13.0 -12.0 -11.0 -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 +1.0 +2.0 +3.0 +4.0 +5.0 +6.0 +7.0 +8.0 +9.0 +10.0 +11.0 +12.0 +13.0 +14.0 +15.0 1 10 MHz 18 19 21 23 25 28 31 34 37 41 47 52 58 64 71 80 88 98 110 123 137 154 172 193 214 240 269 300 336 376 421 472 529 592 664 743 858 939 1078 N/A N/A 30 MHz 18 19 21 23 25 28 31 34 38 42 47 52 58 64 72 80 89 99 111 123 137 153 172 192 214 238 266 298 334 374 419 466 522 585 652 723 844 957 1072 N/A N/A 100 MHz 18 20 22 24 26 29 32 35 39 43 48 53 59 66 73 81 90 101 112 125 139 155 173 193 216 239 268 300 336 377 421 471 528 591 663 742 830 927 1005 N/A N/A Threshold Voltage (mV) 1 900 MHz 1900 MHz 2600 MHz 17 16 17 18 17 18 20 19 20 22 21 22 25 23 24 27 26 26 31 29 29 34 32 32 38 36 35 42 40 39 47 45 44 52 50 49 58 56 54 65 62 60 72 70 68 81 78 76 90 87 84 101 97 94 112 109 105 125 122 118 139 136 132 155 153 148 173 171 167 193 192 186 216 215 210 241 241 236 272 270 266 304 303 298 340 341 337 380 383 380 425 431 425 477 485 481 534 543 544 598 611 610 670 688 690 752 774 775 842 871 875 942 976 982 1047 1066 1061 N/A N/A N/A N/A N/A N/A N/A means not applicable. Rev. 0 | Page 14 of 22 3500 MHz 12 13 14 15 17 19 21 23 25 28 31 35 39 44 49 55 61 69 77 87 98 110 124 140 158 177 200 226 255 289 327 370 419 474 537 608 684 774 876 N/A N/A 5800 MHz N/A N/A N/A N/A N/A 11 12 13 14 16 17 19 21 23 26 29 32 36 40 45 51 57 64 73 81 92 104 119 135 153 175 199 225 257 293 334 381 434 495 564 642 Data Sheet ADL5910 Alternatively, by measuring the voltage on the VCAL output pin with and without RF power applied, an equation can be derived that establishes a precise relationship between the VIN- voltage and the associated RF input power trip point. Within the linear operating range of the ADL5910, there is a linear relationship between VCAL - VCALOFF and the input voltage on RFIN. VCAL - VCALOFF = Slope x (VRFIN - Intercept) VRFIN = 1. 2. (3) where: VCAL is the measured output voltage on the VCAL pin. VCALOFF is the measured output voltage on the VCAL pin with no RF input signal applied. VRFIN is the RF input power (in dBm) converted into volts rms, that is, P R x log -1 IN 10 103 Use a two-point or a three-point calibration to establish the slope and intercept values in Equation 6. The procedure for a twopoint calibration follows: 3. 4. (4) voltage on the VCAL pin (VCALHIGH) pin. Calculate the slope by using the following equation: 5. Calculate the intercept by using the following equation: Intercept = VRFIN - (VCAL - VCALOFF)/Slope When the slope and intercept are known, insert them into Equation 6, where PTHRESHOLD is the desired RF power level at which the circuit trips. Rewriting the equation results in VCAL - VCALOFF = (5) The voltage that must be applied to the VIN- pin for a particular input power is equal to (VCAL - VCALOFF). Therefore, Equation 5 can be rewritten as R x log -1 PIN 10 - Intercept VIN - = Slope x 103 VCAL pin (VCALLOW). Apply an RF input power that is toward the maximum limit of the RF input range (RFINHIGH). Calculate the associated input voltage ( VRFIN HIGH ) and measure the Slope = (VCALHIGH - VCALLOW)/( VRFIN HIGH - VRFIN LOW ) where: R is the characteristic impedance (usually 50 ). PIN is the RF input power on the RFIN pin in dBm. R x log -1 PIN 10 Slope x Intercept - 103 With no RF input signal applied, measure the voltage on the VCAL pin (VCALOFF). Apply an RF input power that is toward the minimum limit of the RF input range (RFINLOW). Calculate the associated input voltage ( VRFIN LOW ) and measure the voltage on the (6) Rev. 0 | Page 15 of 22 R x log -1 PTHRESHOLD 10 VIN - = Slope x - Intercept 10 3 ADL5910 Data Sheet APPLICATIONS INFORMATION A COMPLETE INPUT PROTECTION CIRCUIT The coupled signal is applied to the RF input of the ADL5910. Because of the coupling factor of 20 dB, the ADL5910 must be configured to respond to input levels in excess of 2.5 dBm. As is shown in Table 5 and Figure 18, the threshold level on VIN- must be set to approximately 300 mV. If high triggering precision is required, perform calibration because the threshold voltage for a particular input power level varies from device to device. Figure 18 shows a block diagram of a complete input protection circuit that protects the input to a power amplifier or the input to a receiver to frequencies of approximately 2.6 GHz. This circuit consists of a single-pole, single throw (SPST) switch (for this example, the HMC550A), an asymmetrical power splitter/coupler circuit, and the ADL5910. The main signal path is through the coupler and SPST switch. The circuit in this example protects against input levels to the receiver or the power amplifier that exceed 20 dBm. When the output of the ADL5910 triggers after an overdrive event, the Q output goes low and opens the HMC550A switch. When the HMC550A switch is open, the attenuation in the signal path increases to the specified isolation of the HMC550A switch and the insertion loss of the coupler, ranging from 15 dB to 40 dB based on frequency. Under normal operation, the switch is closed. The closed switch results in insertion loss, which is the sum of the switch insertion loss and the insertion loss of the splitter/coupler. In the example shown in Figure 18, the coupling factor is 20 dB, which results in an insertion loss of 1.72 dB. Different resistor values can reduce the insertion loss, which results in a lower level on the coupled signal. The insertion loss of the switch is approximately 0.7 dB, resulting in a total insertion loss of approximately 2.5 dB. In the example shown in Figure 18, the Q output also drives an interrupt input of a microprocessor or microcontroller. Program the microprocessor or microcontroller to issue short periodic reset pulses. After each reset pulse, the ADL5910 either remains reset (if the input level drops below the threshold) or reopens the switch. 2.5dB INSERTION LOSS HMC550A RFIN (22.5dBm MAXIMUM) 4.99 4.99 RFIN (20dBm MAXIMUM) 220 20dB RECEIVER OR POWER APLIFIER 62 MICROPROCESSOR 300mV RESET VIN- 16 15 RST ADL5910 Q 0.47F 1 RFIN ENVELOPE DETECTOR R Q 12 S Q 13 INT Q 82.5 3 VCAL 13837-218 RFIN (2.5dBm MAXIMUM) Figure 18. A Complete Input Protection Circuit (Power Supply and Decoupling Omitted for Clarity) Rev. 0 | Page 16 of 22 Data Sheet ADL5910 RESET ON ENABLE OR AT POWER-UP IMPROVING FREQUENCY FLATNESS The ADL5910 normally powers up with the Q and Q outputs high and low, respectively. If a logic low on the Q output is required on power-up or enable, use the circuit shown in Figure 19. This circuit consists of a capacitor from ENBL to RST and a resistor from RST to ground. When ENBL is asserted, the RST voltage goes high shortly before being pulled back to 0 V by R5. For applications where input protection is required over a wide range of input frequencies, use the application circuit shown in Figure 20 to compensate for the frequency roll-off of the ADL5910 detector. Across its full range, the frequency response of ADL5910 varies by approximately 9 dB with most of the variation between 2 GHz and 6 GHz. As a result, higher power levels are required at higher frequencies to trip the internal comparator (assuming a constant threshold voltage on the VIN- input pin to the comparator). To compensate for this roll-off, insert a preemphasis filter in front of the RF input. The attenuation of this filter decreases with increasing frequency, resulting in an overall flatter response in the combined filter/detector circuit. When the ENBL pin is not used (that is, ENBL is tied to VPOS), tie the C3 capacitor directly to VPOS. C11 100pF AGND R5 10k AGND C12 0.1F 3.3V C3 100nF VPOS VPOS ENBL YEL 5 RFIN RFIN C2 0.1F VCAL Q 3 Q Q 13 15 16 9 10 11 13837-219 8 PAD 6 DNC DNC 2 GND VIN- ADL5910 14 DNC RST DNC ENBL Q 12 DECL 4 DNC R6 82.5 7 1 5 RFIN VCAL R13 68.1 R6 68.1 ENBL L1 2.2nH L2 2.2nH 3 Q DECL 4 RST AGND VIN- 12 ADL5910 14 Q 16 AGND 6 DNC DNC 2 AGND 13 15 8 9 10 11 PAD R11 68.1 7 1 AGND 13837-220 R10 82.5 VPOS C2 0.1F DNC C5 15pF GND C4 0.8pF DNC R14 49.9 DNC RFIN_EXT R12 121 VPOS Figure 19. Reset of Q Output on Power-Up/Enable (Additional Connections Omitted for Clarity) Figure 20. Recommended Schematic for Improving Flatness vs. Frequency Using a Preemphasis Circuit Rev. 0 | Page 17 of 22 ADL5910 Data Sheet Figure 21 shows the frequency response of this circuit along with the response with no compensation. In this example, the threshold voltage on VIN- was set to 30 mV. 50 1: 500MHz, -34.290dB 2: 2GHz, -26.517dB 3: 4GHz, -23.686dB 4: 6GHz, -9.1210dB 40 TRIP LEVEL VARIATION WITH NO COMPENSATION TRIP LEVEL VARIATION WITH COMPENSATION 30 20 0 10 S11 (dB) 2 -2 -4 0 4 -10 -20 -6 -30 -40 3 2 -8 1 -50 -12 START 1MHz IFBW 10kHz FREQUENCY (Hz) -14 0.01 0.1 1 FREQUENCY (GHz) 10 Figure 21. Variation in Threshold Trip Point with and Without Frequency Pre-Emphasis Rev. 0 | Page 18 of 22 STOP 6.001GHz 13837-222 -10 13837-221 TRIP LEVEL (dBm) 4 Figure 22 shows the measured input return loss of the circuit. Figure 22. Input Return Loss of ADL5910 with Pre-Emphasis Circuit Data Sheet ADL5910 EVALUATION BOARD potentiometer, R8 (an external voltage can also be applied to the VNEXT SMA connector or to the VIN- yellow test loop). The ADL5910-EVALZ is a fully populated, 4-layer, FR4 evaluation board that includes an SPST and an asymmetrical power coupling circuit. In its default configuration, the circuit operates as a complete input protection circuit that can connect to the input of a receiver or a power amplifier. A single 3.3 V power supply (VPOS) and GND test loops provide power for the complete board. When the RF input level exceeds the equivalent voltage level on VIN-, the Q output of the ADL5910 opens the HMC550A, which increases the signal path attenuation to between -40 dB and -20 dB (based on the input frequency). The inline attenuation is the off isolation of the switch. An overdrive trigger also turns on a flashing LED on the evaluation board that is driven by the Q output of the ADL5910. To reset the ADL5910 outputs, press the S1 push down switch. The primary signal path on the evaluation board is from the RFIN_SW SMA connector to the RFOUT_SW SMA connector. In this path, there is a HMC550A SPST switch and an asymmetrical power splitter/coupler. The insertion loss of the splitter/coupler is 1.72 dB, which combines with the insertion loss of HMC550A (0.7 dB typical) to product a total signal path loss of approximately 2.5 dB. The evaluation board can also be configured for standalone testing of the ADL5910 by removing R16, placing a 0 resistor on the R9 pad, and applying the RF input signal on the RFIN_ADL5910 SMA connector. The coupling factor of the splitter/coupler is 20 dB, that is, the signal level between R47 and R45 with respect to the signal level at the input of R46. The evaluation board also includes a series of pads in the signal chain that are adjacent to the RF input of the ADL5910. Place capacitors and inductors on these pads to improve RF flatness (see the Applications Information section). The coupled signal is applied at the RF input of ADL5910. The threshold level of the ADL5910 is set by an on-board mechanical Detailed configuration options for the evaluation board are listed in Table 6. VPOS R17 100 C115 0.01F C111 1000pF AGND R15 Q 0 4 VDD U23 6 VCTL C14 RFIN_SW 1 C1 1 RF1 0.47F 5 4 3 2 RF2 0.47F JOHNSON142-0701-851 AGND C11 100pF AGND C12 0.1F ENBL YEL 4 1.1k R1 1.1k 09 03201 02 S2 3 1 2 R16 0 AGND RFIN_ADL5910 1 0 L2 TBD0402 TBD0402 DNI DNI 1 TCAL YEL 1.1k R7 R4 4.02 AGND AGND R8 1k AGND 1 VNEXT VIN- YEL C13 0.1F 5 4 3 2 5 VPOS 7 VPOS 0.47F R6 VPOS 82.5 RFIN TCAL DECL ENBL RST VIN- Q Q 12 13 AGND U1 Q TBD0402 ADL5910 Q 1 R9 DNI YEL JOHNSON142-0701-851 AGND Q YEL 1 R36 1k AGND DS1 SSL-LX5093BSRD AGND AGND 1 5 4 3 2 JOHNSON142-0701-851 13837-223 L1 TBD0402 DNI 1 3 4 14 15 16 0 AC R13 TBD0402 DNI R10 DNC DNC DNC DNC DNC GND PAD C2 C5 TBD0402 DNI AGND 62 R3 C3 TBD0603 DNI CW R11 TBD0402 DNI 2 S1 2 6 8 9 10 11 PAD 0 C4 JOHNSON142-0701-851 AGND R45 1 VPOS R14 R47 220 AGND B3S-1000 3 1 R12 R2 4.99 5 4 3 2 R5 10k AGND AGND RFOUT_SW 1 R46 4.99 3 GND GND 2 5 HMC550AE AGND Figure 23. Evaluation Board Schematic Rev. 0 | Page 19 of 22 Data Sheet 13837-224 ADL5910 Figure 24. Evaluation Board Layout Table 6. Evaluation Board Configuration Options Component RFIN_SW, RFOUT_SW, R2, R45, R46, R47 Function RF switch path RFIN_ADL5910, R9, R16 RF input R6, R10 to R14, C2, C4, C5, L1, L2 Input preemphasis and termination network TCAL, R7, R8, VNEXT, VIN- VCAL threshold calibration Notes To operate the full input protection circuit, route the input signal through the RFIN_SW and RFOUT_SW SMA connectors. The values of the R46, R2, R47, and R45 resistors determine the coupling factor (20 dB) and insertion loss of the asymmetrical splitter/coupler. To drive the ADL5910 directly and bypass the coupler/switch circuit, apply the RF input signal to the RFIN_ADL5910 SMA. To operate in this mode, remove R16 and place a 0 resistor on R9. The resistance on R6 combines with the internal impedance to provide a broad 50 input match. C2 provides ac coupling between R6 and the RF inpu.t (The RF input of the ADL5910 is internally dc-coupled.) A broadband 50 match is achieved using 82.5 on R6 and a 0.47 F ac coupling capacitor on C2. A pre-emphasis network can be implemented by placing capacitors and inductors on the pads to the left of R6. The output voltage from the threshold calibration pin (VCAL, Pin 3) is available on the yellow TCAL clip lead. Use the voltage on this pin to determine the correct threshold voltage that must be applied to Pin 16 (VIN-) to set a particular RF power threshold. This process includes two steps. First, measure the output voltage on the TCAL yellow clip lead with no RF signal applied to RFIN (this voltage is approximately 750 mV). Second, apply the RF input power to RFIN, which causes the circuit to trip, and again measure the voltage on the TCAL yellow clip lead. The difference between these two voltages is equal to the voltage that must be applied to VIN- during operation. This voltage can be applied either to the VNEXT SMA connector or to the VIN- yellow clip lead. This voltage can also be set by the R8 mechanical potentiometer on the board. Rev. 0 | Page 20 of 22 Default Values 1 R2, R46 = 4.99 (0402), R45 = 62 (0402), R47 = 220 (0402) R9 = open/DNI (0402), R16 = 0 (0402) R6 = 82.5 , R10 = 0 (0402) R11, R13 = open/DNI (0402), R12, R14 = 0 (0402), C2 = 0.47 F, C4, C5 = open/DNI (0402), L1, L2 = open/DNI (0402) R7 = 1.1 k (0603), R8 = 1 k (mechanical potentiometer) Data Sheet ADL5910 Component VPOS, GND, C11, C12 Function Power supply interface Q, Q, R36, DS1 Threshold detect output (Q and Q) ENBL, S2, R1 Enable interface S1 push-button switch, R3, R5, C3 Threshold detect reset R4, C13 Decoupling network for the DECL pin 1 Notes Apply the 3.3 V power supply for the evaluation board to the VPOS (red) and GND (black) test loops. The nominal supply decoupling consists of a 100 pF capacitor and a 0.1 F capacitor, with the 100 pF capacitor placed closest to the VPOS pin (Pin 5). The threshold detect flip flop outputs (Q and Q) are available on the Q and Q yellow test loops. The Q output drives the DS1 flashing LED. Apply 3.3 V to the ENBL yellow test loop or assert the S2 switch, to enable the ADL5910. The enable voltage must be equal to but not greater than the 3.3 V supply voltage. R1 provides current limiting in case a voltage is connected to the ENBL test loop when Switch S2 is in Position 3. The threshold detection flip flop is reset by using the RST push button switch. The RST switch is connected to the VPOS supply voltage through a 1.1 k resistor (R3). A 10 k pull-down resistor (R5) is connected to the RST pin, which pulls RST low in the absence of any other stimulus. The ADL5910 normally powers up with the Q and Q outputs high and low, respectively. To implement a reset on the power-up circuit, install a capacitor (C3). When ENBL is asserted, RST goes high shortly before being pulled back low by R5. Resistor R4 and Capacitor C13 provide decoupling for the DECL pin of the ADL5910. DNI means do not install. Rev. 0 | Page 21 of 22 Default Values 1 C12 = 0.1 F (0402), C11 = 100 pF (0402), VPOS = 3.3 V R36 = 1 k R1 = 1.1 k (0603) R3 = 1.1 k (0603), R5 = 10 k (0603), C3 = open/DNI (0603) R4 = 4.02 (0402), C13 = 0.1 F (0402) ADL5910 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR AREA OPTIONS 16 (SEE DETAIL A) 12 1 1.75 1.60 SQ 1.45 EXPOSED PAD 9 TOP VIEW 0.80 0.75 0.70 TOP VIEW PKG-005138 SEATING PLANE 0.50 0.40 0.30 4 8 5 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. 02-23-2017-E PIN 1 INDICATOR 3.10 3.00 SQ 2.90 Figure 25. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5910ACPZN-R7 ADL5910-EVALZ 1 Temperature Range -40C to +105C Package Description 16-Lead LFCSP, 7'' Tape and Reel Evaluation Board Z = RoHS Compliant Part. (c)2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13837-0-4/17(0) Rev. 0 | Page 22 of 22 Package Option CP-16-22 Branding Q28 Ordering Quantity 3000