GS1524A Adaptive Cable Equalizer
1 of 16GS1524A Adaptive Cable Equalizer
Data Sheet
28852 - 5 June 2009
www.gennum.com
Features
• SMPTE 292M, SMPTE 344M and SMPTE 259M
compliant
•Automatic cable equalization
• Multi-standard operation from 143Mb/s to 1.485Gb/s
• Supports DVB-ASI at 270Mb/s
• Pb-free and RoHS Compliant
• Pin compatible with the GS9064 Cable Equalizer
• Manual bypass (useful for low data rates with slow
rise/fall times)
• Performance optimized for 270Mb/s and 1.485Gb/s
• Typical equalized length of Belden 1694A cable: 200m
at 1.485Gb/s, 350m at 270Mb/s
•50Ω differential output (with internal 50Ω pull-ups)
• Manual output mute or programmable mute based on
max cable length adjust
• Cable length indicator for SMPTE 259M inputs
• Single 3.3V power supply operation
• Operating temperature range: 0°C to +70°C
Applications
• SMPTE 292M, SMPTE 344M and SMPTE 259M Coaxial
Cable Serial Digital Interfaces.
Description
The GS1524A is a second-generation high-speed BiCMOS
integrated circuit designed to equalize and restore signals
received over 75
Ω
co-axial cable
.
The GS1524A is designed to support SMPTE 292M, SMPTE
344M and SMPTE 259M, and is optimized for performance
at 270Mb/s and 1.485Gb/s.
The GS1524A features DC restoration to compensate for
the DC content of SMPTE pathological test patterns. The
device also incorporates a Cable Length Indicator (CLI) that
provides an indication of the amount of cable being
equalized for data rates up to 360Mb/s.
A voltage programmable mute threshold (MCLADJ) is
included to allow muting of the GS1524A output when an
approximate selected cable length is reached for SMPTE
259M signals. This feature allows the GS1524A to
distinguish between low amplitude SD-SDI signals and
noise at the input of the device.
The bidirectional CD/MUTE pin indicates the presence of a
valid signal at the input of the GS1524A in addition to
functioning as a mute control input. The outputs of the
GS1524A will be forced to a mute state when an invalid
input reference signal is applied to the input of the device
or the application layer sets the CD/MUTE pin HIGH. If the
application layer forces CD/MUTE LOW, the serial digital
output of the device will always be active.
Power consumption is typically 265mW using a 3.3V
power supply.
The GS1524A is Pb-free, and the encapsulation compound
does not contain halogenated flame retardant (RoHS
Compliant).
GS1524A Adaptive Cable Equalizer
Data Sheet
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GS1524A Functional Block Diagram
Revision History
CABLE LENGTH INDICATOR/ADJUSTOR
CARRIER DETECT
MUTE
EQUALIZER DC RESTORE OUTPUT
AGC
CLI
CD/MUTE
SDO
BYPASS
SDOSDI
SDI
MCLADJ
Version ECR PCN Date Changes and/or Modifications
6 152097 – June 2009 Removed ‘Proprietary & Confidential’ from footer.
Updated document format.
5 147547 – September
2007
Corrected P/N in Ordering Information.
4 147532 – September
2007
Added P/N to Ordering Information.
3 141578 40438 August 2006 Added 200m output cable length jitter data at
1.485Gb/s in AC Electrical Characteristics and clarified
0m cable length input voltage swing condition.
Modified 200m cable length in Features section and
Detailed Description.
2 137826 – August 2005 Corrected process to BiCMOS.
1 136832 – May 2005 Updated document status to Data Sheet. Updated all
‘Green’ references to say ‘RoHS Compliant’. Clarified
naming of solder reflow profiles and re-ordered
profiles to show preference for Pb-free profile.
Removed ‘Proprietary and Confidential’ footer.
Corrected minor typing errors.
0 135247 – December 2004 Changed to Preliminary Data Sheet. Removed
references to GS9064A. Updated AC, DC and Absolute
Maximum Ratings tables. Added solder reflow profiles.
Added Packaging Data information. Corrected minor
typing errors.
A 131284 – March 2004 New document.
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Data Sheet
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Contents
Features.................................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
Revision History .................................................................................................................................................2
1. Pin Out...............................................................................................................................................................4
1.1 GS1524A Pin Assignment ..............................................................................................................4
1.2 GS1524A Pin Descriptions .............................................................................................................5
2. Electrical Characteristics ............................................................................................................................6
2.1 Absolute Maximum Ratings ..........................................................................................................6
2.2 DC Electrical Characteristics ........................................................................................................6
2.3 AC Electrical Characteristics ........................................................................................................7
3. Input / Output Circuits ................................................................................................................................9
4. Detailed Description.................................................................................................................................. 10
4.1 Serial Digital Inputs ...................................................................................................................... 11
4.2 Cable Equalization ........................................................................................................................ 11
4.3 Programmable Mute Output and Cable Length Indicator ............................................... 11
4.4 Mute and Carrier Detect .............................................................................................................. 12
5. Application Information .......................................................................................................................... 13
5.1 PCB Layout ....................................................................................................................................... 13
5.2 Typical Application Circuits ...................................................................................................... 13
6. Package & Ordering Information .......................................................................................................... 14
6.1 Package Dimensions ..................................................................................................................... 14
6.2 Packaging Data ............................................................................................................................... 14
6.3 Solder Reflow Profiles .................................................................................................................. 15
6.4 Ordering Information ................................................................................................................... 16
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Data Sheet
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1. Pin Out
1.1 GS1524A Pin Assignment
Figure 1-1: 16-Pin SOIC
CLI
VCC
VEE
SDI
SDI
VEE
AGC+
AGC-
CD/MUTE
VCC
VEE
SDO
SDO
VEE
MCLADJ
BYPASS
GS1524A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
(top view)
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Data Sheet
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1.2 GS1524A Pin Descriptions
Table 1-1: GS1524A Pin Descriptions
Pin Number Name Timing Type Description
1CLI Analog Output Cable Length Indicator.
An analog voltage will be output proportional to the cable length
connected to the serial digital input.
NOTE: CLI is recommended for data rates up the 360Mb/s only.
2, 15 VCC Analog Power Most positive power supply connection.
Connect to +3.3V DC.
3, 6, 11, 14 VEE Analog Power Most negative power supply connection.
Connect to GND.
4, 5 SDI, SDI Analog Input Serial digital differential input.
7, 8 AGC+,
AGC-
Analog – External AGC capacitor.
Connect pin 7 and pin 8 together through a 1uF capacitor.
9BYPASS Not
Synchronous
Input Forces the Equalizing and DC RESTORE stages into bypass mode
when HIGH. No equalization occurs in this mode.
10 MCLADJAnalog Input Maximum cable length adjust.
Adjusts the approximate maximum amount of cable to be equalized
(from 0m to the maximum cable length). The output is muted
(latched to the last state) when the maximum cable length is
achieved.
NOTE: MCLADJ is only recommended for data rates up to 360Mb/s.
12, 13 SDO, SDO Analog Output Equalized serial digital differential output.
16 CD/MUTE Not
Synchronous
Bidirectiona
l
STATUS SIGNAL OUTPUT / CONTROL SIGNAL INPUT
levels are LVCMOS/LVTTL compatible.
OUTPUT (CD):
Indicates the presence of a valid input signal. When the CD pin is
LOW, a valid input signal has been detected. When this pin is HIGH,
the input signal is invalid. If CD is set HIGH, the serial digital output
of the device will be forced to a steady state (latched to the last
state).
NOTE: This pin will indicate loss of carrier for data rates > 19Mb/s.
INPUT (MUTE):
When the MUTE pin is set HIGH by the application interface, the
serial digital output of the device will be forced to a steady state
(latched to the last state). When the MUTE pin is set LOW, the serial
digital output of the device will be active.
NOTE: The CD/MUTE pin is not functional when BYPASS is set HIGH.
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Data Sheet
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
2.2 DC Electrical Characteristics
Parameter Value
Supply Voltage -0.5V to +3.6 VDC
Input ESD Voltage 2kV
Storage Temperature Range -50°C < Ts < 125°C
Input Voltage Range (any input) -0.3 to (VCC +0.3)V
Operating Temperature Range 0°C to 70°C
Solder Reflow Temperature 260°C
Table 2-1: DC Electrical Characteristics
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
Supply Voltage VCC – 3.135 3.3 3.465 V ±5%
Power Consumption PDTA = 25°C– 265 – mW –
Supply Current IsTA = 25°C–80–mA–
Output Common Mode
Voltage
VCMOUT TA = 25°C–V
CC - ΔVSDO/2 – V –
Input Common Mode
Voltage
VCMIN TA = 25°C–1.75–V–
CLI DC Voltage (0m) – TA = 25°C–2.5–V–
CLI DC Voltage (no signal) – TA = 25°C–1.9–V–
MCLADJ DC Voltage (to
mute signal)
–0m, T
A = 25°C–1.3–V–
MCLADJ Range – TA = 25°C–0.69–V–
CD/MUTE Output Voltage VCD/MUTE(OH) Carrier not
present
2.4 – – V –
VCD/MUTE(OL) Carrier present – – 0.4 V –
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2.3 AC Electrical Characteristics
CD/MUTE Input Voltage
Required to Force Outputs
to Mute
VCD/MUTE Mute 2.0 – – V –
CD/MUTE Input Voltage
Required to Force Outputs
Active
VCD/MUTE Activate – – 0.8 V –
Table 2-1: DC Electrical Characteristics (Continued)
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
Table 2-2: AC Electrical Characteristics
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
Serial input data rate DRSDO GS1524A 143 – 1485 Mb/s –
Input Voltage Swing ΔVSDI TA =25°C, at transmitter 720 800 950 mVp-p 0m cable
length
Output Voltage Swing ΔVSDO 50Ω load, TA =25°C,
differential
–750–mV
p-p –
Output Jitter for Various
Cable Lengths and Data
Rates
– 270Mb/s
Belden 1694A: 0-350m
Belden 8281: 0-280m
– 0.2 – UI 1,4
– 1.485Gb/s
Belden 1694A: 0-140m
Belden 8281: 0-100m
–0.25– UI 1,4
– 1.485Gb/s
Belden 1694A: 140-200m
– 0.3 – UI 3,4
Output Rise/Fall time – 20% - 80% – 80 220 ps –
Mismatch in rise/fall time – – – – 30 ps –
Duty cycle distortion – – – – 30 ps –
Overshoot – – – – 10 % –
Input Return Loss – – 15 – – dB 2
Input Resistance – single ended – 1.64 – kΩ–
Input Capacitance – single ended – 1 – pF –
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Figure 2-1: Test Circuit
Output Resistance – single ended – 50 – Ω–
NOTES:
1. All parts production tested. In order to guarantee jitter over the full range of specification (VCC = 3.3V ±5%, TA = 0°C to 70°C, and
720-880mV launch swing from the SDI cable driver) the recommended applications circuit must be used.
2. Tested on CB1524 board from 5MHz to 2GHz.
3. Based on characterization data using the recommended applications circuit, at VCC = 3.3V, TA = 25°C, and 800mV launch swing from the SDI
cable driver.
4. Equalizer Pathological test signal is used.
Table 2-2: AC Electrical Characteristics (Continued)
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
GigaBERT
1400
EXT.
CLOCK
CLOCK
OUT
DATA
OUT
EXT.
CLOCK
1.485GHz/270MHz
GS1524A
TEST BOARD TDS 820
CH. 1
CH. 2
OUTIN
OUT
EXT. TRIGGER
50/75
8281 or 1694A CABLE
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3. Input / Output Circuits
Figure 3-1: Input Equivalent Circuit
Figure 3-2: MCLADJ Equivalent Circuit
Figure 3-3: Output Circuit
3k
3.6k
3k
3.6k
RC
SDI SDI
VCC
MCLADJ
12k
150µ
+
-
50
50
SDOSDO
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Data Sheet
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Figure 3-4: CLI Output Circuit
Figure 3-5: CD/MUTE Circuit
Figure 3-6: Bypass Circuit
4. Detailed Description
The GS1524A is a high speed BiCMOS IC designed to equalize serial digital signals.
The GS1524A can equalize both HD and SD serial digital signals, and will typically
equalize 200m of Belden 1694A cable at 1.
485Gb/
s and 350m at 270Mb/s.
The GS1524A/ is powered from a single +3.3V power supply and consumes
approximately 265mW of power.
10k
10k
VCC
CLI
-
+
CD/MUTE
BYPASS
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4.1 Serial Digital Inputs
The serial data signal may be connected to the input pins (SDI/SDI) in either a
differential or single ended configuration. AC coupling of the inputs is recommended, as
the SDI and SDI inputs are internally biased at approximately 1.8V.
4.2 Cable Equalization
The input signal passes through a variable gain equalizing stage whose frequency
response closely matches the inverse of the cable loss characteristic. In addition, the
variation of the frequency response with control voltage imitates the variation of the
inverse cable loss characteristic with cable length.
The edge energy of the equalized signal is monitored by a detector circuit which
produces an error signal corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is integrated by both an internal and
an external AGC filter capacitor providing a steady control voltage for the gain stage. As
the frequency response of the gain stage is automatically varied by the application of
negative feedback, the edge energy of the equalized signal is kept at a constant level
which is representative of the original edge energy at the transmitter. The equalized
signal is also DC restored, effectively restoring the logic threshold of the equalized signal
to its correct level independent of shifts due to AC coupling. The digital output signals
have a nominal voltage of 750mVpp differential, or 375mVpp single ended when
terminated with 50Ω as shown in Figure 4-1.
Figure 4-1: Typical Output Voltage Levels
4.3 Programmable Mute Output and Cable Length Indicator
For SMPTE 259M inputs, the GS1524A incorporates a programmable threshold output
mute (MCLADJ) and an analog cable length indicator (CLI).
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MCLADJ
In applications where there are multiple input channels using the GS1524A, it is
advantageous to have a programmable mute output to avoid signal crosstalk.
The output of the GS1524A can be muted when the input signal decreases below a
certain input level. This threshold is determined using the input voltage applied to the
MCLADJ pin. The MCLADJ pin may be left unconnected for applications where output
muting is not required.
This feature has been designed for use in applications such as routers where signal
crosstalk and circuit noise cause the equalizer to output erroneous data when no input
signal is present. The use of a Carrier Detect function with a fixed internal reference
does not solve this problem since the signal to noise ratio on the circuit board could be
significantly less than the default signal detection level set by the on chip reference.
NOTE: MCLADJ is only recommended for data rates up to 360Mb/s.
CLI
The output voltage of the CLI pin is an approximation of the amount of cable present at
the GS1524A input. With 0m of cable, 800mV input signal levels, and a data rate of
270Mb/s, the CLI output voltage is approximately 2.5V. As the cable length increases,
the CLI voltage decreases providing an approximate correlation between the CLI
voltage and cable length.
NOTE: CLI is only recommended for data rates up to 360Mb/s.
4.4 Mute and Carrier Detect
In addition to the programmable mute output and cable length indicator, the GS1524A
includes a multi-function CD/MUTE bidirectional pin that provides the following
functions:
INPUT (MUTE)
Applying a HIGH INPUT to the CD/MUTE pin forces the GS1524A outputs to a muted
condition. The minimum voltage required to force the outputs to a muted condition is
listed in the DC electrical characteristics table. In this condition the outputs will be
latched to the last logic level present at the output to avoid signal crosstalk.
Applying a LOW INPUT to the CD/MUTE pin will force the GS1524A outputs to remain
active regardless of the length of input cable and the voltage applied to the MCLADJ pin.
See the DC electrical characteristics table for voltage levels.
OUTPUT (CD)
When used as an OUTPUT, the CD/MUTE pin will indicate the presence of a valid input
signal. When CD/MUTE is LOW, a valid input signal has been detected at the input of the
device. When CD/MUTE is HIGH, the input signal is invalid. This pin will indicate loss of
carrier for data rates greater than 19Mb/s.
NOTE: The CD/MUTE pin is not functional in BYPASS mode.
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5. Application Information
5.1 PCB Layout
Special attention must be paid to component layout when designing serial digital
interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance
transmission lines are required for PCB traces longer than approximately 1cm. Note the
following PCB artwork features used to optimize performance:
• PCB trace width for HD rate signals is closely matched to SMT component width to
minimize reflections due to change in trace impedance.
• The PCB ground plane is removed under the GS1524A input components to
minimize parasitic capacitance.
• The PCB ground plane is removed under the GS1524A output components to
minimize parasitic capacitance.
• High speed traces are curved to minimize impedance changes.
5.2 Typical Application Circuits
Figure 5-1: GS1524A Typical Application Circuit
6.4n
10n
BYPASS
MCLADJ
75
SDO
BNC
VCC
CLI
1u
10n
75
4u7
4u7
GS1524A
4
5
16
6
2
12
13
3
11
14
15
8
+
+
+
9
10
1
7
SDI
SDI
CD/MUTE
VEE
VCC
SDO
SDO
VEE
VEE
VEE
VCC
AGC- BYPASS
MCLADJ
CLI
AGC+
1u
SDO
CD/MUTE
37.4
1u
VCC
NOTE: All resistors in Ohms, capacitors in Farads,
and inductors in Henrys, unless otherwise noted.
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Data Sheet
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6. Package & Ordering Information
6.1 Package Dimensions
6.2 Packaging Data
Symbol
A
A1
A2
b
c
D
E
e
H
L1
L
Y
MIN. MIN.MAX. MAX.NOM. NOM.
MILLIMETER INCH
* CONTROLLING DIMENSION: MM
1.35
0.10
1.30
0.33
0.19
9.80
3.80
5.80
0.40
0°
1.63
0.15
1.40
0.41
9.91
3.90
1.27
6.00
0.64
1.07
1.75
0.25
1.50
0.51
0.25
10.01
4.00
0.053
0.004
0.051
0.013
0.064
0.006
0.055
0.016
0.390
0.154
0.50
0.069
0.010
0.059
0.020
0.010
0.394
0.157
0°8° 8°
6.20
1.27
0.10 0.004
0.042
0.0250.016
0.228 0.236 0.244
0.050
0.150
0.386
0.007
D
e
Seating Plane
A2
A
A1
Y
See Detail F
L1
c
Detail F
L
GAUGE PLANE
0.010"
H
E
8
1
16 9
b
Parameter Value
Package Type SOIC 16L
Package Drawing Reference JEDEC MS012
Moisture Sensitivity Level 2
Junction to Air Thermal Resistance, θj-a (at zero airflow) 94.1°C/W
Pb-free and RoHS Compliant Yes
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Data Sheet
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6.3 Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both
standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed
using the maximum Pb-free reflow profile shown in Figure 6-1. The recommended
standard Pb reflow profile is shown in Figure 6-2.
Figure 6-1: Maximum Pb-free Solder Reflow Profile (Preferred)
Figure 6-2: Standard Pb Solder Reflow Profile
25°C
150°C
200°C
217°C
260°C
250°C
Time
Temperature
8 min. max
60-180 sec. max
60-150 sec.
20-40 sec.
3°C/sec max
6°C/sec max
25°C
100°C
150°C
183°C
230°C
220°C
Time
Temperature
6 min. max
120 sec. max
60-150 sec.
10-20 sec.
3°C/sec max
6°C/sec max
OTTAWA
232 Herzberg Road, Suite 101
Kanata, Ontario K2K 2A1
Canada
Phone: +1 (613) 270-0458
Fax: +1 (613) 270-0429
CALGARY
3553 - 31st St. N.W., Suite 210
Calgary, Alberta T2L 2K7
Canada
Phone: +1 (403) 284-2672
UNITED KINGDOM
North Building, Walden Court
Parsonage Lane,
Bishop’s Stortford Hertfordshire, CM23 5DB
United Kingdom
Phone: +44 1279 714170
Fax: +44 1279 714171
INDIA
#208(A), Nirmala Plaza,
Airport Road, Forest Park Square
Bhubaneswar 751009
India
Phone: +91 (674) 653-4815
Fax: +91 (674) 259-5733
SNOWBUSH IP - A DIVISION OF GENNUM
439 University Ave. Suite 1700
Toronto, Ontario M5G 1Y8
Canada
Phone: +1 (416) 925-5643
Fax: +1 (416) 925-0581
E-mail: sales@snowbush.com
Web Site: http://www.snowbush.com
MEXICO
288-A Paseo de Maravillas
Jesus Ma., Aguascalientes
Mexico 20900
Phone: +1 (416) 848-0328
JAPAN KK
Shinjuku Green Tower Building 27F
6-14-1, Nishi Shinjuku
Shinjuku-ku, Tokyo, 160-0023
Japan
Phone: +81 (03) 3349-5501
Fax: +81 (03) 3349-5505
E-mail: gennum-japan@gennum.com
Web Site: http://www.gennum.co.jp
TAIWA N
6F-4, No.51, Sec.2, Keelung Rd.
Sinyi District, Taipei City 11502
Taiwan R.O.C.
Phone: (886) 2-8732-8879
Fax: (886) 2-8732-8870
E-mail: gennum-taiwan@gennum.com
GERMANY
Hainbuchenstraße 2
80935 Muenchen (Munich), Germany
Phone: +49-89-35831696
Fax: +49-89-35804653
E-mail: gennum-germany@gennum.com
NORTH AMERICA WESTERN REGION
Bayshore Plaza
2107 N 1st Street, Suite #300
San Jose, CA 95131
United States
Phone: +1 (408) 392-9454
Fax: +1 (408) 392-9427
E-mail: naw_sales@gennum.com
NORTH AMERICA EASTERN REGION
4281 Harvester Road
Burlington, Ontario L7L 5M4
Canada
Phone: +1 (905) 632-2996
Fax: +1 (905) 632-2055
E-mail: nae_sales@gennum.com
KOREA
8F Jinnex Lakeview Bldg.
65-2, Bangidong, Songpagu
Seoul, Korea 138-828
Phone: +82-2-414-2991
Fax: +82-2-414-2998
E-mail: gennum-korea@gennum.com
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make changes to
the product at any time without notice to improve reliability, function or
design, in order to provide the best product possible.
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Data Sheet
28852 - 5 June 2009
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16
Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of
the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent
infringement.
All other trademarks mentioned are the properties of their respective owners.
GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.
© Copyright 2004 Gennum Corporation. All rights reserved.
www.gennum.com
GENNUM CORPORATE HEADQUARTERS
4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada
Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055
E-mail: corporate@gennum.com www.gennum.com
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
STATIC-FREE WORKSTATION
6.4 Ordering Information
Part Number Package Temperature Range
GS1524A GS1524ACKDE3 Pb-free 16-Pin SOIC0°C to 70°C
GS1524A GS1524ACTDE3 Pb-free 16-Pin SOIC Tape 0°C to 70°C