LM2524D/LM3524D Regulating Pulse Width Modulator
Literature Number: SNVS766D
May 2, 2008
Regulating Pulse Width Modulator
General Description
The LM3524D family is an improved version of the industry
standard LM3524. It has improved specifications and addi-
tional features yet is pin for pin compatible with existing 3524
families. New features reduce the need for additional external
circuitry often required in the original version.
The LM3524D has a ±1% precision 5V reference. The current
carrying capability of the output drive transistors has been
raised to 200 mA while reducing VCEsat and increasing VCE
breakdown to 60V. The common mode voltage range of the
error-amp has been raised to 5.5V to eliminate the need for
a resistive divider from the 5V reference.
In the LM3524D the circuit bias line has been isolated from
the shut-down pin. This prevents the oscillator pulse ampli-
tude and frequency from being disturbed by shut-down. Also
at high frequencies (≃300 kHz) the max. duty cycle per output
has been improved to 44% compared to 35% max. duty cycle
in other 3524s.
In addition, the LM3524D can now be synchronized external-
ly, through pin 3. Also a latch has been added to insure one
pulse per period even in noisy environments. The LM3524D
includes double pulse suppression logic that insures when a
shut-down condition is removed the state of the T-flip-flop will
change only after the first clock pulse has arrived. This feature
prevents the same output from being pulsed twice in a row,
thus reducing the possibility of core saturation in push-pull
Fully interchangeable with standard LM3524 family
±1% precision 5V reference with thermal shut-down
Output current to 200 mA DC
60V output capability
Wide common mode input range for error-amp
One pulse per period (noise suppression)
Improved max. duty cycle at high frequencies
Double pulse suppression
Synchronize through pin 3
Connection Diagram
Top View
Order Number LM2524DN or LM3524DN
See NS Package Number N16E
Order Number LM3524DM
See NS Package Number M16A
© 2008 National Semiconductor Corporation 8650 www.national.com
LM2524D/LM3524D Regulating Pulse Width Modulator
Block Diagram
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Absolute Maximum Ratings (Note 5)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage 40V
Collector Supply Voltage
(LM2524D) 55V
(LM3524D) 40V
Output Current DC (each) 200 mA
Oscillator Charging Current (Pin 7) 5 mA
Internal Power Dissipation 1W
Operating Junction Temperature
Range (Note 2)
LM2524D −40°C to +125°C
LM3524D 0°C to +125°C
Maximum Junction Temperature 150°
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 4 sec.)
M, N Pkg. 260°C
Electrical Characteristics
(Note 1)
LM2524D LM3524D
Symbol Parameter Conditions Tested Design Tested Design Units
Typ Limit Limit Typ Limit Limit
(Note 3) (Note 4) (Note 3) (Note 4)
VREF Output Voltage 54.85 4.80 54.75 VMin
5.15 5.20 5.25 VMax
VRLine Line Regulation VIN = 8V to 40V 10 15 30 10 25 50 mVMax
VRLoad Load Regulation IL = 0 mA to 20 mA 10 15 25 10 25 50 mVMax
Ripple Rejection f = 120 Hz 66 66 dB
IOS Short Circuit VREF = 0 25 25 mA Min
Current 50 50
180 200 mA Max
NOOutput Noise 10 Hz f 10 kHz 40 100 40 100 μVrms Max
Long Term TA = 125°C 20 20 mV/kHr
fOSC Max. Freq. RT = 1k, CT = 0.001 μF550 500 350 kHzMin
(Note 7)
fOSC Initial RT = 5.6k, CT = 0.01 μF 17.5 17.5 kHzMin
Accuracy (Note 7) 20 20
22.5 22.5 kHzMax
RT = 2.7k, CT = 0.01 μF 34 30 kHzMin
(Note 7) 38 38
42 46 kHzMax
ΔfOSC Freq. Change VIN = 8 to 40V 0.5 1 0.5 1.0 %Max
with VIN
ΔfOSC Freq. Change TA = −55°C to +125°C
with Temp. at 20 kHz RT = 5.6k, 5 5 %
CT = 0.01 μF
VOSC Output Amplitude RT = 5.6k, CT = 0.01 μF3 2.4 3 2.4 VMin
(Pin 3) (Note 8)
tPW Output Pulse RT = 5.6k, CT = 0.01 μF0.5 1.5 0.5 1.5 μsMax
Width (Pin 3)
Sawtooth Peak RT = 5.6k, CT = 0.01 μF3.4 3.6 3.8 3.8 VMax
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LM2524D LM3524D
Symbol Parameter Conditions Tested Design Tested Design Units
Typ Limit Limit Typ Limit Limit
(Note 3) (Note 4) (Note 3) (Note 4)
Sawtooth Valley RT = 5.6k, CT = 0.01 μF1.1 0.8 0.6 0.6 VMin
VIO Input Offset VCM = 2.5V 2 8 10 2 10 mVMax
IIB Input Bias VCM = 2.5V 1 8 10 1 10 μAMax
IIO Input Offset VCM = 2.5V 0.5 1.0 10.5 1 μAMax
ICOSI Compensation VIN(I) − VIN(NI) = 150 mV 65 65 μAMin
Current (Sink) 95 95
125 125 μAMax
ICOSO Compensation VIN(NI) − VIN(I) = 150 mV −125 −125 μAMin
Current (Source) −95 −95
−65 −65 μAMax
AVOL Open Loop Gain RL = , VCM = 2.5 V 80 74 60 80 70 60 dBMin
VCMR Common Mode 1.5 1.4 1.5 VMin
Input Voltage
5.5 5.4 5.5 VMax
CMRR Common Mode 90 80 90 80 dBMin
Rejection Ratio
GBW Unity Gain AVOL = 0 dB, VCM = 2.5V 3 2 MHz
VOOutput Voltage RL = 0.5 0.5 VMin
Swing 5.5 5.5 VMax
PSRR Power Supply VIN = 8 to 40V 80 70 80 65 dbMin
Rejection Ratio
Minimum Duty Pin 9 = 0.8V, 0 0 0 0 %Max
Cycle [RT = 5.6k, CT = 0.01 μF]
Maximum Duty Pin 9 = 3.9V, 49 45 49 45 %Min
Cycle [RT = 5.6k, CT = 0.01 μF]
Maximum Duty Pin 9 = 3.9V, 44 35 44 35 %Min
Cycle [RT = 1k, CT = 0.001 μF]
VCOMPZ Input Threshold Zero Duty Cycle 1 1 V
(Pin 9)
VCOMPM Input Threshold Maximum Duty Cycle 3.5 3.5 V
(Pin 9)
IIB Input Bias −1 −1 μA
VSEN Sense Voltage V(Pin 2) − V(Pin 1) 180 180 mVMin
150 mV 200 200
220 220 mVMax
TC-Vsense Sense Voltage T.C. 0.2 0.2 mV/°C
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LM2524D LM3524D
Symbol Parameter Conditions Tested Design Tested Design Units
Typ Limit Limit Typ Limit Limit
(Note 3) (Note 4) (Note 3) (Note 4)
Common Mode −0.7 −0.7 VMin
Voltage Range V5 − V4 = 300 mV 1 1 VMax
VSD High Input V(Pin 2) − V(Pin 1) 10.5 10.5 VMin
Voltage 150 mV 1.5 1.5 VMax
ISD High Input I(pin 10) 1 1 mA
VCES Collector Emitter IC 100 μA 55 40 VMin
Voltage Breakdown
ICES Collector Leakage VCE = 60V
Current VCE = 55V 0.1 50 μAMax
VCE = 40V 0.1 50
VCESAT Saturation IE = 20 mA 0.2 0.5 0.2 0.7 VMax
Voltage IE = 200 mA 1.5 2.2 1.5 2.5
VEO Emitter Output IE = 50 mA 18 17 18 17 VMin
tRRise Time VIN = 20V,
IE = −250 μA200 200 ns
RC = 2k
tFFall Time RC = 2k 100 100 ns
VIN Input Voltage After Turn-on 8 8 VMin
Range 40 40 VMax
T Thermal Shutdown (Note 2) 160 160 °C
IIN Stand By Current VIN = 40V (Note 6) 5 10 5 10 mA
Note 1: Unless otherwise stated, these specifications apply for TA = TJ = 25°C. Boldface numbers apply over the rated temperature range: LM2524D is −40° to
85°C and LM3524D is 0°C to 70°C. VIN = 20V and fOSC = 20 kHz.
Note 2: For operation at elevated temperatures, devices in the N package must be derated based on a thermal resistance of 86°C/W, junction to ambient. Devices
in the M package must be derated at 125°C/W, junction to ambient.
Note 3: Tested limits are guaranteed and 100% tested in production.
Note 4: Design limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage range. These limits are not used to
calculate outgoing quality level.
Note 5: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its rated operating conditions.
Note 6: Pins 1, 4, 7, 8, 11, and 14 are grounded; Pin 2 = 2V. All other inputs and outputs open.
Note 7: The value of a Ct capacitor can vary with frequency. Careful selection of this capacitor must be made for high frequency operation. Polystyrene was used
in this test. NPO ceramic or polypropylene can also be used.
Note 8: OSC amplitude is measured open circuit. Available current is limited to 1 mA so care must be exercised to limit capacitive loading of fast pulses.
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Typical Performance Characteristics
Switching Transistor
Peak Output Current
vs Temperature
Maximum Average Power
Dissipation (N, M Packages)
Maximum & Minimum
Duty Cycle Threshold
Output Transistor
Saturation Voltage
Output Transistor Emitter
Reference Transistor
Peak Output Current
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Standby Current
vs Voltage
Standby Current
vs Temperature
Current Limit Sense Voltage
Test Circuit
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Functional Description
The LM3524D has an on-chip 5V, 50 mA, short circuit pro-
tected voltage regulator. This voltage regulator provides a
supply for all internal circuitry of the device and can be used
as an external reference.
For input voltages of less than 8V the 5V output should be
shorted to pin 15, VIN, which disables the 5V regulator. With
these pins shorted the input voltage must be limited to a max-
imum of 6V. If input voltages of 6V–8V are to be used, a pre-
regulator, as shown in Figure 1, must be added.
*Minimum CO of 10 μF required for stability.
The LM3524D provides a stable on-board oscillator. Its fre-
quency is set by an external resistor, RT and capacitor, CT. A
graph of RT, CT vs oscillator frequency is shown is Figure 2.
The oscillator's output provides the signals for triggering an
internal flip-flop, which directs the PWM information to the
outputs, and a blanking pulse to turn off both outputs during
transitions to ensure that cross conduction does not occur.
The width of the blanking pulse, or dead time, is controlled by
the value of CT, as shown in Figure 3. The recommended
values of RT are 1.8 kΩ to 100 kΩ, and for CT, 0.001 μF to 0.1
If two or more LM3524D's must be synchronized together, the
easiest method is to interconnect all pin 3 terminals, tie all pin
7's (together) to a single CT, and leave all pin 6's open except
one which is connected to a single RT. This method works well
unless the LM3524D's are more than 6≃ apart.
A second synchronization method is appropriate for any cir-
cuit layout. One LM3524D, designated as master, must have
its RTCT set for the correct period. The other slave LM3524D
(s) should each have an RTCT set for a 10% longer period. All
pin 3's must then be interconnected to allow the master to
properly reset the slave units.
The oscillator may be synchronized to an external clock
source by setting the internal free-running oscillator frequen-
cy 10% slower than the external clock and driving pin 3 with
a pulse train (approx. 3V) from the clock. Pulse width should
be greater than 50 ns to insure full synchronization.
The error amplifier is a differential input, transconductance
amplifier. Its gain, nominally 86 dB, is set by either feedback
or output loading. This output loading can be done with either
purely resistive or a combination of resistive and reactive
components. A graph of the amplifier's gain vs output load
resistance is shown in Figure 4.
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The output of the amplifier, or input to the pulse width modu-
lator, can be overridden easily as its output impedance is very
high (ZO ≃ 5 MΩ). For this reason a DC voltage can be applied
to pin 9 which will override the error amplifier and force a par-
ticular duty cycle to the outputs. An example of this could be
a non-regulating motor speed control where a variable volt-
age was applied to pin 9 to control motor speed. A graph of
the output duty cycle vs the voltage on pin 9 is shown in Figure
The duty cycle is calculated as the percentage ratio of each
output's ON-time to the oscillator period. Paralleling the out-
puts doubles the observed duty cycle.
The amplifier's inputs have a common-mode input range of
1.5V–5.5V. The on board regulator is useful for biasing the
inputs to within this range.
The function of the current limit amplifier is to override the
error amplifier's output and take control of the pulse width.
The output duty cycle drops to about 25% when a current limit
sense voltage of 200 mV is applied between the +CL and
−CLsense terminals. Increasing the sense voltage approxi-
mately 5% results in a 0% output duty cycle. Care should be
taken to ensure the −0.7V to +1.0V input common-mode
range is not exceeded.
In most applications, the current limit sense voltage is pro-
duced by a current through a sense resistor. The accuracy of
this measurement is limited by the accuracy of the sense re-
sistor, and by a small offset current, typically 100 μA, flowing
from +CL to −CL.
The outputs of the LM3524D are NPN transistors, capable of
a maximum current of 200 mA. These transistors are driven
180° out of phase and have non-committed open collectors
and emitters as shown in Figure 6.
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Typical Applications
FIGURE 7. Positive Regulator, Step-Up Basic Configuration (IIN(MAX) = 80 mA)
FIGURE 8. Positive Regulator, Step-Up Boosted Current Configuration
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FIGURE 9. Positive Regulator, Step-Down Basic Configuration (IIN(MAX) = 80 mA)
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FIGURE 10. Positive Regulator, Step-Down Boosted Current Configuration
FIGURE 11. Boosted Current Polarity Inverter
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The basic circuit of a step-down switching regulator circuit is
shown in Figure 12, along with a practical circuit design using
the LM3524D in Figure 15.
FIGURE 12. Basic Step-Down Switching Regulator
The circuit works as follows: Q1 is used as a switch, which
has ON and OFF times controlled by the pulse width modu-
lator. When Q1 is ON, power is drawn from VIN and supplied
to the load through L1; VA is at approximately VIN, D1 is re-
verse biased, and Co is charging. When Q1 turns OFF the
inductor L1 will force VA negative to keep the current flowing
in it, D1 will start conducting and the load current will flow
through D1 and L1. The voltage at VAis smoothed by the L1,
Co filter giving a clean DC output. The current flowing through
L1 is equal to the nominal DC load current plus some ΔIL
which is due to the changing voltage across it. A good rule of
thumb is to set
ILP-P ≃ 40% × Io.
FIGURE 13. Relation of Switch Timing to Inductor Current in Step-Down Regulator
Neglecting VSAT, VD, and settling ΔIL+ = ΔIL;
where T = Total Period
The above shows the relation between VIN, Vo and duty cycle.
as Q1 only conducts during tON.
The efficiency, η, of the circuit is:
ηMAX will be further decreased due to switching losses in Q1.
For this reason Q1 should be selected to have the maximum
possible fT, which implies very fast rise and fall times.
Since ΔIL+ = ΔIL = 0.4Io
Solving the above for L1
where: L1 is in Henrys
f is switching frequency in Hz
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Also, see LM1578 data sheet for graphical methods of induc-
tor selection.
Figure 13 shows L1's current with respect to Q1's tON and
tOFF times (VA is at the collector of Q1). This curent must flow
to the load and Co. Co's current will then be the difference
between IL, and Io.
Ico = IL − Io
From Figure 13 it can be seen that current will be flowing into
Co for the second half of tON through the first half of tOFF, or a
time, tON/2 + tOFF/2. The current flowing for this time is ΔIL/4.
The resulting ΔVc or ΔVo is described by:
For best regulation, the inductor's current cannot be allowed
to fall to zero. Some minimum load current Io, and thus in-
ductor current, is required as shown below:
FIGURE 14. Inductor Current Slope in Step-Down
A complete step-down switching regulator schematic, using
the LM3524D, is illustrated in Figure 15. Transistors Q1 and
Q2 have been added to boost the output to 1A. The 5V reg-
ulator of the LM3524D has been divided in half to bias the
error amplifier's non-inverting input to within its common-
mode range. Since each output transistor is on for half the
period, actually 45%, they have been paralleled to allow
longer possible duty cycle, up to 90%. This makes a lower
possible input voltage. The output voltage is set by:
where VNI is the voltage at the error amplifier's non-inverting
Resistor R3 sets the current limit to:
Figures 16, 17 and show a PC board layout and stuffing dia-
gram for the 5V, 1A regulator of Figure 15. The regulator's
performance is listed in Table 1.
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*Mounted to Staver Heatsink No. V5-1.
Q1 = BD344
Q2 = 2N5023
L1 = >40 turns No. 22 wire on Ferroxcube No. K300502 Torroid core.
FIGURE 15. 5V, 1 Amp Step-Down Switching Regulator
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Parameter Conditions Typical
Output Voltage VIN = 10V, Io = 1A 5V
Switching Frequency VIN = 10V, Io = 1A 20 kHz
Short Circuit VIN = 10V 1.3A
Current Limit
Load Regulation VIN = 10V 3 mV
Io = 0.2 − 1A
Line Regulation ΔVIN = 10 − 20V, 6 mV
Io = 1A
Efficiency VIN = 10V, Io = 1A 80%
Output Ripple VIN = 10V, Io = 1A 10 mVp-p
FIGURE 16. 5V, 1 Amp Switching Regulator, Foil Side
FIGURE 17. Stuffing Diagram, Component Side
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Figure 18 shows the basic circuit for a step-up switching reg-
ulator. In this circuit Q1 is used as a switch to alternately apply
VIN across inductor L1. During the time, tON, Q1 is ON and
energy is drawn from VIN and stored in L1; D1 is reverse bi-
ased and Io is supplied from the charge stored in Co. When
Q1 opens, tOFF, voltage V1 will rise positively to the point
where D1 turns ON. The output current is now supplied
through L1, D1 to the load and any charge lost from Co during
tON is replenished. Here also, as in the step-down regulator,
the current through L1 has a DC component plus some ΔIL.
ΔIL is again selected to be approximately 40% of IL. Figure
19 shows the inductor's current in relation to Q1's ON and
OFF times.
FIGURE 18. Basic Step-Up Switching Regulator
FIGURE 19. Relation of Switch Timing to Inductor Current in Step-Up Regulator
Since ΔIL+ = ΔIL−, VINtON = VotOFF − VINtOFF,
and neglecting VSAT and VD1
The above equation shows the relationship between VIN, Vo
and duty cycle.
In calculating input current IIN(DC), which equals the inductor's
DC current, assume first 100% efficiency:
for η = 100%, POUT = PIN
This equation shows that the input, or inductor, current is
larger than the output current by the factor (1 + tON/tOFF). Since
this factor is the same as the relation between Vo and VIN, IIN
(DC) can also be expressed as:
So far it is assumed η = 100%, where the actual efficiency or
ηMAX will be somewhat less due to the saturation voltage of
Q1 and forward on voltage of D1. The internal power loss due
to these voltages is the average IL current flowing, or IIN,
through either VSAT or VD1. For VSAT = VD1 = 1V this power
loss becomes IIN(DC) (1V). ηMAX is then:
This equation assumes only DC losses, however ηMAX is fur-
ther decreased because of the switching time of Q1 and D1.
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In calculating the output capacitor Co it can be seen that Co
supplies Io during tON. The voltage change on Co during this
time will be some ΔVc = ΔVo or the output ripple of the regu-
lator. Calculation of Co is:
where: Co is in farads, f is the switching frequency,
 ΔVo is the p-p output ripple
Calculation of inductor L1 is as follows:
VIN is applied across L1
where: L1 is in henrys, f is the switching frequency in Hz
To apply the above theory, a complete step-up switching reg-
ulator is shown in Figure 20. Since VIN is 5V, VREF is tied to
VIN. The input voltage is divided by 2 to bias the error
amplifier's inverting input. The output voltage is:
The network D1, C1 forms a slow start circuit.
This holds the output of the error amplifier initially low thus
reducing the duty-cycle to a minimum. Without the slow start
circuit the inductor may saturate at turn-on because it has to
supply high peak currents to charge the output capacitor from
0V. It should also be noted that this circuit has no supply re-
jection. By adding a reference voltage at the non-inverting
input to the error amplifier, see Figure 21, the input voltage
variations are rejected.
The LM3524D can also be used in inductorless switching
regulators. Figure 22 shows a polarity inverter which if con-
nected to Figure 20 provides a −15V unregulated output.
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L1 = > 25 turns No. 24 wire on Ferroxcube No. K300502 Toroid core.
FIGURE 20. 15V, 0.5A Step-Up Switching Regulator
FIGURE 21. Replacing R3/R4 Divider in Figure 20 with Reference Circuit Improves Line Regulation
FIGURE 22. Polarity Inverter Provides Auxiliary −15V Unregulated Output from Circuit of Figure 20
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