November 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C33512PFS18A
3.3V 512K × 18 pipeline burst synchronous SRAM
11/30/04; v.2.2 Alliance Semiconductor 1 of 20
Features
• Organization: 524,288 words × 18 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
•Fast OE
access time: 3.5/4.0 ns
• Fully synchronous register-to-register operation
• Single-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Selection guide
–166 –133 Units
Minimum cycle time 6 7.5 ns
Maximum clock frequency 166 133 MHz
Maximum clock access time 3.5 4 ns
Maximum operating current 475 425 mA
Maximum standby current 130 100 mA
Maximum CMOS standby current (DC) 30 30 mA
Logic block diagram
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
19
17
19
A[18:0]
19
Address
DQ
CS
CLK
register
512K × 18
Memory
array
18
18
DQb
CLK
DQ
Byte Write
registers
DQa
CLK
DQ
Byte Write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
2
CE0
CE1
CE2
BWb
BWa
OE
ZZ
OE
CLK CLK
BWE
GWE
18
DQ[a,b]
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8 Mb Synchronous SRAM products list1,2
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT : Flow-through Burst Synchronous SRAM
NTD1-PL : Pipelined Burst Synchronous SRAM with NTDTM
NTD-FT : Flow-through Burst Synchronous SRAM with NTDTM
Org Part Number Mode Speed
512KX18 AS7C33512PFS18A PL-SCD 166/133 MHz
256KX32
AS7C33256PFS32A PL-SCD 166/133 MHz
256KX36 AS7C33256PFS36A PL-SCD 166/133 MHz
512KX18 AS7C33512PFD18A PL-DCD 166/133 MHz
256KX32
AS7C33
256
PFD32A PL-DCD 166/133 MHz
256KX36 AS7C33
256
PFD36A PL-DCD 166/133 MHz
512KX18 AS7C33512FT18A FT 7.5/8.5/10 ns
256KX32
AS7C33
256
FT32A FT 7.5/8.5/10 ns
256KX36 AS7C33
256
FT36A FT 7.5/8.5/10 ns
512KX18 AS7C33512NTD18A NTD-PL 166/133 MHz
256KX32
AS7C33
256
NTD32A NTD-PL 166/133 MHz
256KX36 AS7C33
256
NTD36A NTD-PL 166/133 MHz
512KX18 AS7C33512NTF18A NTD-FT 7.5/8.5/10 ns
256KX32
AS7C33
256
NTF32A NTD-FT 7.5/8.5/10 ns
256KX36 AS7C33
256
NTF36A NTD-FT 7.5/8.5/10 ns
1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the prop-
erty of their respective owners.
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Pin arrangement
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb0
DQb1
V
SSQ
V
DDQ
DQb2
DQb3
NC
V
DD
NC
V
SS
DQb4
DQb5
V
DDQ
V
SSQ
DQb6
DQb7
DQpb
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQpa
DQa7
DQa6
V
SSQ
V
DDQ
DQa5
DQa4
VSS
ZZ
DQa3
DQa2
V
DDQ
V
SSQ
DQa1
DQa0
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
V
DD
TQFP 14 × 20mm
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Functional description
The AS7C33512PFS18A is a high performance CMOS 8-Mbit Synchronous Static Random Access Memory (SRAM) device organized as
524,288 words × 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP,
and PowerPC™1-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 6/7.5 ns with clock access times (tCD) of 3.5/4.0 ns enable 166 and 133 MHz bus frequencies. Three chip enable inputs
permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor
address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and
driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on
all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address
strobes are HIGH. Burst mode is selectable with the
LBO
input. With
LBO
unconnected or driven HIGH, burst operations use a Pentium®
count sequence. With
LBO
driven LOW the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW. This device operates in single-cycle deselect feature during
read cycles.
Read or write cycles may also be initiated with
ADSC
instead of
ADSP
. The differences between cycles initiated with
ADSC
and
ADSP
are
as follows:
•
ADSP
must be sampled HIGH when
ADSC
is sampled LOW to initiate a cycle with
ADSC
.
•
WE
signals are sampled on the clock edge that samples
ADSC
LOW (and
ADSP
HIGH).
• Master chip select
CE0
blocks
ADSP
, but not
ADSC
.
The AS7C33512PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are
available in a 100-pin 14×20 mm TQFP packaging.
.
*Guaranteed not tested
1. PowerPC™ is a trademark International Business Machines Corporation
Capacitance
Parameter Symbol Test conditions Max Unit
Input capacitance CIN*VIN = 0V 5 pF
I/O capacitance CI/O*VIN = VOUT = 0V 7 pF
TQFP thermal resistance
Description Conditions Symbol Typical Units
Thermal resistance
(junction to ambient)1
1 This parameter is sampled.
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
1–layer θJA 40 °C/W
4–layer θJA 22 °C/W
Thermal resistance
(junction to top of case)1θJC 8°C/W
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Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
Signal descriptions
Signal I/O Properties Description
CLK I CLOCK Clock. All inputs except OE, ZZ,
LBO
are synchronous to this clock.
A,A0,A1 I SYNC Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE is active.
CE0 ISYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
CE1, CE2 ISYNC
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
ADSP I SYNC Address strobe (processor). Asserted LOW to load a new address or to enter standby mode.
ADSC I SYNC Address strobe (controller). Asserted LOW to load a new address or to enter standby mode.
ADV I SYNC Burst advance. Asserted LOW to continue burst read/write.
GWE ISYNC
Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b]
control write enable.
BWE I SYNC Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs.
BW[a,b] ISYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
OE IASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
LBO ISTATIC
Selects Burst mode. When tied to VDD or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order. This signal is internally pulled
High.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC - - No connect
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Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b;
BWE
,
BWn
= internal write signal.
Asynchronous Truth Table
Burst sequence table
Function GWE BWE BWa BWb
Write All Bytes LXXX
HLLL
Write Byte a H L L H
Write Byte b H L H L
Read HHXX
HLHH
Operation ZZ OE I/O Status
Snooze mode H X High-Z
Read L L Dout
LHHigh-Z
Write L X Din, High-Z
Deselected L X High-Z
Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)
A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0
Starting Address 0 0 0 1 1 0 1 1 Starting Address 0 0 0 1 1 0 1 1
First Increment 0 1 0 0 1 1 1 0 First Increment 0 1 1 0 1 1 0 0
Second Increment 1 0 1 1 0 0 0 1 Second Increment 1 0 1 1 0 0 0 1
Third Increment 1 1 1 0 0 1 0 0 Third Increment 1 1 1 0 0 1 1 0
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Synchronous truth table[4]
CE01
1 X = don’t care, L = low, H = high
CE1 CE2 ADSP ADSC ADV
WRITE
[2]
2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE,
GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
OE Address accessed CLK Operation DQ
HXXXLX X X NA L to H DeselectHi−Z
L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Q
L H L L X X X H External L to H Begin read Hi−Z
L H L H L X H L External L to H Begin read Q
L H L H L X H H External L to H Begin read Hi−Z
XXXHHL H L Next L to HContinue readQ
XXXHHL H H Next L to HContinue readHi−Z
XXXHHH H L Current L to HSuspend readQ
XXXHHH H H Current L to HSuspend readHi−Z
HXXXHL H L Next L to HContinue readQ
HXXXHL H H Next L to HContinue readHi−Z
HXXXHH H L Current L to HSuspend readQ
HXXXHH H H Current L to HSuspend readHi−Z
L H L H L X L X External L to H Begin write D3
3 For write operation following a READ,
OE
must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
XXXHHL L X Next L to HContinue writeD
HXXXHL L X Next L to HContinue writeD
XXXHHH L X Current L to HSuspend writeD
HXXXHH L X Current L to HSuspend writeD
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Recommended operating conditions at 3.3V I/O
Recommended operating conditions at 2.5V I/O
Absolute maximum ratings1
1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
Parameter Symbol Min Max Unit
Power supply voltage relative to GND VDD, VDDQ –0.5 +4.6 V
Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V
Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V
Power dissipation PD–1.8W
DC output current IOUT –50mA
Storage temperature (plastic) Tstg –65 +150 °C
Temperature under bias Tbias –65 +135 °C
Parameter Symbol Min Nominal Max Unit
Supply voltage for inputs VDD 3.135 3.3 3.465 V
Supply voltage for I/O VDDQ 3.135 3.3 3.465 V
Ground supply Vss 0 0 0 V
Parameter Symbol Min Nominal Max Unit
Supply voltage for inputs VDD 3.135 3.3 3.465 V
Supply voltage for I/O VDDQ 2.375 2.5 2.625 V
Ground supply Vss 0 0 0 V
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DC electrical characteristics for 3.3V I/O operation
DC electrical characteristics for 2.5V I/O operation
*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC
**VIL min = -1.5 for pulse width less than 0.2 X tCYC
IDD operating conditions and maximum limits
Parameter Sym Conditions Min Max Unit
Input leakage current1
1 LBO and ZZ pins and the have an internal pull-up or pull-down, and input leakage = ±10 µA.
|ILI|V
DD = Max, 0V < VIN < VDD -2 2 µA
Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA
Input high (logic 1) voltage VIH
Address and control pins 2*VDD+0.3 V
I/O pins 2*VDDQ+0.3
Input low (logic 0) voltage VIL
Address and control pins -0.3** 0.8 V
I/O pins -0.5** 0.8
Output high voltage VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – V
Output low voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 V
Parameter Sym Conditions Min Max Unit
Input leakage current |ILI|V
DD = Max, 0V < VIN < VDD -2 2 µA
Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA
Input high (logic 1) voltage VIH
Address and control pins 1.7*VDD+0.3 V
I/O pins 1.7*VDDQ+0.3 V
Input low (logic 0) voltage VIL
Address and control pins -0.3** 0.7 V
I/O pins -0.3** 0.7 V
Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V
Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V
Parameter Sym Conditions -166 -133 Unit
Operating power supply
current1
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
ICC
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax,
IOUT = 0 mA, ZZ < VIL
475 425 mA
Standby power supply
current
ISB
All VIN ≤ 0.2V or >
V
DD
– 0.2V,
Deselected,
f = fMax, ZZ < VIL
130 100
mA
ISB1 Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V 30 30
ISB2
Deselected, f = f
Max
, ZZ
≥
V
DD
– 0.2V,
all VIN ≤ VIL or ≥ VIH 30 30
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Timing characteristics for 3.3 V I/O operation
Parameter Symbol
–166 –133
Unit Notes1
1 See “Notes” on page 17
Min Max Min Max
Clock frequency fMax –166–133MHz
Cycle time tCYC 6 – 7.5 – ns
Clock access time tCD -3.5-4.0ns
Output enable low to data valid tOE –3.5–4.0ns
Clock high to output low Z tLZC 0 – 0 – ns 2,3,4
Data output invalid from clock high tOH 1.5 – 1.5 – ns 2
Output enable low to output low Z tLZOE 0 – 0 – ns 2,3,4
Output enable high to output high Z tHZOE –3.5–4.0ns 2,3,4
Clock high to output high Z tHZC –3.5–4.0ns 2,3,4
Output enable high to invalid output tOHOE 0–0–ns
Clock high pulse width tCH 2.4 – 2.5 – ns 5
Clock low pulse width tCL 2.3 – 2.5 – ns 5
Address setup to clock high tAS 1.5 – 1.5 – ns 6
Data setup to clock high tDS 1.5 – 1.5 – ns 6
Write setup to clock high tWS 1.5 – 1.5 – ns 6,7
Chip select setup to clock high tCSS 1.5 – 1.5 – ns 6,8
Address hold from clock high tAH 0.5 – 0.5 – ns 6
Data hold from clock high tDH 0.5 – 0.5 – ns 6
Write hold from clock high tWH 0.5 – 0.5 – ns 6,7
Chip select hold from clock high tCSH 0.5 – 0.5 – ns 6,8
ADV setup to clock high tADVS 1.5 – 1.5 – ns 6
ADSP setup to clock high tADSPS 1.5 – 1.5 – ns 6
ADSC setup to clock high tADSCS 1.5 – 1.5 – ns 6
ADV hold from clock high tADVH 0.5 – 0.5 – ns 6
ADSP hold from clock high tADSPH 0.5 – 0.5 – ns 6
ADSC hold from clock high tADSCH 0.5 – 0.5 – ns 6
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Snooze Mode Electrical Characteristics
Timing characteristics for 2.5V I/O operation
Parameter Symbol
–166 –133
Unit Notes1
Min Max Min Max
Clock frequency fMax – 166 – 133 MHz
Cycle time tCYC 6 – 7.5 – ns
Clock access time
tCD -4.0-4.5ns
Output enable LOW to data valid tOE –3.5–4.0ns
Clock HIGH to output Low Z tLZC 0 – 0 – ns 2,3,4
Data output invalid from clock HIGH tOH 1.5–1.5– ns 2
Output enable LOW to output Low Z tLZOE 0 – 0 – ns 2,3,4
Output enable HIGH to output High Z tHZOE – 3.5 – 4.0 ns 2,3,4
Clock HIGH to output High Z tHZC – 3.5 – 4.0 ns 2,3,4
Output enable HIGH to invalid output tOHOE 0–0–ns
Clock HIGH pulse width tCH 2.4–2.5– ns 5
Clock LOW pulse width tCL 2.3–2.5– ns 5
Address setup to clock HIGH tAS 1.7–1.7– ns 6
Data setup to clock HIGH tDS 1.7–1.7– ns 6
Write setup to clock HIGH tWS 1.7 – 1.7 – ns 6,7
Chip select setup to clock HIGH tCSS 1.7 – 1.7 – ns 6,8
Address hold from clock HIGH tAH 0.7–0.7– ns 6
Data hold from clock HIGH tDH 0.7–0.7– ns 6
Write hold from clock HIGH tWH 0.7 – 0.7 – ns 6,7
Chip select hold from clock HIGH tCSH 0.7 – 0.7 – ns 6,8
ADV setup to clock HIGH tADVS 1.7–1.7– ns 6
ADSP setup to clock HIGH tADSPS 1.7–1.7– ns 6
ADSC setup to clock HIGH tADSCS 1.7–1.7– ns 6
ADV hold from clock HIGH tADVH 0.7–0.7– ns 6
ADSP hold from clock HIGH tADSPH 0.7–0.7– ns 6
ADSC hold from clock HIGH tADSCH 0.7–0.7– ns 6
1 See “Notes on page 17.
Description Conditions Symbol Min Max Units
Current during Snooze Mode ZZ > VIH ISB2 30 mA
ZZ active to input ignored tPDS 2cycle
ZZ inactive to input sampled tPUS 2cycle
ZZ active to SNOOZE current tZZI 2cycle
ZZ inactive to exit SNOOZE current tRZZI 0
.
.
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Key to switching waveforms
Timing waveform of read cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
don’t careFalling inputRising input Undefined
CE1
t
CYC
t
CH
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
ADVS
t
OH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
Dout
t
CSS
t
HZC
t
CD
t
WH
t
ADVH
t
HZOE
t
ADSCS
t
ADSCH
LOAD NEW ADDRESS
ADV inserts wait states
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A2)
Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)
Q(A1)
A2A1 A3
t
OE
t
LZOE
t
CSH
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Burst
Read
Q(A 2Ý01
)
Read
Q(A3) DSEL
Burst
Read
Q(A 2Ý10
)
Suspend
Read
Q(A 2Ý10
)
Burst
Read
Q(A 2Ý11
)
Burst
Read
Q(A 3Ý01
)
Burst
Read
Q(A 3Ý10
)
Burst
Read
Q(A 3Ý11
)
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Timing waveform of write cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
ADSCS
t
ADSCH
t
AS
t
AH
t
WS
t
WH
t
CSS
t
ADVS
t
DS
t
DH
CLK
ADSP
ADSC
Address
BWE
CE0, CE2
ADV
OE
Din
t
CSH
t
ADVH
D(A2Ý01)
D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)
D(A1) D(A2Ý11)
ADV SUSPENDS BURST
ADSC LOADS NEW ADDRESS
A1 A2 A3
t
CH
CE1
BW[a:b]
Read
Q(A1) Sus-
pend
Write
D(A1)
Read
Q(A2)
Suspend
Write
D(A 2
)
ADV
Burst
Write
D(A 2Ý01
)
Suspend
Write
D(A 2Ý01
)
ADV
Burst
Write
D(A 2Ý10
)
Write
D(A 3
)
Burst
Write
D(A 3Ý01
)
ADV
Burst
Write
D(A 2Ý11
)
ADV
Burst
Write
D(A 3Ý10
)
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Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
t
CH
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
DS
t
DH
t
OH
CLK
ADSP
Address
GWE
CE0, CE2
ADV
OE
Din
Dout
t
CD
t
ADVH
t
LZOE
t
OE
t
LZC
Q(A1)
Q(A3Ý01)
D(A2)
Q(A3)
Q(A3Ý10) Q(A3Ý11)
A1 A2 A3
CE1
t
HZOE
DSEL Suspend
Read
Q(A1)
Read
Q(A1)
Suspend
Write
D(A 2
)
ADV
Burst
Read
Q(A 3Ý01
)
ADV
Burst
Read
Q(A 3Ý10
)
ADV
Burst
Read
Q(A 3Ý11
)
Read
Q(A2)
Read
Q(A3)
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
t
CYC
t
CH
t
CL
t
ADSCH
CLK
ADSC
ADDRESS A2
A1
t
ADSCS
A3 A4 A6
A5 A7 A8 A9
t
AH
t
AS
GWE
t
WH
t
WS
t
CSH
CE0,CE2
t
CSS
ADV
t
LZOE
t
OE
t
HZOE
Q(A1) Q(A2) Q(A3) Q(A4) Q(A8) Q(A9)
t
LZOE
t
OH
D(A6) D(A7)
D(A5)
t
DS
t
DH
OE
Dout
Din
READ
Q(A1)
READ
Q(A2)
READ
Q(A3)
READ
Q(A4)
WRITE
D(A5)
WRITE
D(A6)
WRITE
D(A7)
READ
Q(A8)
READ
Q(A9)
CE1
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Timing waveform of power down cycle
t
CYC
t
CH
t
CL
t
ADSPS
CLK
ADSP
ADDRESS A1
t
ADSPS
A2
GWE
t
WH
t
WS
t
CSH
CE0,CE2
t
CSS
ADV
t
LZOE
t
OE
t
HZOE
Q(A1)
D(A2(
Ý
01))
D(A2)
OE
Dout
Din
ADSC
t
HZC
t
PDS
ZZ Setup Cycle
t
PUS
ZZ Recovery Cycle Normal Operation Mode
CE1
ZZ
READ
Q(A1)
SUSPEND
READ
Q(A1)
CON-
TINUE
WRITE
D(A2 Ý01)
SUSPEND
WRITE
D(A2)
READ
Q(A2)
Sleep
I
SB2
State
t
ZZI
t
RZZI
I
supply
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AC test conditions
Z
0
= 50
Ω
D
OUT
50
Ω
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
N
otes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage.
5) tCH measured HIGH above VIH and tCL measured as LOW below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs mus
t
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to
GWE
,
BWE
,
BW[a,b]
.
8) Chip select refers to
CE0
,
CE1
,
CE2
.
353
Ω / 1538Ω
5 pF*
319
Ω / 1667Ω
D
OUT
GND
Figure C: Output load (B)
*including scope
and jig capacitanc
e
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
®
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Package Dimensions
100-pin quad flat pack (TQFP)
A1 A2
L1
L
c
He E
Hd
D
b
e
α
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b0.22 0.38
c0.09 0.20
D13.90 14.10
E19.90 20.10
e0.65 nominal
Hd 15.90 16.10
He 21.90 22.10
L0.45 0.75
L1 1.00 nominal
α0° 7°
Dimensions in millimeters
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Note: Add suffix ‘N’ with the above part number for Lead Free Parts (Ex. AS
7C33512PFS18A
-166TQCN)
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33=3.3V
3.Organization:
512
=
512
K
4.Pipelined mode
5.Deselect: S=Single cycle deselect
6.Organization: 18=x18
7.Production version: A=first production version
8. Clock speed (MHz)
9. Package type: TQ=TQFP
10. Operating temperature: C=Commercial (
0
°
C to 70
°
C); I=Industrial (
-40
°
C to 85
°
C)
11. N = Lead free part
Ordering information
Package –166 MHz –133 MHz
TQFP x18
AS7C33512PFS18A-166TQC AS7C33512PFS18A-133TQC
TQFP x18
AS7C33512PFS18A-166TQI AS7C33512PFS18A-133TQI
Part numbering guide
AS7C 33 512 PF S 18 A –XXX TQ C/I X
1
23
4
5
6789
10 11
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C33512PFS18A
Document Version: v.2.2
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alli-
ance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products
at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/
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assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
®
AS7C33512PFS18A
®
