CY7B991V
3.3 V RoboClock® Low Voltage
Programmable Skew Clock Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-0714 1 Rev. *L Revised November 2, 2016
3.3 V RoboCl ock ® Low Voltage Programmable Skew Clock Buffer
Features
■All output pair skew <100 ps typical (250 ps max)
■3.75 MHz to 80 MHz output operation
■User-selectable output functions:
❐Selectable skew up to 18 ns
❐Inverted and non-inverted
❐Operation at one-half and one-quarter input frequency
❐Operation at 2 × and 4 × input frequency (input as low as
3.75 MHz)
■Zero input to output delay
■50% duty cycle outputs
■Low-voltage transistor-transistor logic (LVTTL) outputs drive
50 terminated lines
■Operates from a single 3.3 V supply
■Low operating current
■32-pin plastic leaded chip carrier (PLCC) package
■Low cycle-to-cycle jitter (100 ps typical)
Functional Description
The CY7B991V 3.3 V RoboClock® low-voltage programmable
skew clock buffer (LVPSCB) offers user-selectable control over
system clock functions. These multiple output clock drivers
provide the system integrator with functions necessary to
optimize the timing of high-performance computer systems.
Each of the eight individual drivers – arranged in four pairs of
user controllable outputs – can drive terminated transmission
lines with impedances as low as 50 . This delivers minimal
output skews and full-swing logic le vels (LVTTL).
Each output is hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency, with outputs able to skew up to ±6
time units from their nominal ‘zero’ skew position. The
completely-integrated phase-locked loop (PLL) allows external
load and transmission line delay effects to be canceled. When
this ‘zero delay’ capability of the LVPSCB is combined with the
selectable output skew functions, the user can create
output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low freque ncy clock that i s multiplied by
two or four at the clock destination. This feature minimizes clock
distribution difficulty , allowing maximum system clock speed and
flexibility.
For a complete list of related resources, click here.
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL) SKEW
SELECT
MATRIX
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
FILTER
PHASE
FREQ
DET
Logic Block Diagram
CY7B991V
Document Number: 38-07141 Rev. *L Page 2 of 20
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................3
Block Diagram Description ..............................................4
Phase Frequency Detector and Filter ..........................4
VCO and Time Unit Generator ....................................4
Skew Select Matrix ... ... ................. ... .. ................. ... ... ...4
Test Mode ..........................................................................5
Operational Mode Descriptions ......................................6
Maximum Ratings .............................................................9
Operating Range ..................... .. ................. ... ................. ...9
Electrical Characteristics .................................................9
Capacitance ....................................................................10
Thermal Resistance ........................................................10
AC Test Loads and Waveforms .....................................10
Switching Characteri st ics (-2 optio n) .................... .......11
Switching Characteri st ics (-5 Optio n) ..........................12
Switching Characteristics (-7 Option) ..........................13
AC Timing Diagrams ............ ... ................. ... .. .................14
Ordering Information ......................................................15
Package Diagram ............................................................16
Acronyms ........................................................................ 17
Document Conventions .................. ... ... ................. ... .....17
Units of Measure ............. ................. ... ......................17
Document History Page ........................ ................. ... .. ...18
Sales, Solutions, and Legal Information ......................20
Worldwide Sales and Design Support .......................20
Products ....................................................................20
PSoC®Solutions .......................................................20
Cypress Developer Community ...................... ... ........20
Technical Support .....................................................20
CY7B991V
Document Number: 38-07141 Rev. *L Page 3 of 20
Pinouts Figure 1. 32-pin PLCC pinout
1234323130
17161514 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3F0
FS
V
REF
GND
TEST
2F1
FB
2Q1
2Q0
CCQ
2F0
GND
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
3Q1
3Q0
CCN
V
CCN
V
3F1
4F0
4F1
VCCN
4Q1
4Q0
GND
GND
VCCQ
Pin Definitions
Pin Name Pin Number I/O Description
REF 1 I Reference frequency input. This input supplies the frequency and timing against which
all functional variations are measured.
FB 17 I PLL feedback input (typically connected to one of the eight outputs).
FS 3 I Three-level frequency range select. See Table 1.
1F0, 1F1 26, 27 I Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
2F0, 2F1 29, 30 I Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
3F0, 3F1 4, 5 I Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
4F0, 4F1 6, 7 I Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
TEST 31 I Three-level select. See test mode section under the block diagram descriptions.
1Q0, 1Q1 24, 23 O Output pair 1. See Table 2.
2Q0, 2Q1 20, 19 O Output pair 2. See Table 2.
3Q0, 3Q1 15, 14 O Output pair 3. See Table 2.
4Q0, 4Q1 11, 10 O Output pair 4. See Table 2.
VCCN 9, 16, 18, 25 PWR Power supply for output drivers.
VCCQ 2, 8 PWR Power supply for internal circuitry.
GND 12, 13, 21, 22,
28, 32 PWR Ground.
CY7B991V
Document Number: 38-07141 Rev. *L Page 4 of 20
Block Diagram Description
Phase Frequency Detector and Filter
The phase frequency detector and filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input. They generate correction information to control the
frequency of the voltage controlled oscillator (VCO). These
blocks, along with the VCO, form a PLL that tracks the incoming
REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency that is used by the time unit genera tor
to create discrete time units, selected in the skew select matrix.
The operational range of the VCO is determined by the FS
control pin. The time unit (tU) is determined by the operating
frequency of the device and the l evel of the FS pin as shown in
Table 1.
Skew Select Matrix
The skew select matrix is comprised of four independent
sections. Each section has two low-skew, high fanout drivers
(xQ0, xQ1), and two corresponding three-level function select
(xF0, xF1) inputs. Table 2 shows the nine possible output
functions for each section as determined by the function se lect
inputs. All times are measured with respect to the REF input
assuming that the output connected to the FB input has 0tU
selected.
Table 1. Frequency Range Select and tU Calculation[1]
FS[2, 3] fNOM (MHz)
where N =
Approximate
Frequency (MHz) At
Which tU = 1.0 ns
Min Max
LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH 40 80 16 62.5
tU1
fNOM N
------------------------
=
Table 2. Programmable Skew Configurations [1]
Function Selects Output Functions
1F1, 2F1,
3F1, 4F1 1F0, 2F0,
3F0, 4F0 1Q0, 1Q1,
2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1
LOW LOW –4tUDivide by 2 Divide by 2
LOW MID –3tU–6tU–6tU
LOW HIGH –2tU–4tU–4tU
MID LOW –1tU–2tU–2tU
MID MID 0tU0tU0tU
MID HIGH +1tU+2tU+2tU
HIGH LOW +2tU+4tU+4tU
HIGH MID +3tU+6tU+6tU
HIGH HIGH +4tUDivide by 4 Inverted
Notes
1. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined b y the “normal” operating fr equency (fNOM) of the VCO and T ime Unit Generator (see Logic Block Dia gram). Nominal frequency
(fNOM) al ways appears at the outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs is fNOM
when the output connected to FB is undivided. The frequency of the REF and FB input s is fNOM/2 or fNOM/4 when the p art is conf igured for a frequency multiplication
using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 2.8 V.
CY7B991V
Document Number: 38-07141 Rev. *L Page 5 of 20
Test Mode
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the CY7B991V to operate
as explained in the Block Diagram Description on page 4. For testing purposes, any of the three-level inputs can have a remo vable
jumper to ground or be tied LOW through a 100- resistor. This ena bles an external tester to change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop d isconnecte d, a nd inp ut
levels supplied to REF directly controls all outputs. Relative output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs function based only on the connection of their own function select
inputs (xF0 and xF1) and the waveform characteristics of the REF input.
Figure 2. Typical Outputs with FB Connected to a Zero Skew Output Test Mode [4]
t 0– 6t U
t 0– 5t U
t 0– 4t U
t 0– 3t U
t 0– 2t U
t 0– 1t U
t 0
t 0+1t U
t 0
t 0
t 0
t 0
t 0
+2t U
+3t U
+4t U
+5t U
+6t U
FBInput
REFInput
– 6t U
– 4t U
– 3t U
– 2t U
– 1t U
0tU
+1tU
+2tU
+3tU
+4tU
+6tU
DIVIDED
INVERT
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
HH
3Fx
4Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
1Fx
2Fx
Note
4. FB connected to an output selected for “zero” skew (that is, xF1 = xF0 = MID).
CY7B991V
Document Number: 38-07141 Rev. *L Page 6 of 20
Operational Mode Descriptions
Figure 2 shows the LVPSCB configured as a zero skew clock buffer. In this mode, the CY7B991V is the basis for a low-skew clock
distribution tree. When all of the function select inputs (×F0, ×F1) are left open, the outputs are aligned and drive a terminated
transmission line to an independe nt load. The FB inpu t is tied to any outp ut in this configur ation and the operating frequen cy range
is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances
as low as 50 ), enables efficient printed circuit board design.
Figure 4 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between
outputs, the LVPSCB is programmed to stagger the timing of its
outputs. The four gro ups of output pairs are each pr ogrammed
to different output timing. Skew timing is adjusted over a wide
range in small increments using the function select pins. In this
configuration, the 4Q0 output is se nt back to FB and configured
for zero skew. The other three pairs of outputs are programmed
to yield different skews relative to the feedback. By advancing
the clock signal on the longer traces or retarding the clock signal
on shorter traces , all loads receive the cl ock pulse at the same
time.
Figure 4 shows the FB input connected to an output with 0 ns
skew (xF1, xF0 = MID) selected. The internal PLL synchronizes
the FB and REF inputs and aligns their rising edges to make
certain that all outputs have precise phase alignment.
Clock skews are advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the outpu t conn ected to FB is also skewe d.
Since “Zero Skew”, +tU, an d – tU are defi ned relative to output
groups, and the PLL aligns the rising edges of REF and FB, wider
output skews are created by proper se lection of the xFn inputs.
For example, a +10 tU between REF and 3Qx is achieved by
connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID,
and 3F1 = High. (Since FB aligns at –4 tU, and 3Qx skews to +6
tU, a total of +10 tU skew is realized.) Many other configurations
are realized by skewing both the outputs used as the FB input
and skewing the other outputs.
Figure 3. Zero Ske w and Zero Delay Clock Driver
SYSTEM
CLOCK
L1
L2
L3
L4
LENGTH L1 = L2 = L3 = L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
Z
0
LOAD
LOAD
LOAD
LOAD
REF
Z
0
Z
0
Z
0
Figure 4. Programmable Skew Clock Driver
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
CLOCK
L1
L2
L3
L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
Z
0
LOAD
LOAD
LOAD
LOAD
REF
Z
0
Z
0
Z
0
SYSTEM
CY7B991V
Document Number: 38-07141 Rev. *L Page 7 of 20
Figure 5 shows an example of the invert function of the L VPSCB.
In this example the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. Whe n 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising e dge of the F B input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs
to become the “inverted” outpu ts to the REF input. By selecting
the output connected to FB, you can have two inverted and six
non-inverted outputs or six inverted and two non-inverted
outputs. The correct configuration is determined by the need for
more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can
also be skewed to compensate for varying trace delays
independent of inversion on 4Q.
Figure 6 shows the L VPSCB configured as a clock multiplier. The
3Q0 output is programmed to divide by fo ur and is sent ba ck to
FB. This causes the PLL to in crease its frequency until the 3 Q0
and 3Q1 outputs are locked at 20 MHz, wh ile the 1Qx and 2Qx
outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two that results in a 40 MHz waveform
at these outputs. Note that the 20- and 40-MHz clocks fall
simultaneously and are out of phase on their rising edge. This
enables the designer to use the rising edges of the 1⁄2 frequency
and 1⁄4 frequency outputs without concern for rising edge skew.
The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are
skewed by programming their select inputs accordingly. Note
that the FS pin is wired for 80 MHz operation as that is the
frequency of the fastest output.
Figure 7 shows the LVPSCB in a clock divider application. 2Q0
is sent back to the FB input and programmed for zero skew . 3Qx
is programmed to divide by four . 4Qx is programmed to divide by
two. Note that the falling edges of the 4Qx an d 3Qx outp uts are
aligned. This enables use of the rising edges of the 1⁄2 frequency
and 1⁄4 frequency without concern for skew mismatch. The 1Qx
outputs are programmed to zero ske w and are aligned with the
2Qx outputs. In this example, the FS input is grounded to
configure the device in the 15 to 30 MHz range since the highest
frequency output is running at 20 MHz.
Figure 8 on page 8 shows some of the functions that are
selectable on the 3Qx and 4Qx ou tputs. These include inverted
outputs and outputs that offer divide-by-2 and divide-by-4 timing.
An inverted output enables the system designer to clock different
subsystems on opposite edges without suffering from the pulse
asymmetry typical of non-ideal loading. This function enables
each of the two subsystems to clock 180 degrees out of phase,
but still is aligned within the skew specification.
The divided outputs offer a zero delay divider for portion s of the
system that divide the clock by either two or four , and still remain
within a narrow skew of the “1X” clock. Without this feature, an
external divider is added, and the propagation delay of the
divider adds to the skew between the different clock signals.
These divided outputs, coupled with the PLL, enable the
LVPSCB to multiply the clock rate at the REF input by either two
or four. This mode allows the designer to distribute a low
frequency clock between various portions of the system. It also
locally multiplies the clock rate to a more suitable frequency,
while still maintaining the low skew characteristics of the clock
driver. The LVPSCB performs all of the functions described in
this section at the same ti me. It can multi ply by two and four or
divide by two (and four) at the same time that it shifts its outputs
over a wide range or maintains zero skew between selected
outputs.
Figure 5. Inverted Output Connections
Figure 6. Frequency Multiplier with Skew Connections
7B991V–11
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
7B991V–12
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
20 MHz
20 MHz
40 MHz
80 MHz
Figure 7. Frequency Divider Connections
7B991V–13
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
20 MHz
5 MHz
10 MHz
20 MHz
CY7B991V
Document Number: 38-07141 Rev. *L Page 8 of 20
Figure 9 shows the CY7B991V conne cted in series to construct a zero skew clock distribution tree between boards. Delays of the
downstream clock buffers are programmed to compensate for the wir e leng th (that is, select nega tive skew e qual to the wire dela y)
necessary to connect them to the master clock source, ap proximating a zero delay clock tree. Cascaded clock buffers accumulate
low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in a
series.
Figure 8. Multi-Function Clock Driver
20 MHz
DISTRIBUTION
CLOCK
80 MHz
INVERTED
Z
0
20 MHz
80 MHz
ZERO SKEW
80 MHz
SKEWED –3.125 ns (–4t
U
)
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF LOAD
LOAD
LOAD
LOAD
Z
0
Z
0
Z
0
Figure 9. Board-to-Board Clock Distribu tion
SYSTEM
CLOCK
Z
0
L1
L2
L3
L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
FS
FB
LOAD
LOAD
LOAD
LOAD
LOAD
TEST
Z
0
Z
0
Z
0
CY7B991V
Document Number: 38-07141 Rev. *L Page 9 of 20
Maximum Ratings
Operating outside these boundaries may affect the performance
and life of the device. These user guidelines are not tested.
Storage temperature ................. ................. –65 °C to 150 °C
Ambient temperature
with power applied .................... ................. –55 °C to 125 °C
Supply voltage to ground potential ..............–0.5 V to +7.0 V
DC input voltage ..........................................–0.5 V to +7.0 V
Output current into outputs (LOW) .............................64 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ..................................>2001 V
Latch up current ......................................................>200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0 °C to 70 °C 3.3 V 10%
Industrial –40 °C to 85 °C 3.3 V 10%
Electrical Characteristics
Over the Operating Range
Parameter [5] Description Test Conditions CY7B991V Unit
Min Max
VOH Output HIGH voltage VCC = Min, IOH = –12 mA 2.4 – V
VOL Output LOW voltage VCC = Min, IOL = 35 mA – 0.45 V
VIH Input HIGH voltage
(REF and FB inputs only) 2.0 VCC V
VIL Input LOW voltage
(REF and FB inputs only) –0.5 0.8 V
VIHH Three-level input HIGH
Voltage (Test, FS, xFn) [6] Min VCC Max. 0.87 × VCC V
CC V
VIMM Three-level input MID
voltage (Test, FS, xFn) [6] Min VCC Max. 0.47 × VCC 0.53 × V CC V
VILL Three-level input LOW
voltage (Test, FS, xFn) [6] Min VCC Max. 0.0 0.13 × VCC V
IIH Input HIGH leakage current
(REF and FB inputs only) VCC = Max, VIN = Max. – 20 A
IIL Input LOW leakage current
(REF and FB inputs only) VCC = Max, VIN = 0.4 V –20 – A
IIHH Input HIGH current (Test, FS,
xFn) VIN = VCC –200A
IIMM Input MID current (Test, FS, xFn) VIN = VCC/2 –50 50 A
IILL Input LOW current (Test, FS, xFn) VIN = GND –200 – A
IOS Short circuit current [7] VCC = Max, VOUT = G N D ( 25 °C only) –200 – mA
ICCQ Operating current used by
internal circuitry VCCN = VCCQ = Max,
All Input Selects Open Commercial – 95 mA
Military / Industrial – 100 mA
ICCN Output buffer current per output
pair [8] VCCN = VCCQ = Max, IOUT = 0 mA,
Input Selects Open, fMAX –19mA
Notes
5. See the last page of th is specification for Group A subgroup testing informa tion.
6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs glitch and the PLL requires an additional tLOCK time before all datasheet
limits are achieved.
7. CY7B991V is tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.
8. Total output current per ou tput pair is approximated by the following expression that includes device current plus load current:
CY7B991V:ICCN = [(4 + 0.11F) + [((835 –3F)/Z) + (.0022FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded output s; 0, 1, or 2
FC = F × C
CY7B991V
Document Number: 38-07141 Rev. *L Page 10 of 20
PD Power dissipation per output pair VCCN = VCCQ = Max, IOUT = 0 mA,
Input Selects Open, fMAX –104mW
Electrical Characteristics (continued)
Over the Operating Range
Parameter [5] Description Test Conditions CY7B991V Unit
Min Max
Capacitance
Parameter [ 9 , 10] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = 3.3 V 10 pF
Thermal Resist ance
Parameter [10] Description Test Conditions 32-pin PLCC
Package Unit
JA Thermal resistance
(junction to ambient) Test conditions follow standard test methods and
procedures for measuring thermal impedance,
according to EIA/JESD51.
44 °C/W
JC Thermal resistance
(junction to case) 26 °C/W
AC Test Loads and Waveforms
Figure 10. AC Test Loads and Waveforms
TTL ACTest Load TTL InputTestWaveform
VCC
R1
R2
CL
3.0 V
2.0 V
Vth =1.5 V
0.8 V
0.0 V
ns 1 ns
2.0 V
0.8 V
Vth =1.5 V
R1=100
R2=100
CL=30pF
(Includes fixture and probe capacitance)
Notes
9. Applies to REF and FB inputs only. Tested initially and after any design or process ch anges that may affect these parameters.
10.Tested initially and after any design or process changes that may affect these parameters.
CY7B991V
Document Number: 38-07141 Rev. *L Page 11 of 20
Switching Characteristics (-2 option)
Over the Operating Range
Parameter [1 1, 12] Description CY7B991V-2 Unit
Min Typ Max
fNOM Operating clock Frequency in MHz FS = LOW [11 , 13] 15 –30 MHz
FS = MID [11, 13] 25 –50
FS = HIGH [1 1, 13, 14] 40 –80
tRPWH REF pulse width HIGH measured at 1/2 × VCCQ threshold 3.65 – – ns
tRPWL REF pulse width LOW measured at 1/2 × VCCQ threshold 3.65 – – ns
tUProgrammable skew unit See Table 1
tSKEWPR Zero output matched-pair skew (XQ0, XQ1)[15 , 1 6] –0.05 0.2 ns
tSKEW0 Zero output skew (all outputs)[15, 17] –0.1 0.25 ns
tSKEW1 Output skew (rise-rise, fall-fall, same class outputs)[15, 18] –0.1 0.5 ns
tSKEW2 Output skew (rise-fall, nominal-inverted, divided-divided)[15, 18] –0.5 1.0 ns
tSKEW3 Output skew (rise-rise, fall-fall, different class outputs)[15, 18] –0.25 0.5 ns
tSKEW4 Output skew (rise-fall, nominal-divided, divided-inverted)[15, 18] –0.5 0.9 ns
tDEV Device-to-device skew[19, 20] – – 1.25 ns
tPD Propagation delay, REF rise to FB rise –0.25 0.0 +0.25 ns
tODCV Output duty cycle variation[21] –0.65 0.0 +0.65 ns
tPWH Output HIGH time deviation from 50%[22] – – 2.0 ns
tPWL Output LOW time deviation from 50%[22] – – 1.5 ns
tORISE Output rise time[22, 23] 0.15 1.0 1.2 ns
tOFALL Output fall time[22, 23] 0.15 1.0 1.2 ns
tLOCK PLL lock time[24] – – 0.5 ms
tJR Cycle-to-cycle output jitter RMS[19] – – 25 ps
Peak[19] –100 200 ps
Notes
1 1. The level to be set on FS is determined by the “normal” operating fre quency (fNOM) of the VCO and T ime Unit Generator (see Logic Block Diagram). Nominal freque ncy
(fNOM) always appears at the outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs i s fNOM
when the output connected to FB i s undi vided. The freque ncy of the REF and FB input s is f NOM/2 or fNOM/4 when the p art is confi gured for a frequency mult iplica tion
using a divided output as the FB input.
12.Test measurement levels for the CY7B9 91V are TTL le vels (1. 5 V to 1.5 V) . Test c ond itions assum e sig nal transi tion tim es of 2 ns or l ess and output loading as sho wn in the
AC Test Loads and W aveforms unl ess otherwise specif ied.
13.For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open co nnection. Internal termination
circuitry holds an unconnected input to VCC/2.
14.When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 2.8 V.
15.SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded
with 30 pF and terminated wit h 50 to VCC/2 (CY7B991V).
16.tSKEWPR is defined as the skew between a pai r of output s (XQ0 and XQ1) whe n all eight output s are selected f or 0tU.
17.tSKEW0 is defined as the skew between output s when they are select ed for 0tU. Other outputs ar e divided or invert ed but n ot shif ted.
18.There are three classes of outputs: Nominal (multiple of tU delay) , Inverted (4Q0 and 4Q1 only wi th 4F0 = 4F1 = HI GH), and Divided (3Qx a nd 4Qx o nly in Divide-b y-2 or
Divide-by-4 mode).
19.Guaranteed by statisti cal correlation. Tested initially and after any design or process changes that may af fect these parameters.
20.tDEV is the output-to -output skew betwe en any two devices opera ting under the same co nditions (V CC ambient temp erature, air f low , etc. )
21.tODCV is the deviation of the out put from a 50% duty cycle. Ou tput pulse widt h variations are inclu ded in t SKEW2 and tSKEW4 specifications.
22.S pecified with output s loaded with 30 pF for the CY7B991V–5 and –7 devices. Devices are terminated throug h 50 to VCC/2. tPWH is measured at 2.0 V . tPWL is measured
at 0.8 V.
23.tORISE and tOFALL measured between 0.8 V and 2.0 V.
24.tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until t PD is within specified limits.
CY7B991V
Document Number: 38-07141 Rev. *L Page 12 of 20
Switching Characteristics (-5 Option)
Over the Operating Range
Parameter [25, 26] Description CY7B991V-5 Unit
Min Typ Max
fNOM Operating clock frequency in MHz FS = LOW [25, 27] 15 –30 MHz
FS = MID [25, 27] 25 –50
FS = HIGH [25, 27] 40 –80
tRPWH REF pulse width HIGH measured at 1/2 × VCCQ threshold 3.65 – – ns
tRPWL REF pulse width LOW measured at 1/2 × VCCQ threshold 3.65 – – ns
tUProgrammable skew unit See Table 1
tSKEWPR Zero output matched-pair skew (XQ0, XQ1)[28 , 2 9] –0.1 0.25 ns
tSKEW0 Zero output skew (all outputs)[28, 29] –0.25 0.5 ns
tSKEW1 Output skew (rise-rise, fall-fall, same class outputs)[28, 30] –0.6 0.7 ns
tSKEW2 Output skew (rise-fall, nominal-inverted, divided-divided)[28, 30] –0.5 1.0 ns
tSKEW3 Output skew (rise-rise, fall-fall, different class outputs)[28, 30] –0.5 0.7 ns
tSKEW4 Output skew (rise-fall, nominal-divided, divided-inverted)[28, 30] –0.5 1.0 ns
tDEV Device-to-device skew[32, 33] – – 1.25 ns
tPD Propagation delay, REF rise to FB rise –0.5 0.0 +0.5 ns
tODCV Output duty cycle variation[34] –1.0 0.0 +1.0 ns
tPWH Output HIGH time deviation from 50%[35] – – 2.5 ns
tPWL Output LOW time deviation from 50%[35] ––3ns
tORISE Output rise time[35, 36] 0.15 1.0 1.5 ns
tOFALL Output fall time[35, 36] 0.15 1.0 1.5 ns
tLOCK PLL lock time[36] – – 0.5 ms
tJR Cycle-to-cycle output jitter RMS[32] – – 25 ps
Peak-to-peak[32] – – 200 ps
Notes
25.The level to be set on FS is determined by the “nor mal” operating frequency (fNOM) of the VCO and Ti me Unit Generator (see Logic Block Diagram). Nominal freq uency
(fNOM) always appears at the outputs when they are operated in thei r undivided modes (see Table 2). The frequency appearing at the REF and FB inputs is fNOM
when the output connected to FB is undivid ed. The frequency of the REF and FB inp uts is fNOM/2 or fNOM/4 whe n the p art is confi gured for a f requency multip lication
using a divided output as the FB input.
26.Test measurement levels f or the CY7B991V are TTL levels (1. 5 V to 1.5 V). Te st c ond iti ons as sum e s i g nal t r ans iti on tim es o f 2 ns or less and output loadin g as shown in the
AC Test Loads and Wavef orms unless otherwise specif ied.
27.For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unco nnected input to VCC/2.
28.tSKEWPR is defined as the skew between a p air of output s (XQ0 and XQ1) when al l eight output s are selected for 0tU.
29.tSKEW0 is defined as the skew between output s when they are selected for 0tU. Other outpu ts are divi ded or inverted but not shifte d.
30.tDEV is the output-to-output skew bet ween any two devices operating under the same condition s (VCC ambient temper ature, air flow, etc.)
31.CL = 0 pF . For CL = 30 pF, tSKEW0 = 0.35 ns.
32.SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been select ed when all are lo aded
with 30 pF and terminat ed with 50 to VCC/2 (CY7 B991V).
33.tODCV is the deviation of the output f rom a 50% duty cycle . Output pulse widt h variations are included in t SKEW2 and tSKEW4 specification s.
34.Specified with outputs loaded with 30 pF for the CY7B991V–5 and –7 devices. Devices are terminated thro ugh 50 to VCC/2. tPWH is measured at 2.0 V . tPWL is measured
at 0.8 V.
35.tORISE and tOFALL measured between 0.8 V and 2.0 V .
36.tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limit s. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specifie d limits.
CY7B991V
Document Number: 38-07141 Rev. *L Page 13 of 20
Switching Characteristics (-7 Option)
Over the Operating Range
Parameter [37, 38] Description CY7B991V–7 Unit
Min Typ Max
fNOM Operating clock Frequency in MHz FS = LOW [37, 39] 15 –30 MHz
FS = MID [37, 39] 25 –50
FS = HIGH [37, 39] 40 –80
tRPWH REF pulse width HIGH measured at 1/2 × VCCQ threshold 3.65 – – ns
tRPWL REF pulse width LOW measured at 1/2 × VCCQ threshold 3.65 – – ns
tUProgrammable skew unit See Table 1
tSKEWPR Zero output matched pair skew (XQ0, XQ1)[40, 41] –0.1 0.25 ns
tSKEW0 Zero output skew (All Outputs)[40, 42] –0.3 0.75 ns
tSKEW1 Output skew (rise-rise, fall-fall, same class outputs)[43, 44] –0.6 1.0 ns
tSKEW2 Output skew (rise-fall, nominal-inverted, divided-divided)[40, 45] –1.0 1.5 ns
tSKEW3 Output skew (rise-rise, fall-fall, different class outputs)[40, 45] –0.7 1.2 ns
tSKEW4 Output skew (rise-fall, nominal-divided, divided-inverted)[40, 45] –1.2 1.7 ns
tDEV Device-to-device skew[43, 46] – – 1.65 ns
tPD Propagation delay, REF rise to FB rise –0.7 0.0 +0.7 ns
tODCV Output duty cycle variation[46] –1.2 0.0 +1.2 ns
tPWH Output HIGH time deviation from 50%[47] ––3ns
tPWL Output LOW time deviation from 50%[47] – – 3.5 ns
tORISE Output rise time[47, 48] 0.15 1.5 2.5 ns
tOFALL Output fall time[47, 48] 0.15 1.5 2.5 ns
tLOCK PLL lock time[49] – – 0.5 ms
tJR Cycle-to-cycle output jitter RMS[50] – – 25 ps
Peak-to-peak[50] – – 200 ps
Notes
37.The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and T ime Unit Generator (see Logic Block Diagra m). Nominal frequency
(fNOM) always appears at the outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs i s fNOM
when the output connected to FB i s undi vided. The freque ncy of the REF and FB input s is f NOM/2 or fNOM/4 when the p art is confi gured for a frequency mult iplica tion
using a divided output as the FB input.
38.Test measurement levels for the CY7B9 91V are TTL le vels (1. 5 V to 1.5 V) . Test c ond itions assum e sig nal transi tion tim es of 2 ns or l ess and output loading as sho wn in the
AC Test Loads and W aveforms unl ess otherwise specif ied.
39.For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open co nnection. Internal termination
circuitry holds an unconnected input to VCC/2.
40.tSKEWPR is defined as the skew between a pai r of output s (XQ0 and XQ1) whe n all eight output s are selected f or 0tU.
41.tSKEW0 is defined as the skew between output s when they are select ed for 0tU. Other outputs ar e divided or invert ed but n ot shif ted.
42.CL = 0 pF. For CL = 30 pF, tSKEW0 = 0.35 n s.
43.SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded
with 30 pF and terminated wit h 50 to VCC/2 (CY7B991V).
44.There are three classes of outputs: Nominal (multiple of tU delay) , Inverted (4Q0 and 4Q1 only wi th 4F0 = 4F1 = HI GH), and Divided (3Qx a nd 4Qx o nly in Divide-b y-2 or
Divide-by-4 mode).
45.tDEV is the output-to -output skew betwe en any two devices opera ting under the same co nditions (V CC ambient temp erature, air f low , etc. )
46.tODCV is the deviation of the out put from a 50% duty cycle. Ou tput pulse widt h variations are inclu ded in t SKEW2 and tSKEW4 specifications.
47.S pecified with output s loaded with 30 pF for the CY7B991V–5 and –7 devices. Devices are terminated throug h 50 to VCC/2. tPWH is measured at 2.0 V . tPWL is measured
at 0.8 V.
48.tORISE and tOFALL measured between 0.8 V and 2.0 V.
49.tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until t PD is within specified limits.
50.Guaranteed by statisti cal correlation. Tested initially and after any design or process changes that may af fect these parameters.
CY7B991V
Document Number: 38-07141 Rev. *L Page 14 of 20
AC Timing Diagrams
tODCV
tODCV
tREF
REF
FB
Q
OTHERQ
INVERTED Q
REF DIVIDED BY 2
REF DIVIDED BY 4
tRPWH
tRPWL
tPD
tSKEWPR,
tSKEW0,1tSKEWPR,
tSKEW0,1
tSKEW2 tSKEW2
tSKEW3,4tSKEW3,4tSKEW3,4
tSKEW1,3, 4tSKEW2,4
tJR
CY7B991V
Document Number: 38-07141 Rev. *L Page 15 of 20
Ordering Code Definitions
Ordering Information
Speed (ps) Ordering Code Package Type Operating
Range
250 CY7B991V-2JC 32 -pin PLCC Commercial
CY7B991V-2JCT 32-pin PLCC – Tape and Reel Commercial
500 CY7B991V-5JI 32 -pin PLCC Industrial
CY7B991V-5JIT 32-pin PLCC – Tape and Reel Industrial
Pb-free
250 CY7B991V-2JXC 32 -pin PLCC Commercial
CY7B991V-2JXCT 32-pin PLCC – Tape and Reel Commercial
500 CY7B991V-5JXC 32 -pin PLCC Commercial
CY7B991V-5JXCT 32-pin PLCC – Tape and Reel Commercial
CY7B991V-5JXI 32-pin PLCC Industrial
CY7B991V-5JXIT 32-pin PLCC – Tape and Reel Industrial
750 CY7B991V-7JXC 32 -pin PLCC Commercial
CY7B991V-7JXCT 32-pin PLCC – Tape and Reel Commercial
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial = 0 C to +70 C; I = Industrial = –40 C to 85 C
X = Pb-free; X Absent = Leaded
Package Type:
J = 32-pin PLCC
Device Option (Performance): X = 2 or 5 or 7
Base Part Number
Company ID: CY = Cypress
CY 7B991V - J X XX X
CY7B991V
Document Number: 38-07141 Rev. *L Page 16 of 20
Package Diagram
Figure 11. 32-pin PLCC (0.453 × 0.553 Inche s) J32 Pack age Outline, 51-85002
51-85002 *E
CY7B991V
Document Number: 38-07141 Rev. *L Page 17 of 20
Acronyms Document Conventions
Units of Measure
Table 3. Acronyms Used in this Document
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
FB Feedback
LVPSCB Low-Voltage Programmable Skew Clock Buffer
LVTTL Low-Voltage Transistor-Transistor Logic
PLL Phase-Locked Loop
PLCC Plastic Leaded Chip Carrier
RF Reference Freq uency
RMS Root Mean Square
VCO Voltage Controlled Oscillator
Table 4. Units of Measure
Symbol Unit of Measure
°C degree Celsius
kkilohm
µA microampere
µs microsecond
mA milliampere
ms millisecond
mW milliwatt
MHz megahertz
ns nanosecond
ohm
pF picofarad
ps picosecond
Vvolt
Wwatt
CY7B991V
Document Number: 38-07141 Rev. *L Page 18 of 20
Document History Page
Document Title: CY7B991V, 3.3 V RoboClock® Low Voltage Programmable Skew Clock Buffer
Document Number: 38-07141
Revision ECN Submission
Date Orig. of
Change Description of Change
** 110250 12/17/01 SZV Change from Specifi ca tion number: 38-00641 to 38-07141.
*A 293239 See ECN RGL Updated Features:
Removed “Jitter < 200 ps peak-to-peak (< 25 ps RMS)”.
Added “Jitter 100 ps (typical)”.
Updated Switching Characteristics (-2 option):
Added typical value of tJR parameter as “100 ps” corresponding to “Peak”.
Updated Ordering Information:
Updated part numbers.
*B 1199925 See ECN KVM /
AESA Removed “Switching Characte ristics (-2 option)”.
Updated Ordering Information:
No change in part numbers.
Changed format only.
*C 1286064 See ECN AESA Change status from Preliminary to Final.
*D 2584293 10/10/08 AESA Added Switching Characteristics (-2 option).
Updated to new te mplate.
*E 2761988 09/10/09 CXQ Updated Test Mode :
Replaced “100W resistor” with “100 resistor”.
Updated Ordering Information:
No change in part numbers.
Replaced “Pb” with “pin” in “Package Type” column.
*F 2905834 04/06/2010 CXQ Updated Ordering Information:
Removed inactive part numbers CY7B991V-5JC, CY7B991V-5JCT,
CY7B991V-7JC and CY7B991V-7JCT.
Updated Package Diagram.
*G 3041840 09/29/2010 CXQ Fixed various format and typographical errors.
Updated Pinouts:
Updated Figure 1 (Fixe d pin 8 lab el).
Updated Pin Defini tions:
Added “Pin Number” column.
Updated Electrical Chara c teristics:
Removed values from “Max” column of ILL and IOS parameters and added the
same values in “Min” column.
Removed note “These inputs are normally wired to VCC, GND, or left
unconnected (actual threshold voltages vary as a percentage of VCC). Internal
termination resistors hold uncon nected inputs at VCC/2. If these inputs are
switched, the function and timing of the outputs may glitch and the PLL may
require an additional tLOCK time before all datasheet limits are achieved.” and
its reference in “Description” column of PD parameter.
*H 4161003 10/16/2013 CINM Updated Package Di agram:
spec 51-85002 – Changed revision from *C to *D.
Updated to new te mplate.
Completing Sunset Review.
*I 4598452 12/16/2014 TAVA Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Added AC Ti mi ng Di a gra ms.
CY7B991V
Document Number: 38-07141 Rev. *L Page 19 of 20
*J 4644120 01/28/2015 TAVA Updated Switching Characteristics (-2 option):
Updated description of tRPWH and tRPWL parameters.
Changed minimum value of tRPWH parameter from 5 ns to 3.65 ns.
Changed minimum value of tRPWL parameter from 5 ns to 3.65 ns.
Updated Switching Characteristics (-5 Option):
Updated description of tRPWH and tRPWL parameters.
Changed minimum value of tRPWH parameter from 5 ns to 3.65 ns.
Changed minimum value of tRPWL parameter from 5 ns to 3.65 ns.
Updated Switching Characteristics (-7 Option):
Updated description of tRPWH and tRPWL parameters.
Changed minimum value of tRPWH parameter from 5 ns to 3.65 ns.
Changed minimum value of tRPWL parameter from 5 ns to 3.65 ns.
Updated Package Diagram:
spec 51-85002 – Changed revision from *D to *E.
*K 5276098 05/18/2016 PSR Updated Electrical Charac teristics:
Updated Note 8 (Replaced “FC = F < C” with “FC = F × C”).
Added Thermal Resistance.
Updated to new te mplate.
*L 5507104 11/02/2016 PAWK Updated Sales, Solutions, and Legal Information and added WICED in the
copyright notice .
Document History Page (continued)
Document Title: CY7B991V, 3.3 V RoboClock® Low Voltage Programmable Skew Clock Buffer
Document Number: 38-07141
Revision ECN Submission
Date Orig. of
Change Description of Change
Document Number: 38-07141 Rev. *L Revised November 2, 2016 Page 20 of 20
CY7B991V
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provided by Cypr ess, unmodified) to make , use, distribute, and import the Sof tware solely for use with Cypress hardwar e products. Any ot her use, reprodu ction, modificatio n, translation, or co mpilation
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