Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
3A, 12V, Synchronous-Rectified Buck Converter
FeaturesGeneral Description
•Wide Input Voltage from 4.3V to 14V
•Output Current up to 3A
•Adjustable Output Voltage from 0.8V to VIN
- ±2% System Accuracy
•70mΩ Integrated Power MOSFETs
•High Efficiency up to 95%
- Automatic Skip/PWM Mode Operation
•Current-Mode Operation
- Easy Feedback Compensation
- Stable with Low ESR Output Capacitors
- Fast Load/Line Transient Response
•Power-On-Reset Monitoring
•Fixed 500kHz Switching Frequency in PWM Mode
•Built-In Digital Soft-Start and Soft-Stop
•Current-Limit Protection with Frequency Foldback
•123% Over-Voltage Protection
•Hiccup-Mode 50% Under-Voltage Protection
•Over-Temperature Protection
•<3µA Quiescent Current in Shutdown Mode
• Small SOP-8 Package
•Lead Free and Green Devices Available
(RoHS Compliant)
Applications
•OLPC, UMPC
•Notebook Computer
• Handheld Portable Device
•Step-Down Converters Requiring High Efficiency
and 3A Output Current
Output Current, IOUT(A)
Efficiency (%)
For high efficiency over all load current range, the
APW7142 is equipped with an automatic Skip/PWM mode
operation. At light load, the IC operates in the Skip mode,
which keeps a constant minimum inductor peak current,
to reduce switching losses. At heavy load, the IC works in
PWM mode, which inductor peak current is programmed
by the COMP voltage, to provide high efficiency and excel-
lent output voltage regulation.
The APW7142 is also equipped with power-on-reset,
soft-start, soft-stop, and whole protections (under-voltage,
over-voltage, over-temperature, and current-limit) into a
single package. In shutdown mode, the supply current
drops below 3µA.
This device, available in a 8-pin SOP-8 package, pro-
vides a very compact system solution with minimal exter-
nal components and PCB area.
The APW7142 is a 3A synchronous-rectified Buck con-
verter with integrated 70mΩ power MOSFETs. The
APW7142, designed with a current-mode control scheme,
can convert wide input voltage of 4.3V to 14V to the output
voltage adjustable from 0.8V to VIN to provide excellent
output voltage regulation.
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
VIN=12V, VOUT=3.3V, L1=4.7µF
VIN=12V, VOUT=5V, L1=6.8µF
VIN=5V, VOUT=3.3V, L1=2.2µF
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw2
Ordering and Marking Information
Absolute Maximum Ratings (Note 1)
Symbol Parameter Rating Unit
VIN VIN Supply Voltage (VIN to AGND) -0.3 ~ 15 V
> 100ns -1 ~ VIN+1
VLX LX to GND Voltage < 100ns - 5 ~ VIN+5 V
PGND to AGND Voltage -0.3 ~ +0.3 V
EN to AGND Voltage -0.3 ~ VIN+0.3 V
FB, COMP to AGND Voltage -0.3 ~ 6 V
PD Power Dissipation Internally Limited W
Maximum Junction Temperature 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Thermal Resistance in Free Air (Note 2)
SOP-8
80 oC/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Pin Configuration
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
APW7142 Package Code
K : SOP-8
Operating Junction Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Handling Code
Temperature Range
Package Code
Assembly Material
APW7142 K : XXXXX - Date Code
APW7142
XXXXX
1
2
3
4
8
7
6
5
LX
LX
EN
COMP
PGND
VIN
AGND
FB
APW7142
SOP-8
Top View
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw3
Symbol Parameter Range Unit
VIN VIN Supply Voltage 4.3 ~ 14 V
VOUT Converter Output Voltage 0.8 ~ VIN V
IOUT Converter Output Current 0 ~ 3 A
CIN Converter Input Capacitor (MLCC) 8 ~ 50 µF
Converter Output Capacitor 20 ~ 1000 µF
COUT Effective Series Resistance 0 ~ 60 mΩ
LOUT Converter Output Inductor 1 ~ 22 µH
Resistance of the Feedback Resistor connected from FB to GND 1 ~ 20 kΩ
TA Ambient Temperature -40 ~ 85 oC
TJ Junction Temperature -40 ~ 125 oC
Note 3: Refer to the Typical Application Circuits
Recommended Operating Conditions (Note 3)
Electrical Characteristics
APW7142
Symbol Parameter Test Conditions Min. Typ. Max.
Unit
SUPPLY CURRENT
IVIN VIN Supply Current V
FB = VREF +50mV, VEN=3V, LX=NC - 0.5 1.5 mA
IVIN_SD VIN Shutdown Supply Current V
EN = 0V - - 3 µA
POWER-ON-RESET (POR) VOLTAGE THRESHOLD
VIN POR Voltage Threshold V
IN rising 3.9 4.1 4.3 V
VIN POR Hysteresis - 0.5 - V
REFERENCE VOLTAGE
VREF Reference Voltage Regulated on FB pin - 0.8 - V
T
J = 25oC, IOUT=10mA, VIN=12V -1.0 - +1.0
Output Voltage Accuracy I
OUT=10mA~3A, VIN=4.75~14V -2.0 - +2.0 %
Line Regulation V
IN = 4.75V to 14V - +0.02
- %/V
Load Regulation IOUT = 0.5A ~ 3A - -0.04
- %/A
OSCILLATOR AND DUTY CYCLE
FOSC Oscillator Frequency T
J = -40 ~ 125oC, VIN = 4.75 ~ 14V 450 500 550 kHz
Foldback Frequency V
OUT = 0V - 80 - kHz
Maximum Converter’s Duty - 99 - %
TON_MIN Minimum Pulse Width of LX - 150 - ns
CURRENT-MODE PWM CONVERTER
Gm Error Amplifier Transconductance
V
FB=VREF±50mV - 200 - µA/V
Error Amplifier DC Gain COMP = NC - 80 - dB
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C, unless otherwise
specified. Typical values are at TA=25°C.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw4
Electrical Characteristics (Cont.)
APW7142
Symbol Parameter Test Conditions Min. Typ. Max.
Unit
CURRENT-MODE PWM CONVERTER (CONT.)
Current-Sense to COMP Voltage
Transresistance - 0.048
- V/A
VIN = 5V, TJ=25°C - 90 110
High-side Switch Resistance VIN = 12V, TJ=25°C - 70 90 mΩ
VIN = 5V, TJ=25°C - 90 110
Low-side Switch Resistance VIN = 12V, TJ=25°C - 70 90 mΩ
PROTECTIONS
ILIM High-Side Switch Current-Limit Peak Current 4.0 5.5 7.0 A
VTH_UV FB Under-Voltage Threshold V
FB falling 45 50 55 %
VTH_OV FB Over-Voltage Threshold V
FB rising 118 123 128 %
FB Under-Voltage Debounce - 1 - µs
TOTP Over-Temperature Trip Point - 150 - oC
Over-Temperature Hysteresis - 40 - oC
TD Dead-Time V
LX = -0.7V - 20 - ns
SOFT-START, SOFT-STOP, ENABLE AND INPUT CURRENTS
TSS Soft-Start / Soft-Stop Interval 1.5 2 2.5 ms
EN Logic Low Voltage V
EN falling - - 0.5 V
EN Logic High Voltage V
EN rising 2.1 - - V
High-Side Switch Leakage Current
V
EN = 0V, VLX = 0V - - 2 µA
IFB FB Pin Input Current -100 - +100
nA
IEN EN Pin Input Current V
EN = 0V ~ VIN -100 - +100
nA
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C,
unless otherwise specified. Typical values are at TA=25°C.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw5
Typical Operating Characteristics
VIN Input Current vs. Supply Voltage
Supply Voltage, VIN (V)
VIN Input Current, IVIN(mA)
Current Limit Level (Peak Current)
vs. Junction Temperature
Junction Temperature, TJ (oC)
Output Voltage vs. Supply Voltage
Supply Voltage, VIN (V)
Output Current vs. Efficiency Output Voltage vs. Output Current
Output Current, IOUT(A)Output Current, IOUT(A)
Output Voltage, VOUT (V)
Efficiency (%)
Output Voltage, VOUT (V)
Current Limit Level, ILIM(A)
Reference Voltage, VREF (V)
Junction Temperature, TJ (oC)
Reference Voltage vs. Junction Temperature
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
VIN=12V, VOUT=3.3V, L1=4.7µF
VIN=12V, VOUT=5V, L1=6.8µF
VIN=5V, VOUT=3.3V, L1=2.2µF
3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
0 1 2 3
4.5
5
5.5
6
6.5
7
-40 -20 0 20 40 60 80 100 120 140 4 6 8 10 12 14
IOUT=500mA
3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
0.0
0.5
1.0
1.5
2.0
0 2 4 6 8 10 12 14
VFB=0.85V
0.784
0.788
0.792
0.796
0.800
0.804
0.808
0.812
0.816
-50 -25 0 25 50 75 100 125 150
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw6
Typical Operating Characteristics (Cont.)
Oscillator Frequency vs.
Junction Temperature
Oscillator Frequency, FOSC(kHz)
Junction Temperature, TJ (oC)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
450
460
470
480
490
500
510
520
530
540
550
-50 -25 0 25 50 75 100 125 150
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw7
EnableShutdown
Operating Waveforms
Power OnPower Off
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
CH3 : IL1 , 2A/div
Time : 1ms/div
1
2
3
VIN
VOUT
IL1
IOUT=3A
CH1 : VEN , 5V/div
CH2 : VOUT , 2V/div
CH3 : IL1 , 2A/div
Time : 1ms/div
1
2
3
VEN
VOUT
IL1
IOUT=3A
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
CH3 : IL1 , 2A/div
Time : 10ms/div
1
2
3
VIN
VOUT
IL1
IOUT=3A
CH1 : VEN , 5V/div
CH2 : VOUT , 2V/div
CH3 : IL1, 2A/div
Time : 100µs/div
VEN
VOUT
IL1
1
2
3
IOUT=3A
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw8
Operating Waveforms (Cont.)
Load Transient Response Load Transient Response
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
Short CircuitShort Circuit
CH1 : VLX , 10V/div
CH2 : VOUT , 2V/div
CH3 : IL1 , 5A/div
Time : 20µs/div
IOUT =3~7A
VLx
VOUT
IL1
1
2
3
CH1 : VLX , 5V/div
CH2 : VOUT , 200mV/div
CH3 : IL1 , 5A/div
Time : 5ms/div
1
2
3
VLX
VOUT
IL1
VOUT is shorted to GND by a short wire
CH1 : VOUT , 200mV/div
CH2 : IL1 , 2A/div
Time : 100µs/div
VOUT
IL1
1
2
IOUT= 50mA-> 3A ->50mA
IOUT rising/falling time=10µs
CH1 : VOUT , 100mV/div
CH2 : IL1 , 2A/div
Time : 100µs/div
IL1
VOUT
1
2
IOUT= 0.5A-> 3A ->0.5A
IOUT rising/falling time=10µs
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw9
Operating Waveforms (Cont.)
Line Transient
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
Switching WaveformSwitching Waveform
Over-Voltage Protection
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
CH3 : VLX , 5V/div
CH4 : IL1 , 5A/div
Time : 20µs/div
VIN
VOUT
IL1
1
2
4
3
VLX
IOUT=-1A
CH1 : VIN , 5V/div
CH2 : VOUT , 50mV/div (Voffset=3.3V)
CH3 : IL1 , 2A/div
Time : 100µs/div
VIN
VOUT
IL1
1
2
3
VIN= 5~12V VIN rising/falling time=20µs
CH1 : VLX , 5V/div
CH2 : IL1 , 2A/div
Time : 1µs/div
IL1
VLX
IOUT=0.2A
1
2
CH1 : VLX , 5V/div
CH2 : IL1 , 2A/div
Time : 1µs/div
VLX
IL1
IOUT=3A
1
2
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw10
Pin Description
PIN
NO. NAME FUNCTION
1 PGND Power Ground of the APW7142, which is the source of the N-channel power MOSFET.
Connect this pin to system ground with lowest impedance.
2 VIN
Power Input. VIN supplies the power (4.3V to 14V) to the control circuitry, gate drivers
and step-down converter switches. Connecting a ceramic bypass capacitor and a
suitably large capacitor between VIN and both of AGND and PGND eliminates switching
noise and voltage ripple on the input to the IC.
3 AGND Ground of MOSFET Gate Drivers and Control Circuitry.
4 FB Output feedback Input. The APW7142 senses the feedback voltage via FB and
regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’s
output sets the output voltage from 0.8V to VIN.
5 COMP Output of the error amplifier. Connect a series RC network from the COMP to the GND to
compensate the regulation control loop. In some cases, an additional capacitor from the
COMP to the GND is required.
6 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn
on the regulator, drive it low to turn it off. Connect this pin to the VIN if it is not used.
7, 8 LX Power Switching Output. LX is the junction of the high-side and low-side power
MOSFETs to supply power to the output LC filter.
Block Diagram
LX
Gate
Control
VREF
Soft-Start /
Soft-Stop
and
Fault Logic
Error
Amplifier
FB
Inhibit
50%VREF UVP
PGND
POR
Soft-Start /
Soft-Stop
Power-On-
Reset
VIN
VIN
Enable
Current Sense
Amplifier
EN
COMP
OVP
123%VREF
Oscillator
500kHz
Slope
Compensation
Current
Compartor
1.5V
VIN
Over
Temperature
Protection
Zero-Crossing
Comparator
Current
Limit
FB
UG
LG
Gate
Driver
Gate
Driver
AGND
Gm
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw11
Typical Application Circuits
1. 4.3~14V Single Power Input Step-Down Converter (with a Ceramic Output Capacitor)
a. Cost-effective Feedback Compensation (C4 is not connected)
b. Fast-Transient-Response Feedback Compensation (C4 is connected)
VIN(V) VOUT(V) L1(µH) C2(µF) C2 ESR(mΩ)R1(kΩ)R2(kΩ)R3(kΩ)C3(pF)
12 5 6.8 22 563.0 12 10.0 1500
12 5 6.8 44 363.0 12 20.0 1500
12 3.3 4.7 22 546.9 15 10.0 1500
12 3.3 4.7 44 346.9 15 22.0 1500
12 2 3.3 22 530.0 20 10.0 1500
12 2 3.3 44 330.0 20 20.0 1500
12 1.2 2.2 22 57.5 15 8.2 1800
12 1.2 2.2 44 37.5 15 16.0 1800
53.3 2.2 22 546.9 15 8.2 680
53.3 2.2 44 346.9 15 20.0 680
51.2 2.2 22 57.5 15 3.0 1800
51.2 2.2 44 37.5 15 7.5 1800
VIN(V) VOUT(V) L1(µH) C2(µF) C2 ESR(mΩ)R1(kΩ)R2(kΩ)C4(pF) R3(kΩ)C3(pF)
12 5 6.8 22 563.0 12 47 33.0 470
12 5 6.8 44 363.0 12 47 68.0 470
12 3.3 4.7 22 546.9 15 47 22.0 680
12 3.3 4.7 44 3 46.9 15 47 47.0 680
12 2 3.3 22 530.0 20 47 13.0 1200
12 2 3.3 44 330.0 20 47 27.0 1200
12 1.2 2.2 22 57.5 15 150 7.5 2200
12 1.2 2.2 44 37.5 15 150 15.0 2200
53.3 2.2 22 546.9 15 56 20.0 220
53.3 2.2 44 346.9 15 56 43.0 220
51.2 2.2 22 57.5 15 330 3.3 1800
51.2 2.2 44 3 7.5 15 330 8.2 1500
LX
EN
6
VIN
2
AGND
3
COMP
5
8
U1
APW7142
FB 4
VOUT
L1
VIN
C1
LX 7
Enable
Shutdown
PGND 1C2
R1
±1%
R2
±1% C4
±30%, Optional
R3
±5%
C3
±30%
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw12
Typical Application Circuits (Cont.)
2. +12V Single Power Input Step-Down Converter (with an Electrolytic Output Capacitor)
LX
EN
6
VIN
2
AGND
3
COMP
5
8
U1
APW7142
FB 4
VOUT
3.3V/3A
L1
4.7µH /3A
VIN
12V
C1
2.2µF
LX 7
Enable
Shutdown
PGND 1C2
470µF
(ESR=30mΩ)
R1
46.9K
±1%
R2
15K
±1% C4
47pF
±30%
R3
62K
±5%
C3
680pF
±30%
C5
470µF
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw13
Function Description
Over-Voltage Protection (OVP)
The over-voltage function monitors the output voltage by
FB pin. When the FB voltage increases over 123% of the
reference voltage due to the high-side MOSFET failure or
for other reasons, the over-voltage protection comparator
will force the low-side MOSFET gate driver high. This ac-
tion actively pulls down the output voltage and eventually
attempts to blow the internal bonding wires. As soon as
the output voltage is within regulation, the OVP compara-
tor is disengaged. The chip will restore its normal
operation. This OVP scheme only clamps the voltage
overshoot, and does not invert the output voltage when
otherwise activated with a continuously high output from
low-side MOSFET driver - a common problem for OVP
schemes with a latch.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction tempera-
ture of the APW7142. When the junction temperature ex-
ceeds TJ = +150oC, a thermal sensor turns off the both
power MOSFETs, allowing the devices to cool. The ther-
mal sensor allows the converters to start a start-up pro-
cess and to regulate the output voltage again after the
junction temperature cools by 40oC. The OTP is designed
with a 40oC hysteresis to lower the average TJ during
continuous thermal overload conditions, increasing life-
time of the APW7142.
Enable/Shutdown
Driving EN to the ground initiates a soft-stop process and
then places the APW7142 in shutdown. When in
shutdown, after the soft-stop process is completed, the
internal power MOSFETs turn off, all internal circuitry shuts
down and the quiescent supply current reduces to less
than 3µA.
VIN Power-On-Reset (POR)
The APW7142 keeps monitoring the voltage on VIN pin to
prevent wrong logic operations which may occur when
VIN voltage is not high enough for the internal control
circuitry to operate. The VIN POR has a rising threshold of
4.1V (typical) with 0.5V of hysteresis.
During startup, the VIN voltage must exceed the enable
voltage threshold. Then, the IC starts a start-up process
and ramps up the output voltage to the voltage target.
Digital Soft-Start
The APW7142 has a built-in digital soft-start to control the
rise rate of the output voltage and limit the input current
surge during start-up. During soft-start, an internal volt-
age ramp (VRAMP), connected to one of the positive inputs
of the error amplifier, rises up from 0V to 0.95V to replace
the reference voltage (0.8V) until the voltage ramp reaches
the reference voltage.
During soft-start without output over-voltage, the APW7142
converter’s sinking capability is disabled until the output
voltage reaches the voltage target.
Digital Soft-Stop
At the moment of shutdown controlled by EN signal, un-
der-voltage event or over-temperature protection, the
APW7142 initiates a digital soft-stop process to discharge
the output voltage in the output capacitors. Certainly, the
load current also discharges the output voltage.
During soft-stop, the internal voltage ramp (VRAMP) falls
down rises from 0.95V to 0V to replace the reference
voltage. Therefore, the output voltage falls down slowly at
the light load. After the soft-stop interval elapses, the soft-
stop process ends and the the IC turns on the low-side
power MOSFET.
Output Under-Voltage Protection (UVP)
In the operational process, if a short-circuit occurs, the
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the re-
quired regulation range. The under-voltage continually
monitors the FB voltage after soft-start is completed. If a
load step is strong enough to pull the output voltage lower
than the under-voltage threshold, the IC shuts down
converter’s output.
The under-voltage threshold is 50% of the nominal out-
put voltage. The under-voltage comparator has a built-in
2µs noise filter to prevent the chips from wrong UVP shut-
down being caused by noise. The under-voltage protec-
tion works in a hiccup mode without latched shutdown.
The IC will initiate a new soft-start process at the end of
the preceding delay.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw14
Current-Limit Protection
The APW7142 monitors the output current, flows through
the high-side power MOSFET, and limits the current peak
at current-limit level to prevent loads and the IC from dam-
aging during overload or short-circuit conditions.
Frequency Foldback
The foldback frequency is controlled by the FB voltage.
When the output is shortened to the ground, the frequency
of the oscillator will be reduced to 80kHz. This lower fre-
quency allows the inductor current to safely discharge,
thereby preventing current runaway. The oscillator’s fre-
quency will gradually increase to its designed rate when
the feedback voltage on the FB again approaches 0.8V.
Function Description (Cont.)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw15
Application Information
Figure 1 Converter Waveforms
........... (1)
........... (2)
L · FD)-(1 · V
IOSC
OUT
=∆
VIN
VOUT
CIN
COUT
L
Q1
LX ESR
ILIOUT
IQ1
ICOUT
VIN
Q2
IOUT
VLX
T=1/FOSC
IL
IQ1
ICOUT
IOUT
I
I
DT
VOUT
VOUT
V
V
DIN
OUT
=
........... (3)ESR.IVESR ⋅∆=
(V)
CF8I
VOUTOSC
COUT ⋅⋅ ∆
=∆........... (4)
(V) ESRI VOUT ⋅∆=∆........... (5)
Setting Output Voltage
The regulated output voltage is determined by:
(V) )
R
R
(10.8V2
1
OUT +×=
Suggested R2 is in the range from 1k to 20kΩ. For por-
table applications, a 10k resistor is suggested for R2. To
prevent stray pickup, please locate resistors R1 and R2
close to APW7142.
Input Capacitor Selection
Use small ceramic capacitors for high frequency
decoupling and bulk capacitors to supply the surge cur-
rent needed each time the P-channel power MOSFET (Q1)
turns on. Place the small ceramic capacitors physically
close to the VIN and between the VIN and the GND.
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and cur-
rent ratings above the maximum input voltage and larg-
est RMS current required by the circuit. The capacitor volt-
age rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times
is a conservative guideline. The RMS current (IRMS) of the
bulk input capacitor is calculated as the following equation:
where D is the duty cycle of the power MOSFET.
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tanta-
lum capacitors can be used, but caution must be exer-
cised with regard to the capacitor surge current rating.
Output Capacitor Selection
An output capacitor is required to filter the output and sup-
ply the load transient current. The filtering requirements
are the function of the switching frequency and the ripple
current (∆I). The output ripple is the sum of the voltages,
having phase shift, across the ESR, and the ideal output
capacitor. The peak-to-peak voltage of the ESR is calcu-
lated as the following equations:
(A)
D)-(1DI IOUTRMS ××=
The peak-to-peak voltage of the ideal output capacitor is
calculated as the following equations:
For the applications using bulk capacitors, the ∆VCOUT is
much smaller than the VESR and can be ignored. Therefore,
the AC peak-to-peak output voltage (∆VOUT ) is shown as
below:
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw16
Application Information (Cont.)
Output Capacitor Selection (Cont.)where
Inductor Value Calculation
........... (6)
IN(MAX)IN V V=
1.2
V· L · 500000 )V-(V · V
IN
OUTINOUT ≤
(H)
V· 600000 )V-(V · V
LIN
OUTINOUT
≥
For the applications using ceramic capacitors, the VESR is
much smaller than the ∆VCOUT and can be ignored.
Therefore, the AC peak-to-peak output voltage (∆VOUT ) is
close to ∆VCOUT .
The load transient requirements are the function of the
slew rate (di/dt) and the magnitude of the transient load
current. These requirements are generally met with a mix
of capacitors and careful layout. High frequency capaci-
tors initially supply the transient and slow the current load
rate seen by the bulk capacitors. The bulk filter capacitor
values are generally determined by the ESR (Effective
Series Resistance) and voltage rating requirements rather
than actual capacitance requirements.
High frequency decoupling capacitors should be placed
as close to the power pins of the load as physically
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
capacitor’s ESR value is related to the case size with lower
ESR available in larger case sizes. However, the Equiva-
lent Series Inductance (ESL) of these capacitors increases
with case size and can reduce the usefulness of the ca-
pacitor to the high slew-rate transient loading.
The operating frequency and inductor selection are inter-
related in that higher operating frequencies permit the
use of a smaller inductor for the same amount of inductor
ripple current. However, this is at the expense of efficiency
due to an increase in MOSFET gate charge losses. The
equation (2) shows that the inductance value has a direct
effect on ripple current.
Accepting larger values of ripple current allows the use of
low inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆I ≤ 0.4x IOUT(MAX) . Remember, the
maximum ripple current occurs at the maximum input
voltage. The minimum inductance of the inductor is cal-
culated by using the following equation:
Layout Consideration
In high power switching regulator, a correct layout is im-
portant to ensure proper operation of the regulator. In
general, interconnecting impedance should be minimized
by using short and wide printed circuit traces. Signal and
power grounds are to be kept separating and finally com-
bined using the ground plane construction or single point
grounding. Figure 2 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
lines should be placed close together. The following is a
checklist for your layout:
Firstly, to initial the layout by placing the power
components. Orient the power circuitry to achieve a
clean power flow path. If possible, make all the con-
nections on one side of the PCB with wide and copper
filled areas.
LX
EN
6
VIN
2
AGND
3
COMP
5
8
U1
APW7142
FB 4
C3
R3R1
LX 7
PGND 1
R2
L1
C2Load
+
VOUT
-
C1
+
VIN
-
Feedback
Divider
C4
(Optional)
Compensation
Network
In Figure 2, the loops with the same color bold lines
conduct high slew rate current. These interconnect-
ing impedances should be minimized by using wide
and short printed circuit traces.
Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX or others) on the PCB.
Therefore place the feedback divider and the feedback
compensation network close to the IC to avoid switch-
ing noise. Connect the ground of feedback divider di-
rectly to the AGND pin of the IC using a dedicated
ground trace.
1.
2.
3.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw17
Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. Use a wide power ground
plane to connect the C1 and C2 to provide a low im-
pedance path between the components for large and
high slew rate current.
Figure 3 Recommended Layout Diagram
C1
L1
C2
VOUT
VLX
SOP-8
APW7142
VIN
Ground
Ground
1
2
3
45
6
7
8
Application Information (Cont.)
4.
Layout Consideration (Cont.)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw18
Package Information
SOP-8
S
Y
M
B
O
LMIN. MAX.
1.75
0.10
0.17 0.25
0.25
A
A1
c
D
E
E1
e
h
L
MILLIMETERS
b0.31 0.51
SOP-8
0.25 0.50
0.40 1.27
MIN. MAX.
INCHES
0.069
0.004
0.012 0.020
0.007 0.010
0.010 0.020
0.016 0.050
0
0.010
1.27 BSC 0.050 BSC
A2 1.25 0.049
0
8
0
8
D
e
E
E1
SEE VIEW A
cb
h X 45
A
A1A2
L
VIEW A
0.25
SEATING PLANE
GAUGE PLANE
Note: 1. Follow JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
3.80
5.80
4.80
4.00
6.20
5.00 0.189 0.197
0.228 0.244
0.150 0.157
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw19
Application
A H T1 C d D W E1 F
330.0±
2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.5±
0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOP-8
4.0±
0.10
8.0±
0.10
2.0±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±
0.20
5.20±
0.20
2.10±
0.20
(mm)
Devices Per Unit
Carrier Tape & Reel Dimensions
Package Type Unit Quantity
SOP-8 Tape & Reel 2500
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw20
Taping Direction Information
SOP-8
USER DIRECTION OF FEED
Classification Profile
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw21
Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3 °C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
ESD MIL-STD-883-3015.7 VHBM≧2KV, VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2010
APW7142
www.anpec.com.tw22
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838