74LVC1G66 Bilateral switch Rev. 7 -- 30 July 2010 Product data sheet 1. General description The 74LVC1G66 provides one single pole, single-throw analog switch function. It has two input/output terminals (Y and Z) and an active HIGH enable input pin (E). When E is LOW, the analog switch is turned off. Schmitt-trigger action at the enable input makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Very low ON resistance: 7.5 (typical) at VCC = 2.7 V 6.5 (typical) at VCC = 3.3 V 6 (typical) at VCC = 5 V Switch current capability of 32 mA High noise immunity CMOS low power consumption TTL interface compatibility at 3.3 V Latch-up performance meets requirements of JESD78 Class I ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Enable input accepts voltages up to 5.5 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G66GW -40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74LVC1G66GV -40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753 74LVC1G66GM -40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 74LVC1G66 NXP Semiconductors Bilateral switch Table 1. Ordering information ...continued Type number Package Temperature range Name Description Version 74LVC1G66GF -40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 74LVC1G66GN -40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115 74LVC1G66GS -40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202 4. Marking Table 2. Marking Marking code[1] Type number 74LVC1G66GW VL 74LVC1G66GV V66 74LVC1G66GM VL 74LVC1G66GF VL 74LVC1G66GN VL 74LVC1G66GS VL [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 E Z 1 4 # Y 1 mna076 001aag487 Fig 1. Logic symbol 2 X1 Fig 2. IEC logic symbol Z Y E VCC Fig 3. 001aam397 Logic diagram 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 2 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 6. Pinning information 6.1 Pinning 74LVC1G66 74LVC1G66 Y 1 Z 2 GND 3 5 VCC Y 1 6 VCC Z 2 5 n.c. GND 4 E 4 E Y 1 6 VCC Z 2 5 n.c. GND 3 4 E 001aag499 001aag498 Transparent top view Transparent top view 001aad654 Fig 4. 3 74LVC1G66 Pin configuration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891 and SOT1115 and SOT1202 6.2 Pin description Table 3. Symbol Pin description Pin Description SOT353-1, SOT753 SOT886, SOT891, SOT1115 and SOT1202 Y 1 1 independent input or output Z 2 2 independent output or input GND 3 3 ground (0 V) E 4 4 enable input (active HIGH) n.c. - 5 not connected VCC 5 6 supply voltage 7. Functional description Table 4. Function table[1] Input E Switch L OFF-state H ON-state [1] H = HIGH voltage level; L = LOW voltage level 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 3 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions [1] VI input voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V ISK switch clamping current VI < -0.5 V or VI > VCC + 0.5 V [2] Min Max Unit -0.5 +6.5 V -0.5 +6.5 V -50 - mA - 50 mA -0.5 VCC + 0.5 V VSW switch voltage enable and disable mode ISW switch current VSW > -0.5 V or VSW < VCC + 0.5 V - 50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 C - 250 mW total power dissipation Ptot Tamb = -40 C to +125 C [3] [1] The minimum input voltage rating may be exceeded if the input current rating is observed. [2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed. [3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VSW Conditions [1] switch voltage Tamb ambient temperature t/V input transition rise and fall rate Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V 0 - VCC V -40 - +125 C VCC = 1.65 V to 2.7 V [2] - - 20 ns/V VCC = 2.7 V to 5.5 V [2] - - 10 ns/V [1] To avoid sinking GND current from terminal Z when switch current flows in terminal Y, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Y. In this case, there is no limit for the voltage drop across the switch. [2] Applies to control signal levels. 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 4 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter -40 C to +85 C Conditions Min HIGH-level input voltage VIH LOW-level input voltage VIL VCC = 1.65 V to 1.95 V Typ[1] -40 C to +125 C Unit Max Min Max 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V 0.35VCC V - - 0.3VCC - 0.3VCC V - 0.1 5 - 100 A II input leakage pin E; VI = 5.5 V or GND; current VCC = 0 V to 5.5 V [2] IS(OFF) OFF-state leakage current VCC = 5.5 V; see Figure 7 [2] - 0.1 5 - 200 A IS(ON) ON-state leakage current VCC = 5.5 V; see Figure 8 [2] - 0.1 5 - 200 A ICC supply current VI = 5.5 V or GND; VSW = GND or VCC; VCC = 1.65 V to 5.5 V [2] - 0.1 10 - 200 A ICC additional supply current pin E; VI = VCC - 0.6 V; VSW = GND or VCC; VCC = 5.5 V [2] - 5 500 - 5000 A CI input capacitance - 2.0 - - - pF CS(OFF) OFF-state capacitance - 6.5 - - - pF CS(ON) ON-state capacitance - 11 - - - pF [1] All typical values are measured at Tamb = 25 C. [2] These typical values are measured at VCC = 3.3 V. 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 5 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 10.1 Test circuits VCC VCC E VIL Z VI E VIH Y IS GND IS VO Z Y GND VI 001aam389 001aam390 VI = VCC or GND and VO = GND or VCC. Fig 7. VO VI = VCC or GND and VO = open circuit. Test circuit for measuring OFF-state leakage current Fig 8. Test circuit for measuring ON-state leakage current 10.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15. Symbol RON(peak) RON(rail) Parameter ON resistance (peak) ON resistance (rail) -40 C to +85 C Conditions -40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 4 mA; VCC = 1.65 V to 1.95 V - 34.0 130 - 195 VI = GND to VCC; see Figure 9 ISW = 8 mA; VCC = 2.3 V to 2.7 V - 12.0 30 - 45 ISW = 12 mA; VCC = 2.7 V - 10.4 25 - 38 ISW = 24 mA; VCC = 3.0 V to 3.6 V - 7.8 20 - 30 ISW = 32 mA; VCC = 4.5 V to 5.5 V - 6.2 15 - 23 ISW = 4 mA; VCC = 1.65 V to 1.95 V - 8.2 18 - 27 ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.1 16 - 24 VI = GND; see Figure 9 ISW = 12 mA; VCC = 2.7 V - 6.9 14 - 21 ISW = 24 mA; VCC = 3.0 V to 3.6 V - 6.5 12 - 18 ISW = 32 mA; VCC = 4.5 V to 5.5 V - 5.8 10 - 15 ISW = 4 mA; VCC = 1.65 V to 1.95 V - 10.4 30 - 45 ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.6 20 - 30 ISW = 12 mA; VCC = 2.7 V - 7.0 18 - 27 ISW = 24 mA; VCC = 3.0 V to 3.6 V - 6.1 15 - 23 ISW = 32 mA; VCC = 4.5 V to 5.5 V - 4.9 10 - 15 VI = VCC; see Figure 9 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 6 of 25 74LVC1G66 NXP Semiconductors Bilateral switch Table 8. ON resistance ...continued At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15. Symbol RON(flat) Parameter -40 C to +85 C Conditions ON resistance (flatness) -40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 4 mA; VCC = 1.65 V to 1.95 V - 26.0 - - - ISW = 8 mA; VCC = 2.3 V to 2.7 V - 5.0 - - - ISW = 12 mA; VCC = 2.7 V - 3.5 - - - ISW = 24 mA; VCC = 3.0 V to 3.6 V - 2.0 - - - ISW = 32 mA; VCC = 4.5 V to 5.5 V - 1.5 - - - [2] VI = GND to VCC [1] Typical values are measured at Tamb = 25 C and nominal VCC. [2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. 10.3 ON resistance test circuit and graphs mna673 40 RON () 30 VSW (1) 20 VCC E VIH (2) (3) Y 10 Z (4) VI GND (5) ISW 0 0 1 2 3 4 5 VI (V) 001aam391 RON = VSW/ISW. (1) VCC = 1.8 V. (2) VCC = 2.5 V. (3) VCC = 2.7 V. (4) VCC = 3.3 V. (5) VCC = 5.0 V. Fig 9. Test circuit for measuring ON resistance 74LVC1G66 Product data sheet Fig 10. Typical ON resistance as a function of input voltage; Tamb = 25 C All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 7 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 001aaa712 55 001aaa708 15 RON () RON () 45 13 35 11 (4) (3) (2) (1) (1) (2) 25 9 (3) (4) 15 7 5 5 0 0.4 0.8 1.2 1.6 2.0 0 0.5 1.0 1.5 2.0 VI (V) (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = -40 C. (4) Tamb = -40 C. Fig 11. ON resistance as a function of input voltage; VCC = 1.8 V 001aaa709 13 2.5 VI (V) Fig 12. ON resistance as a function of input voltage; VCC = 2.5 V 001aaa710 10 RON () RON () 11 8 (1) (1) 9 (2) (2) 6 (3) (3) 7 (4) (4) 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 VI (V) 0 1 (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = -40 C. (4) Tamb = -40 C. 74LVC1G66 Product data sheet 3 4 VI (V) (1) Tamb = 125 C. Fig 13. ON resistance as a function of input voltage; VCC = 2.7 V 2 Fig 14. ON resistance as a function of input voltage; VCC = 3.3 V All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 8 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 001aaa711 7 RON () 6 5 (1) (2) (3) 4 (4) 3 0 1 2 3 4 5 VI (V) (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C. Fig 15. ON resistance as a function of input voltage; VCC = 5.0 V 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18. Symbol Parameter tpd -40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V - 0.8 2.0 - 3.0 ns VCC = 2.3 V to 2.7 V - 0.4 1.2 - 2.0 ns VCC = 2.7 V - 0.4 1.0 - 1.5 ns VCC = 3.0 V to 3.6 V - 0.3 0.8 - 1.5 ns - 0.2 0.6 - 1.0 ns [2][3] propagation delay Y to Z or Z to Y; see Figure 16 VCC = 4.5 V to 5.5 V ten enable time 74LVC1G66 Product data sheet -40 C to +125 C Unit Typ[1] E to Y or Z; see Figure 17 [4] VCC = 1.65 V to 1.95 V 1.0 5.3 12 1.0 15.5 ns VCC = 2.3 V to 2.7 V 1.0 3.0 6.5 1.0 8.5 ns VCC = 2.7 V 1.0 2.6 6.0 1.0 8.0 ns VCC = 3.0 V to 3.6 V 1.0 2.5 5.0 1.0 6.5 ns VCC = 4.5 V to 5.5 V 1.0 1.9 4.2 1.0 5.5 ns All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 9 of 25 74LVC1G66 NXP Semiconductors Bilateral switch Table 9. Dynamic characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18. Symbol Parameter -40 C to +85 C Conditions Min tdis disable time -40 C to +125 C Unit Max Min Max [5] E to Y or Z; see Figure 17 VCC = 1.65 V to 1.95 V 1.0 4.2 10 1.0 13 ns VCC = 2.3 V to 2.7 V 1.0 2.4 6.9 1.0 9.0 ns VCC = 2.7 V 1.0 3.6 7.5 1.0 9.5 ns VCC = 3.0 V to 3.6 V 1.0 3.4 6.5 1.0 8.5 ns 1.0 2.5 5.0 1.0 6.5 ns VCC = 2.5 V - 9.8 - - - pF VCC = 3.3 V - 12.0 - - - pF VCC = 5.0 V - 17.3 - - - pF VCC = 4.5 V to 5.5 V power dissipation capacitance CPD Typ[1] [6] CL = 50 pF; fi = 10 MHz; VI = GND to VCC [1] Typical values are measured at Tamb = 25 C and nominal VCC. [2] tpd is the same as tPLH and tPHL [3] propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when driven by an ideal voltage source (zero output impedance). [4] ten is the same as tPZH and tPZL [5] tdis is the same as tPLZ and tPHZ [6] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + {(CL + CS(ON))x VCC2 x fo} where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; CS(ON) = maximum ON-state switch capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; {(CL + CS(ON)) x VCC2 x fo} = sum of the outputs. 11.1 Waveforms and test circuit VI VM Y or Z input GND t PLH t PHL VOH VM Z or Y output VOL mna667 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 16. Input (Y or Z) to output (Z or Y) propagation delays 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 10 of 25 74LVC1G66 NXP Semiconductors Bilateral switch VI E VM GND t PZL t PLZ VCC Y or Z output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ Y or Z output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND switch enabled switch disabled switch enabled mna668 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 17. Enable and disable times Table 10. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 1.95 V 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 4.5 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH - 0.3 V 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 11 of 25 74LVC1G66 NXP Semiconductors Bilateral switch VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 11. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = External voltage for measuring switching times. Fig 18. Test circuit for measuring switching times Table 11. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC 2.0 ns 30 pF 1 k open GND 2VCC 2.3 V to 2.7 V VCC 2.0 ns 30 pF 500 open GND 2VCC 2.7 V 2.7 V 2.5 ns 50 pF 500 open GND 6V 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open GND 6V 4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open GND 2VCC 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol Parameter Conditions THD total harmonic distortion RL = 10 k; CL = 50 pF; fi = 1 kHz; see Figure 19 Min Typ Max Unit VCC = 1.65 V - 0.032 - % VCC = 2.3 V - 0.008 - % VCC = 3.0 V - 0.006 - % VCC = 4.5 V - 0.001 - % VCC = 1.65 V - 0.068 - % VCC = 2.3 V - 0.009 - % VCC = 3.0 V - 0.008 - % VCC = 4.5 V - 0.006 - % RL = 10 k; CL = 50 pF; fi = 10 kHz; see Figure 19 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 12 of 25 74LVC1G66 NXP Semiconductors Bilateral switch Table 12. Additional dynamic characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol Parameter Conditions f(-3dB) -3 dB frequency response RL = 600 ; CL = 50 pF; see Figure 20 Min Typ Max Unit VCC = 1.65 V - 135 - MHz VCC = 2.3 V - 145 - MHz VCC = 3.0 V - 150 - MHz VCC = 4.5 V - 155 - MHz VCC = 1.65 V - > 500 - MHz VCC = 2.3 V - > 500 - MHz VCC = 3.0 V - > 500 - MHz VCC = 4.5 V - > 500 - MHz VCC = 1.65 V - 200 - MHz VCC = 2.3 V - 350 - MHz VCC = 3.0 V - 410 - MHz VCC = 4.5 V - 440 - MHz VCC = 1.65 V - -46 - dB VCC = 2.3 V - -46 - dB VCC = 3.0 V - -46 - dB VCC = 4.5 V - -46 - dB VCC = 1.65 V - -37 - dB VCC = 2.3 V - -37 - dB VCC = 3.0 V - -37 - dB VCC = 4.5 V - -37 - dB VCC = 1.65 V - 69 - mV VCC = 2.3 V - 87 - mV VCC = 3.0 V - 156 - mV VCC = 4.5 V - 302 - mV RL = 50 ; CL = 5 pF; see Figure 20 RL = 50 ; CL = 10 pF; see Figure 20 iso isolation (OFF-state) RL = 600 ; CL = 50 pF; fi = 1 MHz; see Figure 21 RL = 50 ; CL = 5 pF; fi = 1 MHz; see Figure 21 Vct crosstalk voltage 74LVC1G66 Product data sheet between digital input and switch; RL = 600 ; CL = 50 pF; fi = 1 MHz; tr = tf = 2 ns; see Figure 22 All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 13 of 25 74LVC1G66 NXP Semiconductors Bilateral switch Table 12. Additional dynamic characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol Parameter Conditions Qinj charge injection CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ; fi = 1 MHz; RL = 1 M; see Figure 23 Min Typ Max Unit VCC = 1.8 V - 3.3 - pC VCC = 2.5 V - 4.1 - pC VCC = 3.3 V - 5.0 - pC VCC = 4.5 V - 6.4 - pC VCC = 5.5 V - 7.5 - pC 11.3 Test circuits VCC 0.5VCC E VIH RL Y/Z 10 F Z/Y VO 600 fi D CL 001aam392 Test conditions: VCC = 1.65 V: Vi = 1.4 V (p-p). VCC = 2.3 V: Vi = 2 V (p-p). VCC = 3 V: Vi = 2.5 V (p-p). VCC = 4.5 V: Vi = 4 V (p-p). Fig 19. Test circuit for measuring total harmonic distortion VCC E VIH 0.1 F fi 0.5VCC Y/Z RL Z/Y 50 VO CL dB 001aam393 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads -3 dB. Fig 20. Test circuit for measuring the frequency response when switch is in ON-state 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 14 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 0.5VCC VCC E RL VIL 0.1 F 0.5VCC RL Y/Z Z/Y VO 50 fi CL dB 001aam394 Adjust fi voltage to obtain 0 dBm level at input. Fig 21. Test circuit for measuring isolation (OFF-state) VCC E Y/Z G logic input 50 Z/Y 600 VO RL 0.5VCC CL 0.5VCC 001aam395 Fig 22. Test circuit for measuring crosstalk between digital input and switch VCC E Rgen G logic input Y/Z Z/Y VO RL 1 M Vgen CL 0.1 nF 001aam396 logic input (E) off on off VO VO 001aam398 Qinj = VO x CL. VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. Fig 23. Test circuit for measuring charge injection 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 15 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 12. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7 0 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 24. Package outline SOT353-1 (TSSOP5) 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 16 of 25 74LVC1G66 NXP Semiconductors Bilateral switch Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT753 JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 25. Package outline SOT753 (SC-74A) 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 17 of 25 74LVC1G66 NXP Semiconductors Bilateral switch XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 26. Package outline SOT886 (XSON6) 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 18 of 25 74LVC1G66 NXP Semiconductors Bilateral switch XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4x (1) L L1 e 6 5 e1 4 e1 6x A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 27. Package outline SOT891 (XSON6) 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 19 of 25 74LVC1G66 NXP Semiconductors Bilateral switch XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4x)(2) L L1 e 6 5 4 e1 e1 (6x)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1115_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1115 Fig 28. Package outline SOT1115 (XSON6) 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 20 of 25 74LVC1G66 NXP Semiconductors Bilateral switch XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4x)(2) L L1 e 6 5 4 e1 e1 (6x)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1202_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1202 Fig 29. Package outline SOT1202 (XSON6) 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 21 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor TTL Transistor-Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model DUT Device Under Test 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G66 v.7 20100730 Product data sheet - 74LVC1G66 v.6 Modifications: * * Added type number 74LVC1G66GN (SOT1115/XSON6 package). Added type number 74LVC1G66GS (SOT1202/XSON6 package). 74LVC1G66 v.6 20070827 Product data sheet - 74LVC1G66 v.5 74LVC1G66 v.5 20070807 Product data sheet - 74LVC1G66 v.4 74LVC1G66 v.4 20040413 Product specification - 74LVC1G66 v.3 74LVC1G66 v.3 20021115 Product specification - 74LVC1G66 v.2 74LVC1G66 v.2 20020529 Product specification - 74LVC1G66 v.1 74LVC1G66 v.1 20011030 Product specification - - 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 22 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVC1G66 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 23 of 25 74LVC1G66 NXP Semiconductors Bilateral switch Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC1G66 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 30 July 2010 (c) NXP B.V. 2010. All rights reserved. 24 of 25 74LVC1G66 NXP Semiconductors Bilateral switch 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms and test circuit . . . . . . . . . . . . . . . 10 Additional dynamic characteristics . . . . . . . . . 12 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information. . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 July 2010 Document identifier: 74LVC1G66