© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6 1Publication Order Number:
MC33078/D
MC33078, MC33079
Low Noise Dual/Quad
Operational Amplifiers
The MC33078/9 series is a family of high quality monolithic
amplifiers employing Bipolar technology with innovative high
performance concepts for quality audio and data signal processing
applications. This family incorporates the use of high frequency PNP
input transistors to produce amplifiers exhibiting low input voltage
noise with high gain bandwidth product and slew rate. The all NPN
output stage exhibits no deadband crossover distortion, large output
voltage swing, excellent phase and gain margins, low open loop high
frequency output impedance and symmetrical source and sink AC
frequency performance.
The MC33078/9 family offers both dual and quad amplifier
versions and is available in the plastic DIP and SOIC packages (P and
D suffixes).
Features
•Dual Supply Operation: $5.0 V to $18 V
•Low Voltage Noise: 4.5 nV/ Hz
Ǹ
•Low Input Offset Voltage: 0.15 mV
•Low T.C. of Input Offset Voltage: 2.0 mV/°C
•Low Total Harmonic Distortion: 0.002%
•High Gain Bandwidth Product: 16 MHz
•High Slew Rate: 7.0 V/ms
•High Open Loop AC Gain: 800 @ 20 kHz
•Excellent Frequency Stability
•Large Output Voltage Swing: +14.1 V/ −14.6 V
•ESD Diodes Provided on the Inputs
•Pb−Free Packages are Available
Figure 1. Representative Schematic Diagram
(Each Amplifier)
VCC
D1 Q4 Q9
Q3 Q5 Pos D3
C2 R7 Q11
Neg
R2
Q8 D4 C3 R9
Q10
Q2 D2
Q6
R4
Q7 R5
R6
Q12
R3
C1
R1
Q1
Z1
J1 Amplifier
Biasing
VEE
Q3
Vout
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MARKING
DIAGRAMS
SOIC−14
D SUFFIX
CASE 751A
14
1
MC33079D
AWLYWW
1
14
1
4
1
PDIP−14
P SUFFIX
CASE 646
MC33079P
AWLYYWW
1
14
PDIP−8
P SUFFIX
CASE 626
1
8
SOIC−8
D SUFFIX
CASE 751
1
8
DUAL
QUAD
1
8
MC33078P
AWL
YYWW
33078
ALYW
G
1
8
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G= Pb−Free Package
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2
PIN CONNECTIONS
CASE 626/751
DUAL
(Dual, Top View)
4
VEE
1
2
3
5
6
7
8VCC
Output 2
Inputs 2
Inputs 1
−
+1
−
+
2
Output 1
CASE 646/751A
QUAD
)
*
)
*
*
)
*
)
(Quad, Top View)
1
2
3
4
5
6
7
14
8
9
10
11
12
13
Output 1
VCC
Output 4
Inputs 4
Output 2
VEE
Inputs 3
Output 3
14
23
Inputs 1
Inputs 2
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (VCC to VEE) VS+36 V
Input Differential Voltage Range VIDR Note 1 V
Input Voltage Range VIR Note 1 V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Maximum Junction Temperature TJ+150 °C
Storage Temperature Tstg −60 to +150 °C
ESD Protection at any Pin
MC33078 − Human Body Model
− Machine Model
MC33079 − Human Body Model
− Machine Model
Vesd 600
200
550
150
V
Maximum Power Dissipation PDNote 2 mW
Operating Temperature Range TA−40 to +85 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Either or both input voltages must not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).
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DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (RS = 10 W, VCM = 0 V, VO = 0 V)
(MC33078)TA = +25°C
TA = −40° to +85°C
(MC33079)TA = +25°C
TA = −40° to +85°C
|VIO|−
−
−
−
0.15
−
0.15
−
2.0
3.0
2.5
3.5
mV
Average Temperature Coefficient of Input Offset Voltage
RS = 10 W, VCM = 0 V, VO = 0 V, TA = Tlow to Thigh
DVIO/DT− 2.0 − mV/°C
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = −40° to +85°C
IIB −
−300
−750
800
nA
Input Offset Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = −40° to +85°C
IIO −
−25
−150
175
nA
Common Mode Input Voltage Range (DVIO = 5.0 mV, VO = 0 V) VICR ±13 ±14 − V
Large Signal Voltage Gain (VO = $10 V, RL = 2.0 kW)
TA = +25°C
TA = −40° to +85°C
AVOL 90
85 110
−−
−
dB
Output Voltage Swing (VID = $1.0V)
RL = 600 W
RL = 600 W
RL = 2.0 kW
RL = 2.0 kW
RL = 10 kW
RL = 10 kW
VO+
VO−
VO+
VO−
VO+
VO−
−
−
+13.2
−
+13.5
−
+10.7
−11.9
+13.8
−13.7
+14.1
−14.6
−
−
−
−13.2
−
−14
V
Common Mode Rejection (Vin = ±13V) CMR 80 100 − dB
Power Supply Rejection (Note 3)
VCC/VEE = +15 V/ −15 V to +5.0 V/ −5.0 V PSR 80 105 − dB
Output Short Circuit Current (VID = 1.0 V, Output to Ground)
Source
Sink
ISC +15
−20 +29
−37 −
−
mA
Power Supply Current (VO = 0 V, All Amplifiers)
(MC33078) TA = +25°C
(MC33078) TA = −40° to +85°C
(MC33079) TA = +25°C
(MC33079) TA = −40° to +85°C
ID−
−
−
−
4.1
−
8.4
−
5.0
5.5
10
11
mA
3. Measured with VCC and VEE differentially varied simultaneously.
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AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Slew Rate (Vin = −10 V to +10 V, RL = 2.0 kW, CL = 100 pF AV = +1.0) SR 5.0 7.0 − V/ms
Gain Bandwidth Product (f = 100 kHz) GBW 10 16 − MHz
Unity Gain Bandwidth (Open Loop) BW − 9.0 − MHz
Gain Margin (RL = 2.0 kW)
CL = 0 pF
CL = 100 pF
Am−
−−11
−6.0 −
−
dB
Phase Margin (RL = 2.0 kW)
CL = 0 pF
CL = 100 pF
fm−
−55
40 −
−
Deg
Channel Separation (f = 20 Hz to 20 kHz) CS − −120 − dB
Power Bandwidth (VO = 27 Vpp, RL = 2.0 kW, THD $ 1.0%) BWp− 120 − kHz
Total Harmonic Distortion
(RL = 2.0 kW, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0) THD − 0.002 − %
Open Loop Output Impedance (VO = 0 V, f = 9.0 MHz) |ZO| − 37 − W
Differential Input Resistance (VCM = 0 V) Rin − 175 − kW
Differential Input Capacitance (VCM = 0 V) Cin − 12 − pF
Equivalent Input Noise Voltage (RS = 100 W, f = 1.0 kHz) en− 4.5 − nV/ H
z
√
Equivalent Input Noise Current (f = 1.0 kHz) in− 0.5 − pA/Hz√
VCM = 0 V
TA = 25°C
Figure 2. Maximum Power Dissipation
versus Temperature Figure 3. Input Bias Current versus
Supply Voltage
Figure 4. Input Bias Current versus Temperature Figure 5. Input Offset Voltage versus Temperature
P, MAXIMUM POWER DISSIPATION (mW
)
D
−20 0 20 40 60 80 100 120 140 160
TA, AMBIENT TEMPERATURE (°C)
−55 −40
MC33078P & MC33079P
MC33079D
MC33078D
101520
VCC, | VEE |, SUPPLY VOLTAGE (V)
I, INPUT BIAS CURRENT (nA)
IB
TA, AMBIENT TEMPERATURE (°C)
0 25 50 75 100 125−55 −25
VCC = +15 V
VEE = −15 V
VCM = 0 V
V, INPUT OFFSET VOLTAGE (mV)
IO
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
Unit 1
Unit 2
Unit 3
VCC = +15 V
VEE = −15 V
RS = 10 W
VCM = 0 V
AV = +1
I, INPUT BIAS CURRENT (nA)
IB
2400
2000
1600
1200
800
400
0
800
600
400
200
0
1000
800
600
400
200
0
2.0
1.0
0
−1.0
−2.0
5.0
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5
Sink
Source
VCC = +15 V
VEE = −15 V
RL < 100 W
VID = 1.0 V
−55°C
25°C
VCC = +15 V
VEE = −15 V
125°C
−55°C
125°C
25°C
Figure 6. Input Bias Current versus
Common Mode Voltage Figure 7. Input Common Mode Voltage
Range versus Temperature
Figure 8. Output Saturation Voltage versus
Load Resistance to Ground Figure 9. Output Short Circuit Current
versus Temperature
Figure 10. Supply Current versus
Temperature Figure 11. Common Mode Rejection
versus Frequency
I, INPUT BIAS CURRENT (nA)
IB
−15 −10 −5.0 0 5.0 10 15
VCM, COMMON MODE VOLTAGE (V)
VCC = +15 V
VEE = −15 V
TA = 25°C
VICR
Voltage
Range
−VCM
−55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
+VCM VCC = +3.0 V to +15 V
VEE = −3.0 V to −15 V
DVIO = 5.0 mV
VO = 0 V
| I|, OUTPUT SHORT CIRCUIT CURRENT (mA)
SC
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
I, SUPPLY CURRENT (mA)
CC
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
±10 V
±15 V
±15 V
±10 V
±5.0 V
±5.0 V
VCM = 0 V
RL = ∞
VO = 0 V
MC33078
MC33079
Supply Voltages
CMR, COMMON MODE REJECTION (dB)
100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
VCC = +15 V
VEE = −15 V
VCM = 0 V
DVCM = ±1.5 V
TA = 25°C
, OUTPUT SATURATION VOLTAGE (V)
sat
RL, LOAD RESISTANCE TO GROUND (kW)
0 1.0 2.0 3.0 4.0
, INPUT COMMON MODE VOLTAGE RANGE (V)
V
600
500
400
300
200
100
0
VCC −0
VCC −0.5
VCC −1.0
VCC −1.5
VEE +1.5
VEE +1.0
VEE +0.5
VEE +0
50
30
20
10
40
10
8.0
6.0
4.0
2.0
0
160
140
120
100
80
60
40
20
VCC −1.0
VCC −3.0
VCC −5.0
VEE +5.0
VEE +3.0
VEE +1.0
CMR = 20Log
−
+
D VCM ADM
D VCM
D VO
× ADM
D VO
9.0
7.0
5.0
3.0
1.0
±4.0 V
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VO, OUTPUT VOLTAGE (V )
pp
RL = 2.0 kW
f ≤ 10 Hz
DVO = 2/3 (VCC −VEE)
TA = 25°C
RL = 10 kW
CL = 0 pF
f = 100 kHz
TA = 25°C
Figure 12. Power Supply Rejection
versus Frequency Figure 13. Gain Bandwidth Product
versus Supply Voltage
Figure 14. Gain Bandwidth Product
versus Temperature Figure 15. Maximum Output Voltage
versus Supply Voltage
Figure 16. Output Voltage versus Frequency Figure 17. Open Loop Voltage Gain
versus Supply Voltage
f, FREQUENCY (Hz)
P
S
R, P
O
WER
S
UPPLY REJE
C
TI
O
N
(
dB
)
100 1.0 k 10 k 100 k 1.0 M 10 M
+PSR
−PSR
VCC = +15 V
VEE = −15 V
TA = 25°C
VCC |VEE| , SUPPLY VOLTAGE (V)
GWB, GAIN BANDWIDTH PRODUCT (MHz)
0 101520
TA, AMBIENT TEMPERATURE (°C)
G
WB,
G
AIN BANDWIDTH PR
O
DU
C
T
(
MHz
)
−55 −25 0 50 75 10025 125
VCC = +15 V
VEE = −15 V
f = 100 kHz
RL = 10 kW
CL = 0 pF
VCC |VEE| , SUPPLY VOLTAGE (V)
V , OUTPUT VOLTAGE (Vp)
O
0101520
VO −
VO +
TA = 25°C
RL = 10 kW
RL = 10 kW
RL = 2.0 kW
RL = 2.0 kW
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 100 k 1.0 M 10 M
VCC = +15 V
VCC = −15 V
RL = 2.0 kW
AV = +1.0
THD ≤ 1.0%
TA = 25°C
VCC |VEE| , SUPPLY VOLTAGE (V)
VOL
A, OPEN LOOP VOLTAGE GAIN (dB)
0101520
140
120
100
80
60
40
20
0
30
20
10
0
20
15
10
5.0
0
20
15
10
5.0
0
−5.0
−10
−15
−20
35
30
25
20
15
10
5.0
0
110
100
90
80
+PSR = 20Log DVO/ADM
DVCC
ADM
−
+DVO
VEE
−PSR = 20Log DVO/ADM
DVCC
DVCC
5.0
5.0
5.0
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VOL
A, OPEN LOOP VOLTAGE GAIN (dB)
Figure 18. Open Loop Voltage Gain
versus Temperature Figure 19. Output Impedance
versus Frequency
Figure 20. Channel Separation
versus Frequency Figure 21. Total Harmonic Distortion
versus Frequency
Figure 22. Total Harmonic Distortion
versus Output Voltage Figure 23. Slew Rate versus Supply Voltage
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
f ≤ 10 Hz
DVO = −10 V to +10 V
f, FREQUENCY (Hz)
| Z|, OUTPUT IMPEDANCE ()Ω
1.0 k 10 k 100 k 1.0 M 10 M
O
VCC = +15 V
VEE = −15 V
VO = 0 V
TA = 25°C
AV = 1000 AV = 100 AV = 10 AV = 1.0
f, FREQUENCY (Hz)
CS, CHANNEL SEPARATION (dB)
CS = 20 Log DVOA
DVOM
10 100 1.0 k 100 k10 k
Drive Channel
VCC = +15 V
VEE = −15 V
RL = 2.0 KW
DVOD = 20 Vpp
TA = 25°C
MC33078
MC33079
f, FREQUENCY (Hz)
THD, TOTAL HARMONIC DISTORTION (%)
10 100 1.0 k 10 k 100 k
VCC = +15 V
VEE = −15 V
VO = 1.0 Vrms
TA = 25°C
VO, OUTPUT VOLTAGE (Vrms)
THD, TOTAL HARMONIC DISTORTION (%)
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
VCC = +15 V
VEE = −15 V
f = 2.0 kHz
TA = 25°C
AV = 1000
AV = 100
AV = 10
AV = 1.0
VCC |VEE| , SUPPLY VOLTAGE (V)
4121620
SR, SLEW RATE (V/ s)μ
Vin = 2/3 (VCC −VEE)
TA = 25°C
Rising
110
105
100
95
90
50
40
30
20
10
0
160
150
140
130
120
110
100
1.0
0.1
0.01
0.001
1.0
0.5
0.1
0.05
0.01
0.005
0.001
10
8.0
6.0
4.0
2.0
0
10 kW
VOM
Measurement Channel
−
+
100 W
100 W
VO
2.0 kW
+
−
DVin
VO
2.0
kW
−
+
RA
Vin 2.0 kW
VO
+
−10 kW
6 8 10 14 18
Falling
9.0
7.0
5.0
3.0
1.0
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25°C
−55 °C
125°C
VCC = +15 V
VEE = −15 V
DVin = 100 mV
DVin
VO
CL
−
+
VCC = +15 V
VEE = −15 V
VO = 0 V
Phase
Gain
125°C
−55°C25°C
25°C
−55°C
125°C
Vin
VO
CL
2.0 kW
−
+
Gain
Phase
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
TA = 25°C
Figure 24. Slew Rate versus Temperature Figure 25. Voltage Gain and Phase
versus Frequency
Figure 26. Open Loop Gain Margin and
Phase Margin versus Load Capacitance Figure 27. Overshoot versus Output
Load Capacitance
Figure 28. Input Referred Noise Voltage and
Current versus Frequency Figure 29. Total Input Referred Noise Voltage
versus Source Resistance
SR, SLEW RATE (V/s)μ
VCC = +15 V
VEE = −15 V
DVin = 20 V
TA, AMBIENT TEMPERATURE (°C)
Falling
Rising
−55 −25 0 25 50 75 100 125
f, FREQUENCY (Hz)
VOL
A, OPEN LOOP VOLTAGE GAIN (dB)
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
0
45
90
135
180
,
EXCESS PHASE
(
DEGREES
)
φ
A, OPEN LOOP GAIN MARGIN (dB)
m
1 10 100 1000
0
10
20
30
40
50
60
φ, PHASE MARGIN (DEGREES)
m
70
CL, OUTPUT LOAD CAPACITANCE (pF) CL, OUTPUT LOAD CAPACITANCE (pF)
10 100 1.0 k 10 k
os, OVERSHOOT (%)
10 100 1.0 k 10 k 100 k
10
0.1
f, FREQUENCY (Hz)
e, INPUT REFERRED NOISE VOLTAGE ()
nnV/ Hz√
VCC = +15 V
VEE = −15 V
TA = 25°C
Voltage
Current
pA/ Hz√
nV/ Hz√
RS, SOURCE RESISTANCE (W)
i
, REFERRED NOISE VOLTAGE (
n
VCC = +15 V
VEE = −15 V
f = 1.0 kHz
TA = 25°C
Vn(total) =
10 100 1.0 k 10 k 100 k 1.0 M
, INPUT REFERRED NOISE CURRENT ( )
n
V)
10
8.0
6.0
4.0
2.0
120
100
80
60
40
20
0
14
12
10
8.0
6.0
4.0
2.0
0
100
80
60
40
20
0
100
80
50
30
20
10
8.0
5.0
3.0
2.0
1.0
1000
100
10
1.0
DVin
VO
2.0
kW
−
+
(inRs)2)e
n2)4KTR
S
Ǹ
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+
−
Phase
Gain
R1
R2
VO
VCC = +15 V
VEE = −15 V
RT = R1 +R2
AV = +100
VO = 0 V
TA = 25°C
Figure 30. Phase Margin and Gain Margin versus
Differential Source Resistance
Figure 31. Inverting Amplifier Slew Rate Figure 32. Non−inverting Amplifier Slew Rate
Figure 33. Non−inverting Amplifier Overshoot Figure 34. Low Frequency Noise Voltage
versus Time
, PHASE MARGIN (DEGREES)
A , GAIN MARGIN (dB)
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
φm
10 100 1.0 k 10 k 100 k
VCC = +15 V
VEE = −15 V
AV = −1.0
RL = 2.0 kW
CL = 100 pF
TA = 25°C
V, OUTPUT VOLTAGE (5.0 V/DIV)
O
t, TIME (2.0 ms/DIV)
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 2.0 kW
CL = 100 pF
TA = 25°C
V, OUTPUT VOLTAGE (5.0 V/DIV)
O
t, TIME (2.0 ms/DIV)
VCC = +15 V
VEE = −15 V
RL = 2.0 kW
CL = 100 pF
AV = +1.0
TA = 25°C
V, OUTPUT VOLTAGE (5.0 V/DIV)
O
t, TIME (200 ms/DIV)
e, INPUT NOISE VOLTAGE (100 nV/DIV)
n
t, TIME (1.0 sec/DIV)
m
14
12
10
8.0
6.0
4.0
2.0
0
70
60
50
40
30
20
10
0
VCC = +15 V
VEE = −15 V
BW = 0.1 Hz to 10 Hz
TA = 25°C
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Figure 35. Voltage Noise Test Circuit
(0.1 Hz to 10 Hz
p−p
)
+
−
0.1 mF
10 W100 kW
2.0 kW
4.7 mF
Voltage Gain = 50,000
Scope
×1
Rin = 1.0 MW
1/2
MC33078
−
+
D.U.T.
100 kW
0.1 mF
2.2 mF
22 mF
24.3 kW
4.3 kW
110 kW
Note: All capacitors are non−polarized.
ORDERING INFORMATION
Device Package Shipping†
MC33078D SOIC−8 98 Units / Rail
MC33078DG SOIC−8
(Pb−Free)
MC33078DR2 SOIC−8 2500 Tape & Reel
MC33078DR2G SOIC−8
(Pb−Free)
MC33078P PDIP−8 50 Units / Rail
MC33078PG PDIP−8
(Pb−Free)
MC33079D SOIC−14 55 Units / Rail
MC33079DG SOIC−14
(Pb−Free)
MC33079DR2 SOIC−14 2500 Tape & Reel
MC33079DR2G SOIC−14
(Pb−Free)
MC33079P PDIP−14 25 Units / Rail
MC33079PG PDIP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 −A−
−B−
−T−
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M−−− 10 −−− 10
N0.76 1.01 0.030 0.040
__
MC33078, MC33079
http://onsemi.com
12
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AG
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SEATING
PLANE
1
4
58
N
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
AMIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024 1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
MC33078, MC33079
http://onsemi.com
13
PACKAGE DIMENSIONS
PDIP−14
N SUFFIX
CASE 646−06
ISSUE N
17
14 8
B
A
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 18.80
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M−−− 10 −−− 10
N0.015 0.039 0.38 1.01
__
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG DK
C
SEATING
PLANE
N
−T−
14 PL
M
0.13 (0.005)
L
M
J0.290 0.310 7.37 7.87
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
MC33078, MC33079
http://onsemi.com
14
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