®
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with
voltage regulator
Rev. 03 — 2 July 2012 Product data sheet
1. General description
The ADC1003S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital
Converters (ADC) for professional video and other applications. They convert the analog
input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz.
All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible,
although a low-level sine wave clock input signal is allowed.
The device includes an internal voltage reference regulator. If the application requires that
the reference is driven via external sources the recommendation is to use one of the
ADC1004S030/040/050 family.
2. Features
10-bit resolution
Sampling rate up to 50 MHz
DC sampling allowed
One clock cycle conversion only
High signal-to-noise ratio over a large analog input frequency range
(9.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz)
No missing codes guaranteed
In-Range (IR) CMOS output
Levels TTL and CMOS compatible digital inputs
3 V to 5 V CMOS digital outputs
Low-level AC clock input signal allowed
Internal reference voltage regulator
Power dissipation only 235 mW (typical)
Low analog input capacitance, no buffer amplifier required
No sample-and-hold circuit required
3. Applications
High-speed analog-to-digital conversion for:
Video data digitizing
Radar
Transient signal analysis
Global Positioning System (GPS) receiver
modulators
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 2 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
Cellular based stations
Barcode scanner
Medical imaging
4. Quick reference data
Table 1. Quick reference data
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0
C to 70
C;
typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25
C;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO output supply voltage 3.0 3.3 5.25 V
ICCA analog supply current -30 35 mA
ICCD digital supply current -16 21 mA
ICCO output supply current fclk = 40 MHz;
ramp input
- 12mA
INL integral non-linearity fclk = 40 MHz;
ramp input
-0.8 2.0 LSB
DNL differential non-linearity fclk = 40 MHz;
ramp input
-0.5 0.9 LSB
fclk(max) maximum clock
frequency
ADC1003S030TS 30 --MHz
ADC1003S040TS 40 --MHz
ADC1003S050TS 50 --MHz
Ptot total power dissipation fclk = 40 MHz;
ramp input
-235 305 mW
5. Ordering information
Table 2. Ordering information
Type number Package Sampling
frequency
(MHz)
Name Description Version
ADC1003S030TS SSOP28 plastic shrink small outline package; 28 leads;
body width 5.3 mm
SOT341-1 30
ADC1003S040TS SSOP28 plastic shrink small outline package; 28 leads;
body width 5.3 mm
SOT341-1 40
ADC1003S050TS SSOP28 plastic shrink small outline package; 28 leads;
body width 5.3 mm
SOT341-1 50
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 3 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
6. Block diagram
12
DGND2
6
8
Rlad
7
9
RB
RM
RT
VI
11
VCCD2
35
26
VCCA
21
22
23
24
20 D4
D5
D6
D7
D8
19
18
25
2
D3
D2
17 D1
16 D0
D9
IN-RANGE LATCH
CMOS
OUTPUTS
LATCHES
CLOCK DRIVER
REFERENCE
VOLTAGE
REGULATOR
014aaa321
1
CLKDEC
10
OE
TC
ADC1003S030/040/050
13 VCCO
4
AGND
analog ground digital ground digital ground
27
DGND1
14
OGND
output ground
analog
voltage input
data outputs
LSB
MSB
28 VCCD1
IR
output
CMOS OUTPUT
ANALOG - TO - DIGITAL
CONVERTER
Fig 1. Block diagram
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 4 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
7. Pinning information
7.1 Pinning
ADC1003S
050TS
CLK V
CCD1
TC DGND1
V
CCA
IR
AGND D9
DEC D8
RB D7
RM D6
VI D5
RT D4
OE D3
V
CCD2
D2
DGND2 D1
V
CCO
D0
OGND n.c.
014aaa320
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
Fig 2. Pin configuration
7.2 Pin description
Table 3. Pin description
Symbol Pin Description
CLK 1clock input
TC 2two’s complement input (active LOW)
VCCA 3analog supply voltage (5 V)
AGND 4analog ground
DEC 5decoupling input
RB 6reference voltage BOTTOM input
RM 7reference voltage MIDDLE
VI 8analog input voltage
RT 9reference voltage TOP input
OE 10 output enable input (CMOS level input, active LOW)
VCCD2 11 digital supply voltage 2 (5 V)
DGND2 12 digital ground 2
VCCO 13 supply voltage for output stages (3 V to 5 V)
OGND 14 output ground
n.c. 15 not connected
D0 16 data output; bit 0 (Least Significant Bit (LSB))
D1 17 data output; bit 1
D2 18 data output; bit 2
D3 19 data output; bit 3
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 5 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCCA analog supply voltage [1] 0.3 +7.0 V
VCCD digital supply voltage [1] 0.3 +7.0 V
VCCO output supply voltage staged [1] 0.3 +7.0 V
VCC supply voltage difference VCCA VCCD 1.0 +1.0 V
VCCA VCCO 1.0 +4.0 V
VCCD VCCO 1.0 +4.0 V
VI input voltage referenced to
AGND
0.3 +7.0 V
Vi(clk)(p-p) peak-to-peak clock input
voltage
referenced to
DGND
- VCCD V
IOoutput current -10 mA
Tstg storage temperature 55 +150 C
Tamb ambient temperature 40 +85 C
Tjjunction temperature - 150 C
[1] The supply voltages VCCA, VCCD and VCCO may have any value between 0.3 V and +7.0 V provided that
the supply voltage differences VCC are respected.
9. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction
to ambient
in free air 110 K/W
D4 20 data output; bit 4
D5 21 data output; bit 5
D6 22 data output; bit 6
D7 23 data output; bit 7
D8 24 data output; bit 8
D9 25 data output; bit 9 (Most Significant Bit (MSB))
IR 26 in-range data output
DGND1 27 digital ground 1
VCCD1 28 digital supply voltage 1 (5 V)
Table 3. Pin description …continued
Symbol Pin Description
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 6 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
10. Characteristics
Table 6. Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0
C to 70
C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO output supply voltage 3.0 3.3 5.25 V
VCC supply voltage difference VCCA VCCD 0.2 -+0.20 V
VCCA VCCO 0.2 -+2.25 V
VCCA VCCO 0.2 -+2.25 V
ICCA analog supply current -30 35 mA
ICCD digital supply current -16 21 mA
ICCO output supply current fclk = 40 MHz;
ramp input
- 12mA
Ptot total power dissipation fclk = 40 MHz;
ramp input
-235 305 mW
Inputs
Clock input CLK (referenced to DGND)[1]
VIL LOW-level input voltage 0 - 0.8 V
VIH HIGH-level input voltage 2 - VCCD V
IIL LOW-level input current Vclk = 0.8 V 1 0 +1 A
IIH HIGH-level input current Vclk = 2 V - 2 10 A
Ziinput impedance fclk = 40 MHz - 2 - k
Ciinput capacitance - 2 - pF
Inputs OE and TC (referenced to DGND)
VIL LOW-level input voltage 0 - 0.8 V
VIH HIGH-level input voltage 2 - VCCD V
IIL LOW-level input current VIL = 0.8 V 1--A
IIH HIGH-level input current VIH = 2 V - - 1 A
VI (Analog input voltage referenced to AGND)
IIL LOW-level input current VI = VRB = 1.3 V - 0 - A
IIH HIGH-level input current VI = VRT = 3.67 V -35 -A
Ziinput impedance fi = 4.43 MHz - 8 - k
Ciinput capacitance - 5 - pF
Reference voltages for the resistor ladder using the internal voltage regulator see Table 7
VRB voltage on pin RB 1.1 1.3 1.5 V
VRT voltage on pin RT 3.4 3.6 3.8 V
Vref(dif) differential reference
voltage
VRT VRB 2.25 2.3 2.35 V
Iref reference current -9.39 -mA
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 7 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
Rlad ladder resistance -245 -
TCRlad ladder resistor
temperature coefficient
-456 - m/K
Voffset offset voltage BOTTOM [2] -175 -mV
TOP [2] -175 -mV
Vi(a)(p-p) peak-to-peak analog input
voltage
[3] 1.90 1.95 2.00 V
Digital outputs D9 to D0 and IR (Referenced to OGND)
VOL LOW-level output voltage IOL = 1 mA 0 - 0.5 V
VOH HIGH-level output voltage IOH = 1 mA VCCO 0.5 - VCCO V
IOZ OFF-state output current 0.5 V < VO < VCCO 20 -+20 A
Switching characteristics; clock input CLK see Figure 4;[1]
fclk(max) maximum clock frequency ADC1003S030TS 30 --MHz
ADC1003S040TS 40 --MHz
ADC1003S050TS 50 --MHz
tw(clk)H HIGH clock pulse width full effective
bandwidth
8.5 --ns
tw(clk)L LOW clock pulse width full effective
bandwidth
5.5 --ns
Analog signal processing
Linearity
INL integral non-linearity fclk = 40 MHz;
ramp input
-0.8 2.0 LSB
DNL differential non-linearity fclk = 40 MHz;
ramp input
-0.5 0.9 LSB
Eoffset offset error middle code -1 - LSB
EGgain error from device to device,
using internal
reference voltage
[4] -3 - %
Bandwidth (fclk = 40 MHz)
Bbandwidth full-scale sine wave [5] -15 -MHz
75 % full-scale sine
wave
[5] -20 -MHz
small signal at
mid-scale;
VI = 10 LSB at
code 512
[5] -350 - MHz
ts(LH) LOW to HIGH settling time full-scale square
wave; see Figure 6
[6] -1.5 3.0 ns
ts(HL) HIGH to LOW settling time full-scale square
wave; see Figure 6
[6] -1.5 3.0 ns
Table 6. Characteristics …continued
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0
C to 70
C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 8 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
Harmonics (fclk = 40 MHz); see Figure 7 and Figure 8
1H first harmonic level fi = 4.43 MHz - - 0 dB
2H second harmonic level fi = 4.43 MHz -70 63 dB
3H third harmonic level fi = 4.43 MHz -72 63 dB
THD total harmonic distortion fi = 4.43 MHz -61 -dB
Signal-to-noise ratio; see Figure 7 and Figure 8[7]
S/N signal-to-noise ratio full-scale:
without harmonics;
fclk = 40 MHz;
fi = 4.43 MHz
55 58 -dB
Effective bits; see Figure 7 and Figure 8[7]
ENOB effective number of bits ADC1003S030TS; fclk = 30 MHz
fi = 4.43 MHz -9.4 bit
fi = 7.5 MHz -9.1 bit
ADC1003S040TS; fclk = 40 MHz;
fi = 4.43 MHz -9.3 -bit
fi = 7.5 MHz -9.0 -bit
fi = 10 MHz -8.9 -bit
fi = 15 MHz -8.1 -bit
ADC1003S050TS; fclk = 50 MHz
fi = 4.43 MHz -9.3 -bit
fi = 7.5 MHz -8.9 -bit
fi = 10 MHz -8.8 -bit
fi = 15 MHz -8.0 -bit
Two-tone[8]
IM intermodulation
suppression
fclk = 40 MHz -69 -dB
Bit error rate
BER bit error rate fclk = 50 MHz;
fi = 4.43 MHz;
VI = 16 LSB at code
512
-1013 -times/sample
Differential gain[9]
Gdif differential gain fclk = 40 MHz;
PAL modulated ramp
-0.8 - %
Table 6. Characteristics …continued
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0
C to 70
C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 9 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
[1] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less
than 0.5 ns
[2] Analog input voltages producing code 0 up to and including code 1023:
a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
(VRB) at Tamb = 25 C.
b) Voffset TOP is the difference between reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to
code 1023 at Tamb = 25 C.
[3] In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter
reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins RB and RT via offset resistors
ROB and ROT as shown in Figure 3.
a) The current flowing into the resistor ladder is
IL
VRT VRB
–
ROB RLROT
++
---------------------------------------
=
and the full-scale input range at the converter
to cover code 0 to code 1023, is
VIRLIL
RL
ROB RLROT
++
--------------------------------------- VRT VRB
–0.848 VRT VRB
–== =
b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio
RL
ROB RLROT
++
---------------------------------------
will
be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends
mainly on the difference VRT VRB and its variation with temperature and supply voltage. When several ADCs are connected in
parallel and fed with the same reference source, the matching between each of them is optimized.
[4]
EG
V1023 V0
–ViPP–
–
ViPP–
--------------------------------------------------------100=
[5] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 2 LSB, neither any significant attenuation are observed in the reconstructed signal.
[6] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
Differential phase[9]
dif differential phase fclk = 40 MHz;
PAL modulated ramp
-0.4 -deg
Timing (fclk = 40 MHz; CL = 15 pF); see Figure 4[10]
td(s) sampling delay time - 3 - ns
th(o) output hold time 4 - -ns
td(o) output delay time VCCO = 4.75 V -10 13 ns
VCCO = 3.15 V -12 15 ns
CLload capacitance - - 15 pF
3-state output delay times; see Figure 5
tdZH float to active HIGH delay
time
-5.5 8.5 ns
tdZL float to active LOW delay
time
-12 15 ns
tdHZ active HIGH to float delay
time
-19 24 ns
tdLZ active LOW to float delay
time
-12 15 ns
Table 6. Characteristics …continued
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0
C to 70
C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 10 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
[7] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to
signal-to-noise ratio: SINAD = ENOB 6.02 + 1.76 dB.
[8] Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have
the same amplitude and the total amplitude of both signals provides full-scale to the converter.
[9] Measurement carried out using video analyzer VM700A, where the video analog signal is reconstructed through a digital-to-analog
converter.
[10] Output data acquisition: the output data is available after the maximum delay time of td(o). For the 50 MHz version it is recommended to
have the lowest possible output load.
014aaa325
RT
RB
RM
Rlad
ROT
RL
RL
RL
RL
IL
ROB
code 1023
code 0
Fig 3. Explanation of Table 6 Table note 3
11. Additional information relating to Table 6
Table 7. Output coding and input voltage (typical values; referenced to AGND)
Code Vi(a)(p-p)
(V)
IR Binary outputs D9 to D0 Two’s complement
outputs D9 to D0
Underflow < 1.455 000 0000 0000 10 0000 0000
01.455 100 0000 0000 10 0000 0000
1 - 1 00 0000 0001 10 0000 0001
-
511 2.43 01 1111 1111 11 1111 1111
-
1022 -11 11 1111 1110 01 1111 1110
1023 3.405 111 1111 1111 01 1111 1111
Overflow > 3.405 011 1111 1111 01 1111 1111
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 11 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
Table 8. Mode selection
TC OE D9 to D0 IR
X 1 high impedance high impedance
0 0 active; two’s complement active
1 0 active; binary active
014aaa326
CLK
V
I
DATA
N − 2
DATA
D0 to D9 DATA
N − 1 DATA
NDATA
N + 1
sample N + 2sample N + 1
V
CCO
sample N
sample N + 2
sample N + 1sample N
t
w(clk)H
t
w(clk)L
t
d(s)
t
d(o)
t
h(o)
50%
0 V
V
CCO
50%
0 V
Fig 4. Timing diagram
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 12 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
LOW
HIGH
HIGH
LOW
ADC1003S050
VCCD
OE
OE
output
data
output
data
10 %
50 %
50 %
90 %
50 %
tdLZ tdZL
tdHZ tdZH
15 pF
3.3 kΩ
S1
TEST
VCCD
tdLZ
VCCD
tdZL
DGND
tdZH
tdHZ DGND
014aaa334
VCCD
S1
frequency on pin OE = 100 kHz
Fig 5. Timing diagram and test conditions of 3-state output delay time.
014aaa327
code 1023
code 0
50% 50%
CLK
VI
ts(LH) ts(HL)
50% 50%
2 ns 2 ns
0.5 ns 0.5 ns
Fig 6. Analog input settling-time diagram
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 13 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
014aaa328
−60
−100
−20
+20
amplitude
(dB)
−140
f (MHz)
0 20.015.05.00 10.0
(1) Effective bits: 9.42; THD = 71.8 dB
(2) Harmonic levels (dB): 2nd = 83.19; 3rd = 78.09; 4th = 78.72; 5th = 78.33; 6th = 77.55
Fig 7. Typical fast Fourier transform (fclk = 40 MHz; fi = 4.43 MHz)
0f (MHz)
20.0 25.015.05.0 10.0
014aaa329
−60
−100
−20
+20
amplitude
(dB)
−140
(1) Effective bits: 8.91; THD = 62.96 dB
(2) Harmonic levels (dB): 2nd = 71.38; 3rd = 71.54; 4th = 74.14; 5th = 65.15; 6th = 77.16
Fig 8. Typical fast Fourier transform (fclk = 50 MHz; fi = 10 MHz)
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 14 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
014aaa330
VCCO
D9 to D0
IR
OGND
V
CCA
V
I
AGND
014aaa332
Fig 9. CMOS data and in-range outputs Fig 10. Analog inputs
014aaa323
V
CCO
OGND
OE
TC
RM
RB
AGND
DEC
014aaa333
V
CCA
RT
REGULATOR
Rlad
Rlad
Rlad
Rlad
Fig 11. OE and TC input Fig 12. RB, RM and RT
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 15 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
VCCD
CLK 1.5 V
DGND
014aaa324
Fig 13. CLK input
12. Application information
12.1 Application diagram
ADC1003S050
CLK V
CCD1
TC DGND1
V
CCA
IR
AGND D9
DEC D8
RB
(1)
D7
RM
(1)
D6
VI D5
RT
(1)
D4
OE D3
V
CCD2
D2
DGND2 D1
V
CCO
D0
OGND n.c.
(2)
014aaa322
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
100 nF
4.7 nF
1 nF 1 nF
100 nF
100 nF
100 nF
100 nF
(3)
(3)
(3)
(3)
AGND
AGND
AGND
AGND
The analog and digital supplies should be separated and well decoupled.
A user manual is available that describes the demonstration board that uses the ADC1003S030/040/050 family in an
application environment.
(1) RB, RM and RT are decoupled to AGND.
(2) Pin 15 may be connected to DGND in order to prevent noise influence.
(3) Decoupling capacitor for supplies: must be placed close to the device.
Fig 14. Application diagram
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 16 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
12.2 Alternative parts
The following alternative parts are also available:
Table 9. Alternative parts
Type number Description Sampling frequency
ADC1004S030 Single 10 bits ADC [1] 30 MHz
ADC1004S040 Single 10 bits ADC [1] 40 MHz
ADC1004S050 Single 10 bits ADC [1] 50 MHz
ADC1005S060 Single 10 bits ADC [1] 60 MHz
ADC0804S030 Single 8 bits ADC [1] 30 MHz
ADC0804S040 Single 8 bits ADC [1] 40 MHz
ADC0804S050 Single 8 bits ADC [1] 50 MHz
[1] Pin to pin compatible
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 17 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
13. Package outline
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 10.4
10.0 5.4
5.2 0.65 1.25
7.9
7.6 0.9
0.7 1.1
0.7 8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT341-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
114
28 15
0.25
y
pin 1 index
0 2.5 5 mm
scale
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
A
max.
2
Fig 15. Package outline SOT341-1 (SSOP28)
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 18 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
14. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
ADC1003S030_040_050_3 20120702 Product data sheet -ADC1003S030_040_050_2
ADC1003S030_040_050_2 20080807 Product data sheet -ADC1003S030_040_050_1
Modifications: Corrections made to the values of V
•CC and the cross reference in subhead Reference
voltages for the resistor ladder in Table 6.
Corrections made to the table notes in Figure
• 14.
ADC1003S030_040_050_1 20080611 Product data sheet - -
15. Contact information
For more information or sales office addresses, please visit: http://www.idt.com
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 19 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
16. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
5 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Thermal characteristics . . . . . . . . . . . . . . . . . . 5
10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6
11 Additional information relating to Table 6 . . 10
12 Application information . . . . . . . . . . . . . . . . . 15
12.1 Application diagram . . . . . . . . . . . . . . . . . . . . 15
12.2 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 16
13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 17
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 18
15 Contact information . . . . . . . . . . . . . . . . . . . . 18
16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
