a
Circuit Design and Applications of the ADM663A/ADM666A
Micropower Linear Voltage Regulators
by Khy Vijeh, Matt Smith
AN-392
APPLICATION NOTE
ONE TECHNOLOGY WAY
•
P.O. BOX 9106
•
NORWOOD, MASSACHUSETTS 02062-9106
•
617/329-4700
GENERAL INFORMATION
The ADM663A/ADM666A contains a micropower band-
gap reference voltage source; an error amplifier, A1;
three comparators, C1, C2, C3, and a series pass output
transistor. A P-channel FET and an NPN transistor are
used on the ADM663A while the ADM666A uses an NPN
output transistor.
CIRCUIT DESCRIPTION
The internal bandgap reference is trimmed to 1.3 V
± 30 mV. This is used as a reference input to the error
amplifier A1. The feedback signal from the regulator out-
put is supplied to the other input by an on-chip voltage
divider or by two external resistors. When V SET is at
ground, the internal divider tap between R1 and R2, pro-
vides the error amplifier’s feedback signal giving a +5 V
output. When V SET is at VIN, the internal divider tap be-
tween R2 and R3 provides the error amplifier’s feedback
signal giving a +3.3 V output. When V SET is at more than
50 mV above ground and less than 50 mV below V IN, the
error amplifier’s input is switched directly to the V SET
pin, and external resistors are used to set the output
voltage. The external resistors are selected so that the
desired output voltage gives 1.3 V at V SET.
Comparator C1 monitors the output current via the
SENSE input. This input, referenced to V OUT(2), monitors
the voltage drop across a load sense resistor. If the volt-
age drop exceeds 0.5 V, then the error amplifier A1 is
disabled and the output current is limited.
The ADM663A has an additional amplifier, A2, which
provides a temperature proportional output, V TC. If this
is summed into the inverting input of the error amplifier,
a negative temperature coefficient results at the output.
This is useful when powering liquid crystal displays over
wide temperature ranges.
The ADM666A has an additional comparator, C4, that
compares the voltage on the low battery input, LBI, pin
to the internal +1.3 V reference. The output from the
comparator drives an open drain FET connected to the
low battery output pin, LBO. The low battery threshold
may be set using a suitable voltage divider connected to
LBI. When the voltage on LBI falls below 1.3 V, the open
drain output LBO is pulled low.
VIN 22k
C1
1.3V
A1 0.5V
VOUT2
VOUT1
C2 VIN–50mV
SENSE
C3
D
E
C
O
D
E
R
R1
R2
R3
50mV
A2
0.9V
ADM663A
VTC
GND
SHDN
VSET
Figure 1. ADM663A Functional Block Diagram
VIN
C1
1.3V
A1 0.5V
VOUT
C2 VIN–50mV
SENSE
C3
D
E
C
O
D
E
R
R1
R2
R3
50mV
C4
1.3V
ADM666A
LBI
LBO
GND
SHDN
VSET
Figure 2. ADM666A Functional Block Diagram
–2–
Both the ADM663A and the ADM666A contain a shut-
down (SHDN) input that can be used to disable the error
amplifier and hence the voltage output. The power con-
sumption in shutdown reduces to less than 9 µA.
Circuit Configurations
For a fixed +5 V output the V SET input is grounded and no
external resistors are necessary. This basic configura-
tion is shown in Figure 3. For a fixed +3.3 V output, the
VSET input is connected to V IN as shown in Figure 4. Cur-
rent limiting is not being utilized so the SENSE input is
connected to V OUT(2).
SENSE
VOUT2
VIN
VSET GND SHDN
ADM663A
ADM666A
+6V TO +16V
INPUT +5V
OUTPUT
0.1µF
0.1µF
Figure 3. A Fixed +5 V Output
SENSE
VOUT2
VIN
VSET GND SHDN
ADM663A
ADM666A
+4.5V TO +16V
INPUT +3.3V
OUTPUT
0.1µF
0.1µF
Figure 4. A Fixed +3.3 V Output
Output Voltage Setting
If VSET is not connected to GND or to V IN, the output volt-
age is set according to the following equation:
VOUT
=
VSET
×(
R
1+
R
2)
R
1
where V SET = 1.30 V.
The resistor values may be selected by first choosing a
value for R1 and then selecting R2 according to the fol-
lowing equation:
R
2=
R
1×
VOUT
1. 30 –1
The input leakage current on V SET is 10 nA maximum.
This allows large resistor values to be chosen for R1 and
R2 with little degradation in accuracy. For example, a
1 MΩ resistor may be selected for R1, and then R2 may
be calculated accordingly. The tolerance on V SET is guar-
anteed at less than ±30 mV so in most applications, fixed
resistors will be suitable.
SHDN
GND
ADM663A
ADM666A
+2V TO +16V
INPUT RCL
R2
R1
+1.3V TO +15V
OUTPUT
SENSE
VOUT2
VSET
VIN
Figure 5. Adjustable Output
Table I. Output Voltage Selection
V
SET
V
OUT
GND +5 V
VIN +3 V
R1/R2 ADJ
Current Limiting
Current limiting may be achieved by using an external
current sense resistor in series with V OUT(2). When the
voltage across the sense resistor exceeds the internal
0.5 V threshold, current limiting is activated. The sense
resistor is therefore chosen such that the voltage across
it will be 0.5 V when the desired current limit is reached.
RCL
=0.5
ICL
where R CL is the current sense resistor, I CL is the maxi-
mum current limit.
The value chosen for R CL should also ensure that the cur-
rent is limited to less than the 100 mA absolute maxi-
mum rating and also that the power dissipation will also
be within the package maximum ratings.
If current limiting is employed, there will be an addi-
tional voltage drop across the external sense resistor
that must be considered when determining the regula-
tors dropout voltage.
If current limiting is not used, the SENSE input should
be connected to V OUT(2). In this case, input current should
be limited so that in case of short circuited output,
device power dissipation does not exceed the rated
maximum.
Shutdown Input (SHDN)
The SHDN input allows the regulator to be turned off
with a logic level signal. This will disable the output and
reduce the current drain to a low quiescent (9 µA maxi-
mum) current. This is very useful for low power applica-
tions. The SHDN input should be driven with a CMOS
logic level signal since the input threshold is 0.3 V. In
TTL systems, an open collector driver with a pull-up re-
sistor may be used.
If the shutdown function is not being used, then it
should be connected to GND.
–3–
Low Supply or Low Battery Detection
The ADM666A contains on-chip circuitry for low power
supply or battery detection. If the voltage on the LBI pin
falls below the internal 1.3 V reference, then the open
drain output LBO will go low. The low threshold voltage
may be set to any voltage above 1.3 V by appropriate
resistor divider selection.
R
3=
R
4
V
BATT
1. 3
V
–1
where R3 and R4 are the resistive divider resistors and
VBATT is the desired low voltage threshold.
Since the LBI input leakage current is less than 10 nA,
large values may be selected for R3 and R4 in order to
minimize loading. For example, a 6 V low threshold may
be set using 10 M Ω for R3 and 2.7 M Ω for R4.
SENSE
VOUT
VSET
LBO
VIN
LBI
SHDNGND
ADM666A
+2V TO +16V
INPUT
RCL
R2
R1
+1.3V TO +15V
OUTPUT
LOW
BATTERY
OUTPUT
R3
R4
Figure 6. ADM666A Adjustable Output with Low
Battery Detection
Low Output Detection
The circuit in Figure 7 will generate a low LBO when out-
put voltage drops below a preset value determined by
the following equations:
R
2+
R
3=
R
1
V
OUT
1. 3 –1
R
3=(
R
1+
R
2)
V
OL
1. 3 –1
for VOUT = 5.0 V nominal, V OL = 3% of V OUT = 4.85 V and R1
= 1 MΩ solving the equations simultaneously we will get
R2 = 31 k Ω and R3 = 2.82 M Ω.
VOUT
SENSE
LBI
VSET
VIN
LBO
SHDN
GND
0.1µF 0.1µF
VOUT = 5V
R3
2.82MΩ
R2
31kΩ
R1
1MΩ
Figure 7. Voltage Regulator Circuit with Low Output
Detector
High Current Operation
The ADM663A contains an additional output, V OUT1, suit-
able for directly driving the base of an external NPN
transistor. Figure 8 shows a configuration which can be
used to provide +5 V with boosted current drive. A 1 Ω
current sensing resistor limits the current at 0.5 A.
V
OUT1
V
OUT2
SENSE
SHDN
V
SET
GND
ADM663A
V
IN
SHUTDOWN
+
V
IN
10µF 2N4237
100Ω1.0Ω
+5V, 0.5A
OUTPUT
10µF
+
Figure 8. ADM663A Boosted Output Current (0.5 A)
Temperature Proportional Output
The ADM663A contains a V TC output with a positive tem-
perature coefficient of +2.5 mV/ °C typ. This may be con-
nected to the summing junction of the error amplifier
(VSET) through a resistor resulting in a negative tempera-
ture coefficient at the output of the regulator. This is
especially useful in multiplexed LCD displays to com-
pensate for the inherent negative temperature coeffi-
cient of the LCD threshold. At +25 °C, the voltage at the
VTC output is typically 0.9 V. The equations for setting
both the output voltage and the tempco are given be-
low. If this function is not being used, then V TC should be
left unconnected.
VOUT
=
VSET
1+
R
2
R
1
+
R
2
R
3(
VSET
–
VTC
)
TCVOUT
=–
R
2
R
3(
TCVTC
)
where V SET = +1.3 V, V TC = +0.9 V, TCV TC = +2.5 mV/ °C
SENSE
VOUT2
VSET
VTC
ADM663A
VOUT
R2
R1R3
Figure 9. ADM663A Temperature Proportional Output
–4–
APPLICATION HINTS
Input-Output (Dropout Voltage)
A regulator’s minimum input-output differential or
dropout voltage determines the lowest input voltage for
a particular output voltage. The ADM663A/ADM666A
dropout voltage is 1 V at 100 mA output current. For
example when used as a fixed +5 V regulator, the mini-
mum input voltage is +6 V. At lower output currents
(IOUT < 10 mA) on the ADM663A, V OUT1 may be used as
the output driver in order to achieve lower dropout volt-
ages. In this case the dropout voltage depends on the
voltage drop across the internal FET transistor. This may
be calculated by multiplying the FET’s saturation resis-
tance by the output current, for example with V IN = 9 V,
RSAT = 20 Ω. Therefore, the dropout voltage for 5 mA is
100 mV. As the current limit circuitry is referenced to
VOUT2, VOUT2 should be connected to V OUT1. For high cur-
rent operation V OUT2 should be used alone and V OUT1 left
unconnected.
SENSE
VOUT2
VOUT1
VIN
VSET GND SHDN
ADM663A
+6V TO +16V
INPUT +5V
OUTPUT
Figure 10. Low Current, Low Dropout Configuration
Thermal Considerations
The ADM663A/ADM666A can supply up to 100 mA load
current and can operate with input voltages up to 16.5 V,
but the package power dissipation and hence the die
temperature must be kept within the maximum limits.
The package power dissipation is calculated from the
product of the voltage differential across the regulator
times the current being supplied to the load. The power
dissipation must be kept within the maximum limits
given in the Absolute Maximum Ratings section.
P
D
= (
V
IN
–V
OUT
)
(
I
L
)
The die temperature is dependent on both the ambient
temperature and on the power being dissipated by the
device. The ADM663A/ADM666A contains an internal
thermal limiting circuit which will shut down the regula-
tor if the internal die temperature exceeds 125 °C. There-
fore, care must be taken to ensure that, under normal
operating conditions, the die temperature is kept below
the thermal limit.
T
J
=
T
A
+ P
D
(θ
JA
)
This may be expressed in terms of power dissipation as
follows:
P
D
=
(
T
J
– T
A
)/(θ
JA
)
where:
T
J
= Die Junction Temperature ( °C)
T
A
= Ambient Temperature ( °C)
P
D
= Power Dissipation (W)
θ
JA
= Junction to Ambient Thermal Resistance ( °C/W)
If the device is being operated at the maximum permit-
ted ambient temperature of +85 °C, the maximum power
dissipation permitted is:
P
D
(
max
) = (
T
J
(
max
) –
T
A
)/(θ
JA
)
P
D
(
max
) = (125 – 85)/(θ
JA
)
= 40/θ
JA
θ
JA
= 120°C/W for the 8-pin DIP (N-8) package
θ
JA
= 170°C/W for the 8-pin SOIC (R-8) package
Therefore, for a maximum ambient temperature of 85 °C
P
D
(
max
) = 333
mW for N
-8
P
D
(
max
) = 235
mW for
R
-8
At lower ambient temperatures the maximum permitted
power dissipation increases accordingly up to the
maximum limits specified in the absolute maximum
specifications.
The thermal impedance ( θJA) figures given are mea-
sured in still air conditions and are reduced consider-
ably where fan assisted cooling is employed. Other
techniques for reducing the thermal impedance include
large contact pads on the printed circuit board and wide
traces. The copper will act as a heat exchanger thereby
reducing the effective thermal impedance.
High Power Dissipation Recommendations
Where excessive power dissipation due to high
input-output differential voltages and or high current
conditions exists, the simplest method of reducing the
power requirements on the regulator is to use a series
dropping resistor. In this way the excess power can be
dissipated in the external resistor. As an example, con-
sider an input voltage of +12 V and an output voltage
requirement of +5 V @ 100 mA with an ambient tem-
perature of +85 °C. The package power dissipation under
these conditions is 700 mW which exceeds the maxi-
mum ratings. By using a dropper resistor to drop 4 V,
the power dissipation requirement for the regulator is
reduced to 300 mW which is within the maximum speci-
fications for the N-8 package at +85 °C. The resistor value
is calculated as R = 4/0.1 = 40 Ω. A resistor power rating
of 400 mW or greater may be used.
Bypass Capacitors
The high frequency performance of the ADM663A/
ADM666A may be improved by decoupling the output
using a filter capacitor. A capacitor of 0.1 µF is suitable.
An input capacitor helps reduce noise, improves dy-
namic performance and reduces the input dV/dt at the
regulator input. A suitable input capacitor is 0.1 µF or
greater.
–5–
Typical Performance Characteristics
0.01 0.1 100001000100101
80
40
0
20
60
FREQUE NCY – Hz
PSRR – dB
VINDC = +9V
VIN p-p = +2V
VOUTDC = +5V
TA = +25°C
Figure 11. Power Supply Rejection Ratio vs. Frequency
2.0
020
0.6
0.2
2
0.4
0
1.2
0.8
1.0
1.4
1.6
1.8
1816141210864
IOUT1 – mA
(VIN – VOUT) – Volts
VIN = +2V TA = +25°C
VIN = +9V
VIN = +15V
Figure 12. ADM663A V
OUT1
Input-Output
Differential vs. Output Current
12
10
8
6
4
2
0
VIN – Volts
2 4 6 8 10 12 14 16
IIN – µA
TA = +25°C
VOUT = +5V
VOUT = +3.3V
Figure 13. Quiescent Current vs. Input Voltage
I
OUT
– mA
0 12020 40 60 80 100
V
IN
– V
OUT
– Volts
2.0
1.0
0.4
1.8
1.2
0.8
0.6
1.6
1.4
0.2
0.0
V
IN
= +2V V
IN
= +9V
V
IN
= +15V
T
A
= +25°C
663A/666A
Figure 14. ADM663 V
OUT2
, ADM666 Input-Output
Differential vs. Output Current
200µs
VIN = 9V
C2
VIN
10µF 80Ω
0-4V
SCOPE
50mV
C2 = 10µF
C2 = 1µF
Figure 15. Load Transient Response
2.0A LDO Voltage Regulator with Short Circuit Protection
In battery powered systems, battery life is significantly
affected by the voltage regulator’s dropout voltage.
These systems often require low dropout linear regula-
tors capable of high output current and extremely low
quiescent current.
The circuit in Figure 16 can source current in excess of
2 A with less than 400 mV dropout voltage and con-
sumes less than 10 µA in shutdown mode. The c ircuit
exhibits excellent line and load regulation and better
than 5% initial output voltage accuracy.
Unlike other LDO voltage regulators which require large
capacitors in excess of 10 µF for stability, a very small
0.1 µF bypass capacitor is sufficient for this circuit.
–6–
SHDN
GND SENSE
VOUT
VSET
VIN
ADM666A
VIN = 5.5
1µF +
–
R3
1kΩ
2N6111
Q1 R1
28kΩ
1%
0.1µF
5V @ 2A
R2
9.5kΩ
1%
R4
5Ω
5
8
6
2
41
Figure 16. 2.0A LDO Regulator
The circuit’s maximum current is determined by the
selection of the pass transistor’s current gain, ß, and its
maximum power dissipation. For low dropout voltage, a
viable choice is a PNP pass transistor with appropriate
power dissipation and ß. The s implified functional dia-
gram in Figure 17 helps clarify the circuit’s operation.
4
VIN R3
1kΩ
2N6111
Q1 R1
28kΩ0.1µF
VOUT
R2
9.5kΩ
86
21
1.3V Q2
R4
5Ω
ADM666
1µF
A1
Figure 17. Simplified Functional Diagram
The 2N6111 is in a servo loop with ADM666A’s voltage
reference, error amplifier and driver circuit.
To maintain regulation, output voltage is continuously
monitored by comparing the voltage on the set pin
(Pin 6) to a 1.3 V internal voltage reference. The differ-
ence is amplified by the error amplifier, A1, and used to
control the pass transistor’s base current, thus control-
ling its collector current. As output voltage changes due
to a change in input voltage or load current, the pass
transistor’s base current is adjusted to maintain a con-
stant output voltage.
Since maximum base current is limited to ADM666A’s,
short circuit current set by R4 to 100 mA, pass transis-
tors with higher ß will source higher currents to the
load. As a result, output short circuit current behavior of
the circuit depends on the pass transistor’s ß.
Another significant advantage of using a pass transistor
with high ß is to achieve higher efficiency since most of
the input current is diverted to the load and only a small
fraction of it is used to control the servo loop.
For high current applications where low dropout voltage
is not required, a power Darlington transistor can be
substituted to take advantage of its relatively high ß.
The trade-off of this approach is higher power dissipa-
tion due to Darlington’s high saturation voltage.
Output voltage is programmable between 1.3 V to 15.4 V
by selecting appropriate resistor values for the voltage
divider network using the following equation:
V
OUT
=1. 3
VR
1+
R
2
R
2
The circuit’s performance is shown in Figures 18 and 19.
VIN
4.900
VOUT
4.750
5.0 7.05.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8
5.000
4.950
4.850
4.800
5.050
0.0136
5.0036
4.990
RL = 2.05Ω
Figure 18. Output Voltage vs. Input Voltage
ILOAD – A
01.5
0.2 0.4 0.6 0.8 1.0
VOUT – VARIATION – mV
15
10
20
25
0
30
5
2.0 3.0
Figure 19. Output Voltage Variation vs. Load Current
The short circuit current is limited by limiting the pass
transistor’s base current, I b to a value determined by:
Ib
=0.5
R
4
The actual value of the short circuit current is deter-
mined by the ß of the pass transistor which in this case
is in 30 to 150 range at a collector current of 3.0 A dc.
For more accurate short circuit current control, the
circuit in Figure 20 is a simple way to add short circuit
protection.
–7–
SHDN
GND SENSE
V
OUT
V
SET
V
IN
ADM666
2kΩ
2N6111
R1
28kΩ0.1µF
R2
9.5kΩ
R4
5Ω
5
8
6
2
41
1N4728
3.3V, ZENER
50kΩ
750kΩ
850Ω
R
SC
= 0.05Ω
20Ω
2x
2N3906
1µF
Figure 20. External Short Circuit Protection
The short circuit current is determined by using the
following equation:
RSC
=0.1
ISC
An appropriate heat sink must be utilized to avoid dam-
age to the pass transistor as well as controller IC. Figure
21 is a plot of the current through the controller and volt-
age across it vs. input voltage at a constant load current.
As the curve indicates, maximum power dissipation for
controller occurs when input voltage is between 5.4 V to
5.6 V, worst case being 215 mW at V IN = 5.53 V, which is
well within the product specification.
V
IN
110
90
5.0 7.05.2 5.4 5.6 5.8 6.0
130
50
30
70
10
I
B
mA
4.8
4.6
5.0
4.2
4.0
4.4
3.8
VOLTAGE ACROSS PINS 8 AND 2
215 mW
I
B
V
8–2
R
L
= 2.05Ω
ADM666
I
V
8
5Ω
2
V
IN
Figure 21. Controller IC Power Dissipation
However, the pass transistor requires adequate heat
sink specially if it were to operate with large input output
voltage differential.
LDO Regulator with Battery Crossover Switch
The circuit in Figure 22 automatically connects the
standby battery to the circuit when primary voltage
source is disconnected or drops below a preset voltage
level.
Battery ON voltage level is determined using the follow-
ing equation:
R
1=
R
2(
V
BAT
)
1. 3
V
–1
An N-channel power FET switch with very low R ON is
used to achieve a very low dropout across the switch
when it is ON.
Optional resistor R3 is used to compensate for constant
losses by self-discharge or trickle charging of the bat-
tery. Consult the battery specification to determine
trickle charge current and maximum permissible over
charge current.
Resistor values used in this circuit are optimized for low
power operation, when monitoring BAT-ON output;
avoid excessive loads on this output.
Shut-down pin should be tied to ground if it is not used.
ADM666A
VIN
VSET
LBO
LBI
GND SHDN
SENSE
VOUT
100kΩ
D1
VP12A
6V
4 5
2
1
3.3V
100mA
0.1µF
8
6
SHUTDOWN
50kΩ
150kΩ
BAT ON
R2
2.5MΩ
R1
7.31MΩ
1µF
7
3
R3
Figure 22. LDO Regulator with Battery Crossover
Switch Circuit
Low Battery Disconnect Circuit
To prevent damage to the battery and loss of data due to
battery over-discharge, the circuit illustrated in Figure
23 monitors the battery voltage and disconnects the bat-
tery from the circuit when it drops below a preset value.
ADM666A
VIN
VSET
LBI
SHDN
SENSE
VOUT 2
1
0.1µF
D1
*
D2
*
D3
R6
10Ω
MEMORY
V+
MAIN
V+
8
6
3
5
7
2N2222
R4
2MΩ
R5
9.1MΩ
R3
600kΩ
R1
6.54MΩ
R2
2.5MΩ
6V
6V SEALED LEAD-ACID
BATTERY SOURCE
FOR BEST TEMPERATURE TRACKING PERFORMANCE,
DIODES MUST BE IN THERMAL CONTACT.
*
1µF
+
LBO
LBO
Figure 23. Low Battery Disconnect and Memory
Backup Circuit
Diode D2 is added for isolation; D1 is to compensate for
voltage drop across D2. For better output voltage accu-
racy performance, diodes D1 and D2 must be in thermal
contact. Surface mount Schottky diodes mounted in
close proximity of each other offer the best temperature
tracking performance.
–8–
In battery disconnect mode, the circuit’s quiescent cur-
rent is less than 20 µA. If LBO function is not needed or it
is monitored via a high impedance input, the circuit’s
current consumption can be reduced significantly by re-
placing R4 with a short and R3 with a 9 M Ω resistor. This
circuit has less than 10 µA quiescent current.
5 Volt Supply with Battery Backup and Battery ON Lag
The circuit in Figure 24 switches to NiCd backup battery
when the main input voltage drops below value set by
R1, R2 and R3 and returns to the main input when its
voltage reaches the preset value set by R3.
ADM666A
VIN
VSET
LBO
LBI
SHDN
SENSE
VOUT 2
1
0.1µF
8
6
3
5
7
R1
MAIN 5V
MEMORY 5V
LOW BATTERY
FLAG
R2
+
1µF
SHOULD BE
CONNECTED
TO GND
IF NOT USED
GND
4
R3
HYST ADJ
100kΩ
51kΩ
150kΩ+
–
5V NICD
BACKUP
VP12A
Figure 24. 5 V Battery Powered Supply with Backup
and Battery ON Flag
The Battery ON flag goes low whenever the circuit is
switched to NiCd battery.
Low Cost Battery Charger Circuits
A simple, low cost and yet flexible battery charger is pre-
sented in Figure 25. Maximum output voltage is pro-
grammed by selection of R1 and R2 ratio’s using
R
1=
R
2
(V
OUT
)
1
.
3
V–
1
for VOUT = 7.8 V, R1 = 2.82 M Ω, and R2 = 560 k Ω. Maxi-
mum charge current is determined by the current limit-
ing resistor which in this case is 100 mA set by R8.
V
IN
V
SET
LBO
LBI
SHDN
SENSE
V
OUT
2
1
0.1µF
6
3
5
7
GND
4
R1 2.82MΩ
R3
R2 560kΩ
R5
2MΩ
R6
20kΩ
R8 5Ω
R4
9.2MΩ
8
V
IN
= 9V
1µF
+
R7
3k
270kΩ
5
CELLS
ADM666A
Figure 25. Low Cost Battery Charger
Charge termination voltage, V T, and charge resume volt-
age, V CH, are set by R3, R4 and R5. Charging is termi-
nated when battery voltage reaches V T.
Charge termination voltage, which in this case is 7.2 V,
is calculated using the following equation:
R
4=(
R
5+
R
6)
VT
1. 3 –1
where R6 = 20 k Ω, and R4 = 9.2 M Ω.
ADM666A continues to monitor the battery voltage
level; charging will resume when it drops below the V CH.
The VCH level is set by adjusting R3.
With resistor values selected in Figure 26, charging
starts when the battery voltage is around V CH = 5 volts
and will terminate when the battery voltage reaches
slightly above 7.2 V.
Charger status is indicated by the LED. A lighted LED
indicates charger ON; a flashing LED indicates battery
disconnect.
To minimize calculation errors and maximize the circuit
efficiency, LED current should be limited to about 2 mA.
To minimize current drain by battery voltage monitoring
circuit’s, large resistor values are selected for R4 and R5
(see text for recommended values).
Charge current is limited to 100 mA by a short circuit
current limiting resistor. However higher charge current
is possible using the circuit in Figure 26.
V
IN
22k
C1
1.3V
A1 0.5V
V
OUT2
V
OUT1
C2 V
IN
–50mV
SENSE
C3
D
E
C
O
D
E
R
R1
R2
R3
50mV
A2
0.9V
ADM663A
V
TC
GND
SHDN
V
SET
Figure 26. High Charge Current Battery Charger
Power PNP pass transistor with appropriate current rat-
ing is controlled by the ADM666A.
Available charge current is determined by the
transistor’s power rating, its current gain, ß, and con-
trolled by the short circuit current limit resistor.
E2032–12–5/95
PRINTED IN U.S.A.
