WF2M32-XXX5 HI-RELIABILITY PRODUCT 2Mx32 5V FLASH MODULE, SMD 5962-97531 (pending) PRELIMINARY* FEATURES Access Time of 90, 120, 150ns Packaging: * 66 pin, PGA Type, 1.185" square, Hermetic Ceramic HIP (Package 401). * 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square (Package 510) 3.56mm (0.140") height. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3) Sector Architecture * 32 equal size sectors of 64KBytes per each 2Mx8 chip * Any combination of sectors can be erased. Also supports full chip erase. Minimum 100,000 Write/Erase Cycles Minimum Organized as 2Mx32 RESET pin resets internal state machine to the read mode. Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation, Separate Power and Ground Planes to improve noise immunity Commercial, Industrial, and Military Temperature Ranges 5 Volt Read and Write. 5V 10% Supply. Low Power CMOS Data Polling and Toggle Bit feature for detection of program or erase cycle completion. Supports reading or programming data to a sector not being erased. * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. Note: For programming information refer to Flash Programming 16M5 Application Note. FIG. 1 PIN CONFIGURATION FOR WF2M32-XHX5 PIN DESCRIPTION TOP VIEW 1 12 23 34 45 Data Inputs/Outputs A0-20 Address Inputs I/O8 WE2 I/O15 I/O24 VCC I/O31 WE1-4 Write Enables I/O9 CS2 I/O14 I/O25 CS4 I/O30 CS1-4 Chip Selects OE Output Enable VCC Power Supply GND Ground I/O10 GND I/O13 I/O26 WE4 I/O29 A14 I/O11 I/O12 A7 I/O27 I/O28 A16 A10 OE A12 A4 A1 A11 A9 A17 A20 A5 A2 BLOCK DIAGRAM W E1 CS1 A0 A15 WE1 A13 A6 A3 A18 VCC I/O7 A8 WE3 I/O23 I/O0 CS1 I/O6 I/O16 CS3 I/O22 I/O1 A19 I/O5 I/O17 GND I/O21 I/O2 I/O3 I/O4 I/O18 I/O19 I/O20 22 33 44 55 W E2 CS2 W E3 CS3 W E4 CS4 OE A0-20 2M x 8 8 11 I/O0-31 56 I/O0-7 66 2M x 8 8 I/O8-15 2M x 8 8 I/O16-23 2M x 8 8 I/O24-31 RESET internally tied to Vcc in the HIP package for this pin configuration. See Alternate Pin Configuration with RESET tied to pin 12 for system control of reset (Fig. 10, page 11) October 1999 Rev.3 1 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WF2M32-XXX5 FIG. 2 PIN CONFIGURATION FOR WF2M32-XG2UX5 PIN DESCRIPTION RESET A0 A1 A2 A3 A4 A5 CS3 GND CS4 WE1 A6 A7 A8 A9 A10 VCC TOP VIEW I/O0-31 Data Inputs/Outputs 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 The White 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form. Write Enables CS1-4 Chip Selects OE Output Enable VCC Power Supply GND Ground RESET Reset BLOCK DIAGRAM WE 1 CS 1 WE 2 CS 2 WE 4 CS 4 WE 3 CS 3 RESET OE A0-20 A18 A19 A20 WE4 OE CS2 A17 WE2 WE3 A15 A16 CS1 A14 A13 A12 A11 VCC Address Inputs 0.940" 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 2M x 8 8 I/O0-7 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 A0-20 WE1-4 2 2M x 8 8 I/O8-15 2M x 8 8 I/O16-23 2M x 8 8 I/O24-31 WF2M32-XXX5 ABSOLUTE MAXIMUM RATINGS Parameter CAPACITANCE (T A = +25C) Symbol Ratings Unit VT -2.0 to +7.0 V Voltage on Any Pin Relative to VSS Power Dissipation PT Storage Temperature Short Circuit Output Current Endurance - Write/Erase Cycles (Mil Temp) Data Retention (Mil Temp) 8 Parameter W Tstg -65 to +125 C IOS 100 100,000 min mA cycles 20 years RECOMMENDED DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage V CC 4.5 5.0 5.5 V Ground V SS 0 0 0 V Input High Voltage V IH 2.0 - V CC + 0.5 V Input Low Voltage V IL -0.5 - +0.8 V Operating Temperature (Mil.) TA -55 - +125 C Operating Temperature (Ind.) TA -40 - +85 C Symbol Conditions OE capacitance COE VIN = 0 V, f = 1.0 MHz Max Unit WE1-4 capacitance HIP (PGA) HIP (Alternate pinout) CQFP G4T CQFP G2U G2 (Alternate pinout) CWE VIN = 0 V, f = 1.0 MHz 50 pF pF 20 50 50 20 50 CS1-4 capacitance CCS VIN = 0 V, f = 1.0 MHz 20 pF Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 20 pF Address input capacitance CAD VIN = 0 V, f = 1.0 MHz 50 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS - CMOS COMPATIBLE (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) Parameter Symbol Conditions Min Max Unit I LI V CC = 5.5, V IN = GND to VCC 10 A I LOx32 V CC = 5.5, V IN = GND to VCC 10 A VCC Active Current for Read (1) ICC1 CS = VIL, OE = VIH, f = 5MHz 160 mA V CC Active Current for Program or Erase (2) I CC2 CS = VIL, OE = VIH 240 mA V CC Standby Current I CC3 V CC = 5.5, CS = V IH , f = 5MHz, RESET = Vcc 0.3V 8.0 mA Output Low Voltage V OL I OL = 12.0 mA, V CC = 4.5 Output High Voltage V OH I OH = -2.5 mA, V CC = 4.5 Low V CC Lock-Out Voltage V LKO Input Leakage Current Output Leakage Current 0.45 0.85xVcc 3.2 V V 4.2 V NOTES: 1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH. 2. Icc active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V 3 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WF2M32-XXX5 AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED (VCC = 5.0V, TA = -55C to +125C) Parameter Symbol -90 Min -120 Max Min -150 Max Min Unit Max Write Cycle Time tAVAV tWC 90 120 150 Chip Select Setup Time tELWL tCS 0 0 0 ns Write Enable Pulse Width tWLWH tWP 45 50 50 ns Address Setup Time tAVWL tAS 0 0 0 ns Data Setup Time tDVWH tDS 45 50 50 ns Data Hold Time tWHDX tDH 0 0 0 ns Address Hold Time tWLAX tAH 45 50 50 ns Write Enable Pulse Width High tWHWL tWPH 20 Duration of Byte Programming Operation (1) tWHWH1 300 300 300 s Sector Erase (2) tWHWH2 15 15 15 sec Read Recovery Time before Write tGHWL 0 0 0 V CC Setup Time t VCS 50 50 50 20 Chip Programming Time 20 44 Chip Erase Time (3) ns ns s s 44 256 256 44 sec 256 sec Output Enable Hold Time (4) tOEH 10 10 10 ns RESET Pulse Width (5) tRP 500 500 500 ns NOTES: 1. Typical value for t WHWH1 is 7s. 2. Typical value for t WHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. 5. RESET internally tied to Vcc for the default pin configuration in the HIP package. AC CHARACTERISTICS - READ-ONLY OPERATIONS (VCC = 5.0V, TA = -55C to +125C) Parameter Symbol -90 Min -120 Max 90 Min -150 Max 120 Min Unit Max Read Cycle Time t AVAV t RC Address Access Time t AVQV t ACC 90 120 150 150 ns Chip Select Access Time t ELQV t CE 90 120 150 ns Output Enable to Output Valid t GLQV t OE 40 50 55 ns ns Chip Select High to Output High Z (1) t EHQZ t DF 20 30 35 ns Output Enable High to Output High Z (1) t GHQZ t DF 20 30 35 ns Output Hold from Addresses, CS or OE Change, whichever is First t AXQX t OH RST Low to Read Mode (1,2) 0 t Ready 20 1. Guaranteed by design, not tested. 2. RESET internally tied to Vcc for the default pin configuration in the HIP package. White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 0 4 0 20 ns 20 s WF2M32-XXX5 AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) Parameter Symbol -90 Min -120 Max Min -150 Max Min Unit Max Write Cycle Time t AVAV t WC 90 120 150 Write Enable Setup Time t WLEL t WS 0 0 0 ns Chip Select Pulse Width t ELEH t CP 45 50 50 ns Address Setup Time t AVEL t AS 0 0 0 ns Data Setup Time t DVEH t DS 45 50 50 ns Data Hold Time t EHDX t DH 0 0 0 ns Address Hold Time t ELAX t AH 45 50 50 ns t EHEL t CPH 20 Chip Select Pulse Width High 20 ns 20 ns Duration of Byte Programming Operation (1) t WHWH1 300 300 300 s Sector Erase Time (2) t WHWH2 15 15 15 sec Read Recovery Time t GHEL 44 sec 256 sec 0 0 Chip Programming Time 44 Chip Erase Time (3) 256 Output Enable Hold Time (4) 256 10 tOEH s 0 44 10 10 ns NOTES: 1. Typical value for t WHWH1 is 7s. 2. Typical value for t WHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. FIG. 3 AC TEST CONDITIONS AC TEST CIRCUIT Parameter I OL Current Source VZ D.U.T. 1.5V (Bipolar Supply) C eff = 50 pf CS I OH Current Source The Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . V Z is typically the midpoint of VOH and V OL. I OL & IOH are adjusted to simulate a typical resistive load circuit. rising edgeincludes of the last WE signal ATE tester jig capacitance. WE Entire programming or erase operations FIG. 4 RESET TIMING DIAGRAM RY/BY tBUSY RESET tRP tReady 5 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WF2M32-XXX5 FIG. 5 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 6 Outputs WE OE CS Addresses High Z tACC tCE tOE Addresses Stable tRC Output Valid tOH tDF High Z AC WAVEFORMS FOR READ OPERATIONS WF2M32-XXX5 A0H tDH tWPH Data tDS tCS WE OE 5.0 V tWP tGHWL tWC CS Addresses 5555H tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT tOE tCE tRC tDF WRITE/ERASE/PROGRAM OPERATION, WE CONTROLLED tOH FIG. 6 NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to each chip. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 7 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WF2M32-XXX5 FIG. 7 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 AAH tDS tDH 8 VCC tVCS NOTE: 1. SA is the sector address for Sector Erase. Data WE OE CS Addresses tGHWL tCS tWP tAS tWPH 55H 2AAAH 5555H tAH 5555H 80H 5555H AAH 2AAAH 55H SA 10H/30H AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS WF2M32-XXX5 FIG. 8 9 D0-D6 Data WE OE CS D7 t CH tOEH tCE t OE tWHWH 1 or 2 D7 D0-D6 = Invalid D7 = Valid Data D0-D7 Valid Data t OH t DF High Z AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WF2M32-XXX5 FIG. 9 A0H NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to each chip. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 tDH tCPH 10 5.0 V tDS Data CS OE WE tWS tWC Addresses 5555H tGHEL tCP tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT ALTERNATE CS CONTROLLED PROGRAMMING OPERATION TIMINGS WF2M32-XXX5 FIG. 10 ALTERNATE PIN CONFIGURATION FOR WF2M32I-XHX5 PIN DESCRIPTION TOP VIEW 1 12 23 34 45 Data Inputs/Outputs A0-20 Address Inputs I/O8 RESET I/O15 I/O24 VCC I/O31 WE Write Enable I/O9 CS2 I/O14 I/O25 CS4 I/O30 CS1-4 Chip Selects OE Output Enable VCC Power Supply I/O10 GND I/O13 I/O26 NC I/O29 A14 I/O11 I/O12 A7 I/O27 I/O28 A16 A10 OE A12 A4 A1 A11 A9 A17 NC A5 A2 A0 A15 WE A13 A6 A3 A18 VCC I/O7 A8 A20 I/O23 I/O0 CS1 I/O6 I/O16 CS3 I/O22 I/O1 A19 I/O5 I/O17 GND I/O21 I/O4 I/O18 I/O3 I/O2 11 22 FIG. 11 33 55 Ground RESET Reset CS 3 CS 2 CS4 RESET WE OE A0-20 I/O20 I/O19 44 GND BLOCK DIAGRAM CS1 2M x 8 2M x 8 8 8 66 I/O8-15 I/O0-7 2M x 8 2M x 8 8 8 I/O16-23 I/O24-31 ALTERNATE PIN CONFIGURATION FOR WF2M32U-XG2UX5 PIN DESCRIPTION RESET A0 A1 A2 A3 A4 A5 NC GND NC WE A6 A7 A8 A9 A10 VCC TOP VIEW I/O0-31 Data Inputs/Outputs 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 0.940" Address Inputs WE Write Enable CS Chip Select OE Output Enable VCC Power Supply GND Ground RESET CS WE OE A0-20 A19 A20 NC A18 NC A17 NC NC CS OE A16 A15 A14 A13 A12 A11 A0-20 The White 68 lead G2U CQFP RESET Reset fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage BLOCK DIAGRAM of the CQFP form. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O0-31 56 2M x 8 8 I/O0-7 11 2M x 8 8 I/O8-15 2M x 8 8 I/O16-23 2M x 8 8 I/O24-31 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WF2M32-XXX5 PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H) 30.1 (1.185) 0.38 (0.015) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 6.22 (0.245) MAX 3.81 (0.150) 0.1 (0.005) 1.27 (0.050) 0.1 (0.005) 0.76 (0.030) 0.1 (0.005) 2.54 (0.100) TYP 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 12 WF2M32-XXX5 PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U) 25.15 (0.990) 0.25 (0.010) SQ 3.51 (0.140) MAX 22.36 (0.880) 0.25 (0.010) SQ 0.25 (0.010) 0.10 (0.002) 0.25 (0.010) REF Pin 1 R 0.25 (0.010) 24.0 (0.946) 0.25 (0.010) 0.53 (0.021) 0.18 (0.007) 1 / 7 1.01 (0.040) 0.13 (0.005) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP SEE DETAIL "A" 0.38 (0.015) 0.05 (0.002) 20.3 (0.800) REF The White 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form. 0.940" TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 13 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WF2M32-XXX5 ORDERING INFORMATION W F 2M32 X - XXX X X 5 X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads VPP PROGRAMMING VOLTAGE 5=5V DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55C to +125C -40C to +85C 0C to +70C PACKAGE TYPE: H = Ceramic Hex In line Package, HIP (Package 401) G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510) ACCESS TIME (ns) IMPROVEMENT MARK * For HIP Package Blank = 4CS and 4WE I = 4CS and 1WE, RESET * For G2U Package Blank = 4CS and 4WE U = 1CS and 1WE ORGANIZATION, 2M x 32 User configurable as 4M x 16 or 8M x 8 (Except WF2M32U-XG2UX which is 32 bit wide only.) Flash PROM WHITE ELECTRONIC DESIGNS CORP. DEVICE TYPE SECTOR SIZE SPEED PACKAGE SMD NO. 2M x 32 5V Flash Module 64KByte 150ns 66 pin HIP (H) 5962-97531 01HXX* 2M x 32 5V Flash Module 64KByte 120ns 66 pin HIP (H) 5962-97531 02HXX* 2M x 32 5V Flash Module 64KByte 90ns 66 pin HIP (H) 5962-97531 03HXX* 2M x 32 5V Flash Module 64KByte 150ns 68 lead CQFP/J (G2U) 5962-97531 01HXX* 2M x 32 5V Flash Module 64KByte 120ns 68 lead CQFP/J (G2U) 5962-97531 02HXX* 2M x 32 5V Flash Module 64KByte 90ns 68 lead CQFP/J (G2U) 5962-97531 03HXX* * Pending White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 14