Product Specification PE42720 UltraCMOS(R) SPDT RF Switch 5 - 3000 MHz Product Description Features HaRPTM technology enhanced High linearity LI FE The PE42720 is a HaRPTM technology-enhanced absorptive 75 SPDT RF switch developed on the UltraCMOS(R) process technology. CTB/CSO of -104 dBc PE42720 is a highly linear device delivering high isolation and low insertion loss performance. It is designed for CATV applications including CATV signal switching and distribution, cable modem headend, and DBS IF switching. Supports +1.8V control logic Low insertion loss 0.7 dB @ 1 GHz 0.8 dB @ 2 GHz PE42720 supports +1.8V control logic and offers high ESD protection. In addition, no blocking capacitors are required if DC voltage is not present on the RF ports. High isolation 65 dB @ 1 GHz 64 dB @ 2 GHz 63 dB @ 3 GHz High ESD performance 2500V HBM on all pins 500V CDM on all pins O F Peregrine's HaRPTM technology enhancement is an innovative feature of the UltraCMOS(R) process, offering the performance of GaAs with the economy and integration of conventional CMOS. 1.0 dB @ 3 GHz Figure 1. Functional Diagram EN D Figure 2. Package Type 20-lead 4x4 mm LGA DOC-35206 Document No. DOC-12514-2 www.psemi.com (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE42720 Product Specification Table 1. Electrical Specifications @ 25C, VDD = 3.0V (ZS = ZL = 75 ) Parameter Path Condition Min Operating frequency 5 Isolation RFX-RFX 5-100 MHz 100-1000 MHz 1000-2000 MHz 2000-3000 MHz Isolation RFC-RFX 5-100 MHz 100-1000 MHz 1000-2000 MHz 2000-3000 MHz All ports 5-2500 MHz 2500-3000 MHz Return loss Input 1 dB compression point1,2 RFC-RFX 0.6 0.7 0.8 1.0 Max Unit 3000 MHz 0.8 0.9 1.0 1.3 dB dB dB dB LI FE RFC-RFX 5-100 MHz 100-1000 MHz 1000-2000 MHz 2000-3000 MHz Insertion loss Typ All bands, 100% duty cycle 68 63 60 58 70 65 62 60 dB dB dB dB 68 63 62 61 70 65 64 63 dB dB dB dB 20 14 dB dB 31 dBm -104 dBc 5 mVPP 30 159 channels; 42 dBmV per channel output power Video feedthrough3 DC measurement Switching time 50% CTRL to 90% or 10% RF F CTB / CSO 1500 2100 ns EN D O Notes: 1. The input 1dB compression point is a linearity figure of merit. Refer to Table 3 for the RF input power PIN 2. Measured in a 50 system 3. Measured with a 3 ns rise time, 0/3V pulse and 500 MHz bandwidth (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-12514-2 UltraCMOS(R) RFIC Solutions Page 2 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE42720 Product Specification Figure 3. Pin Configuration (Top View) Table 3. Operating Ranges Symbol Min Supply voltage VDD 2.7 Supply current VDD = 2.7 to 5.5V IDD Digital input high (CTRL1, CTRL2) VIH Digital input low (CTRL1, CTRL2) 3 RF1 Description RF port 1 RF common 13 RF21 16 CTRL2 Digital control logic input 2 17 CTRL1 Digital control logic input 1 20 VDD Supply voltage Exposed pad: ground for proper operation RF pins 3, 8, and 13 must be at 0V DC. The RF pins do not require DC blocking capacitors for proper operation if the 0V DC requirement is met EN D Note 1: O RFC GND 200 A 3.6 V A PIN 28 dBm RF input power into terminated ports (RFX)1 PIN,TERM 20 dBm Operating temperature range TOP +85 C -0.3 ICTRL 9 -40 Table 4. Absolute Maximum Ratings Supply voltage 1 8 Pad V 12 Parameter/Condition Ground RF port 5.5 V F GND Unit Note 1: 100% duty cycle, all bands, 75 Table 2. Pin Descriptions 1, 2, 4-7, 9, 10-12, 14, 15, 18, 19 1.17 Max 0.6 RF input power (RFC-RFX)1 Pin Name 130 VIL Digital input current Pin # Typ LI FE Parameter Document No. DOC-12514-2 www.psemi.com Digital input voltage (CTRL1, CTRL2) RF input power (RFC-RFX)1 RF input power into terminated ports (RFX)1 Storage temperature range 2 Symbol Min Max Unit VDD -0.3 5.5 V VCTRL -0.3 3.6 V PIN 28 dBm PIN,TERM 20 dBm +150 C TST -65 ESD voltage HBM , all pins VESD,HBM 2500 V ESD Voltage MM3, all pins VESD,MM 150 V VESD,CDM 500 V 4 ESD Voltage CDM , all pins Notes: 1. 100% duty cycle, all bands, 75 2. Human Body Model (MIL-STD 883 Method 3015) 3. Machine Model (JEDEC JESD22-A115) 4. Charged Device Model (JEDEC JESD22-C101) Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE42720 Product Specification Electrostatic Discharge (ESD) Precautions Table 5. Truth Table When handling this UltraCMOS(R) device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. CTRL1 CTRL2 RFC - RF1 RFC - RF2 Low Low OFF OFF Low High OFF ON High Low ON OFF Note 1: Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS(R) devices are immune to latch-up. Switching Frequency The PE42720 has a maximum 25 kHz switching rate. N/A N/A1 CTRL1 = HIGH and CTRL2 = High are not supported Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE42720 in the 20-lead 4x4 mm LGA package is MSL3. Spurious Performance The typical spurious performance of the PE42720 is -155 dBm. EN D O F Switching frequency describes the time duration between switching events. Switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. Switching time is provided in Table 1. High LI FE High 1 (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-12514-2 UltraCMOS(R) RFIC Solutions Page 4 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE42720 Product Specification Typical Performance Data @ 25C and VDD = 3.0V unless otherwise specified Figure 6. Insertion Loss vs. VDD (RFC-RFX) D O F Figure 5. Insertion Loss vs. Temp (RFC-RFX) LI FE Figure 4. Insertion Loss (RFC-RFX) Figure 8. RFC Port Return Loss vs. VDD (RF1 Active) EN Figure 7. RFC Port Return Loss vs. Temp (RF1 Active) Document No. DOC-12514-2 www.psemi.com (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE42720 Product Specification Typical Performance Data @ 25C and VDD = 3.0V unless otherwise specified Figure 9. RFC Port Return Loss vs. Temp (RF2 Active) LI FE Figure 12. Active Port Return Loss vs. VDD (RF1 Active) D O F Figure 11. Active Port Return Loss vs. Temp (RF1 Active) Figure 10. RFC Port Return Loss vs. VDD (RF2 Active) Figure 14. Active Port Return Loss vs. VDD (RF2 Active) EN Figure 13. Active Port Return Loss vs. Temp (RF2 Active) (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-12514-2 UltraCMOS(R) RFIC Solutions Page 6 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE42720 Product Specification Typical Performance Data @ 25C and VDD = 3.0V unless otherwise specified Figure 18. Isolation vs. VDD (RFC-RFX) EN D O F Figure 17. Isolation vs. Temp (RFC-RFX) Figure 16. Isolation vs. VDD (RFX-RFX) LI FE Figure 15. Isolation vs. Temp (RFX-RFX) Document No. DOC-12514-2 www.psemi.com (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE42720 Product Specification Figure 19. Evaluation Board Layout The SPDT switch evaluation board was designed to ease customer evaluation of Peregrine's PE42720. The RF common port is connected through a 75 transmission line via the F-Type connector, J2. RF1 and RF2 ports are connected through 75 transmission lines via F-Type connectors J1 and J3, respectively. A 75 through transmission line is available via F-Type connectors J4 and J5, which can be used to de-embed the loss of the PCB. J6 provides DC and digital inputs to the device. F The board is constructed of a four metal layer material with a total thickness of 60 mils. To achieve high isolation, the 75 transmission lines are designed in layer 2 using a stripline waveguide design. The board stack up for 75 transmission lines has 20 mil thickness of Rogers 4350B between layer 1 and layer 2, 20 mil thickness of Rogers 4450F between layer 2 and layer 3, and 13.3 mil thickness of Rogers 4350B between layer 3 and layer 4. LI FE Evaluation Kit O For the true performance of the PE42720 to be realized, the PCB should be designed in such a way that RF transmission lines and sensitive DC I/O traces are heavily isolated from one another. EN D 101-0557 (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-12514-2 UltraCMOS(R) RFIC Solutions Page 8 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE42720 Product Specification DOC-12527 EN D O F LI FE Figure 20. Evaluation Board Schematic Document No. DOC-12514-2 www.psemi.com (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE42720 Product Specification Figure 21. Package Drawing 20-lead 4x4 mm LGA 0.10 C A 4.00 (2X) 2.000.05 B 0.50 11 0.400.05 (x20) 15 0.31 (x20) 0.60 (x20) 0.50 (x16) (x16) 4.00 16 LI FE 10 2.000.05 2.05 0.260.05 (x20) 0.10 C (2X) 0.10 PIN #1 CORNER TOP VIEW 6 20 5 1 2.05 2.00 REF 4.20 BOTTOM VIEW 0.700.04 RECOMMENDED LAND PATTERN DOC-01890 0.10 C 0.940.07 0.08 C 4.20 SEATING PLANE F C O SIDE VIEW D Figure 22. Top Marking Specifications EN 42720 YYWW ZZZZZ = Pin 1 designator YYWW = Date Code ZZZZZ = Last five digits of Lot Number DOC-01641 (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-12514-2 UltraCMOS(R) RFIC Solutions Page 10 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE42720 Product Specification LI FE Figure 23. Tape and Reel Drawing 1. 10 sprocket hole pitch cumulative tolerance 0.02 2. Camber not to exceed 1 mm in 100 mm 3. Material: PS + C 4. Ao and Bo measured as indicated 5. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier 6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole Ao = 4.35 mm Bo = 4.35 mm Ko = 1.1 mm D O Notes: F Tape Feed Direction Table 6. Ordering Information Description Package Shipping Method PE42720LGBB-Z PE42720 SPDT RF switch Green 20-lead 4x4 mm LGA 3000 units/T&R EK42720-02 PE42720 Evaluation kit Evaluation kit 1/Box EN Order Code Sales Contact and Information For sales and contact information please visit www.psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. Document No. DOC-12514-2 www.psemi.com No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. (c)2010-2013 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com