MC68336/376 MASKED ROM MODULE MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 7-1
SECTION 7
MASKED ROM MODULE
The masked ROM module (MRM) consists of a fixed-location control register block
and an 8-Kbyte mask-programmed read-only memory array that can be mapped to
any 8-Kbyte boundary in the system memory map. The MRM can be programmed to
insert wait states to accommodate migration from slow external development memory.
Access time depends upon the number of wait states specified, but can be as fast as
two bus cycles. The MRM can be used for program accesses only, or for program and
data accesses. Data can be read in bytes, words or long words. The MRM can be con-
figured to support system bootstrap during reset.
7.1 MRM Register Block
There are three MRM control registers: the masked ROM module configuration regis-
ter (MRMCR), and the ROM array base address registers (ROMBAH and ROMBAL).
In addition, the MRM register block contains signature registers (SIGHI and SIGLO),
and ROM bootstrap words (ROMBS[0:3]).
The module mapping bit (MM) in the SIM configuration register defines the most
significant bit (ADDR23) of the IMB address for each MC68336/376 module. 5.2.1
Module Mapping contains information about how the state of MM affects the system.
The MRM control register block consists of 32 bytes, but not all locations are imple-
mented. Unimplemented register addresses are read as zeros, and writes have no
effect. Refer to D.4 Masked ROM Module for register block address map and register
bit/field definitions.
7.2 MRM Array Address Mapping
Base address registers ROMBAH and ROMBAL are used to specify the ROM array
base address in the memory map. Although the base address contained in ROMBAH
and ROMBAL is mask-programmed, these registers can be written after reset to
change the default array address if the base address lock bit (LOCK in MRMCR) is not
masked to a value of one.
The MRM array can be mapped to any 8-Kbyte boundary in the memory map, but must
not overlap other module control registers (overlap makes the registers inaccessible).
If the array overlaps the MRM register block, addresses in the block are accessed
instead of the corresponding array addresses.
ROMBAH and ROMBAL can only be written while the ROM is in low-power stop mode
(MRMCR STOP = 1) and the base address lock (MRMCR LOCK = 0) is disabled.
LOCK can be written once only to a value of one. This prevents accidental remapping
of the array.
MC68336/376 MASKED ROM MODULE MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 7-2
7.3 MRM Array Address Space Type
ASPC[1:0] in MRMCR determines ROM array address space type. The module can
respond to both program and data space accesses or to program space accesses
only. This allows code to be executed from ROM, and permits use of program counter
relative addressing mode for operand fetches from the array. The default value of
ASPC[1:0] is established during mask programming, but field value can be changed
after reset if the LOCK bit in the MRMCR has not been masked to a value of one.
Table 7-1 shows ASPC[1:0] field encodings.
Refer to 4.5 Addressing Modes for more information on addressing modes. Refer to
5.5.1.7 Function Codes for more information concerning address space types and
program/data space access.
7.4 Normal Access
The array can be accessed by byte, word, or long word. A byte or aligned word access
takes a minimum of one bus cycle (two system clocks). A long word access requires
two bus cycles. Misaligned accesses are not permitted by the CPU32 and will result in
an address error exception.
Access time can be optimized for a particular application by inserting wait states into
each access. The number of wait states inserted is determined by the value of
WAIT[1:0] in the MRMCR. Two, three, four, or five bus-cycle accesses can be speci-
fied. The default value WAIT[1:0] is established during mask programming, but field
value can be changed after reset if the LOCK bit in the MRMCR has not been masked
to a value of one.
Table 7-2 shows WAIT[1:0] field encodings.
Refer to 5.6 Bus Operation for more information concerning access times.
Table 7-1 ROM Array Space Type
ASPC[1:0] State Specified
00 Unrestricted program and data
01 Unrestricted program
10 Supervisor program and data
11 Supervisor program
Table 7-2 Wait States Field
WAIT[1:0] Cycles per Transfer
00 3
01 4
10 5
11 2
MC68336/376 MASKED ROM MODULE MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 7-3
7.5 Low-Power Stop Mode Operation
Low-power stop mode minimizes MCU power consumption. Setting the STOP bit in
MRMCR places the MRM in low-power stop mode. In low-power stop mode, the array
cannot be accessed. The reset state of STOP is the complement of the logic state of
DATA14 during reset. Low-power stop mode is exited by clearing STOP.
7.6 ROM Signature
Signature registers RSIGHI and RSIGLO contain a user-specified mask-programmed
signature pattern. A special signature algorithm allows the user to verify ROM array
content.
7.7 Reset
The state of the MRM following reset is determined by the default values programmed
into the MRMCR BOOT, LOCK, ASPC[1:0], and WAIT[1:0] bits. The default array base
address is determined by the values programmed into ROMBAL and ROMBAH.
When the mask programmed value of the MRMCR BOOT bit is zero, the contents of
MRM bootstrap words ROMBS[0:3] are used as reset vectors. When the mask pro-
grammed value of the MRMCR BOOT bit is one, reset vectors are fetched from
external memory, and system integration module chip-select logic is used to assert the
boot ROM select signal CSBOOT. Refer to 5.9.4 Chip-Select Reset Operation for
more information concerning external boot ROM selection.
MC68336/376 MASKED ROM MODULE MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 7-4
