MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
MT9M024_DS Rev. G Pub. 4/15 EN 1©Semiconductor Components Industries, LLC,2015
1/3-Inch CMOS Digital Image Sensor
MT9M024 Data Sheet, Rev. G
For the latest data sheet, please visit www.onsemi.com
Features
• Superior low-light performance
• HD video (720p60)
• Linear or high dynamic range capture
• Video/Single Frame modes
• On-chip AE and statistics engine
• Parallel and serial output
• Auto black level calibration
•Context switching
•Temperature Sensor
Applications
• Video surveillance
• 720p60 video applications
• High dynamic range imaging
General Description
The ON Semiconductor MT9M024 is a 1/3-inch CMOS
digital image sensor with an active-pixel array of
1280H x 960V. It captures images in either linear or
high dynamic range modes, with a rolling-shutter
readout. It includes sophisticated camera functions
such as auto exposure control, windowing, and both
video and single frame modes. It is designed for both
low light and high dynamic range scene performance.
It is programmable through a simple two-wire serial
interface. The MT9M024 produces extraordinarily
clear, sharp digital pictures, and its ability to capture
both continuous video and single frames makes it the
perfect choice for a wide range of applications, includ-
ing surveillance and HD video. *1.8V VDD_IO is recommended due to better row noise per-
formance
Table 1: Key Parameters
Parameter Typical Value
Optical format 1/3-inch (6 mm)
Active pixels 1280 x 960 = 1.2 Mp
Pixel size 3.75m
Color filter array RGB Bayer or monochrome
Shutter type Electronic rolling shutter
Input clock range 6 – 50 MHz
Output clock maximum 74.25 MHz
Output Serial HiSPi 12-, 14-, or 20-bit
Parallel 12-bit
Frame
rate
Full resolution 45 fps
720p 60 fps
Responsivity 5.48 V/lux-sec
SNRMAX 43.9 dB
Maximum dynamic range >115 dB
Supply
voltage
I/O 1.8 or 2.8V*
Digital 1.8 V
Analog HiSPi 2.8 V0.4 V or 1.8 V
Power consumption
(typical)
270 mW (1280 x 720
60 fps Parallel output Linear
Mode)
460 mW (1280 x 720 60 fps
Parallel output HDR Mode)
Operating temperature
(ambient) -TA–30°C to + 70° C (surveillance)
Package options 9x9 mm iBGA
Bare die
MT9M024_DS Rev. G Pub. 4/15 EN 2©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Ordering Information
Ordering Information
Table 2: Available Part Numbers
Part Number Product Description Orderable Product Attribute Description
MT9M024IA3XTC-DPBR 1.2 MP 1/3" CIS Dry Pack with Protective Film, Double Side BBAR Glass
MT9M024IA3XTC-DRBR 1.2 MP 1/3" CIS Dry Pack without Protective Film, Double Side BBAR Glass
MT9M024IA3XTM-DPBR 1.2 MP 1/3" CIS Dry Pack with Protective Film, Double Side BBAR Glass
MT9M024IA3XTM-DRBR 1.2 MP 1/3" CIS Dry Pack without Protective Film, Double Side BBAR Glass
MT9M024_DS Rev. G Pub. 4/15 EN 3©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Table of Contents
Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
High Dynamic Range Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Real-Time Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Power-On Reset and Standby Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
MT9M024_DS Rev. G Pub. 4/15 EN 4©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
List of Figures
List of Figures
Figure 1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2: Typical Configuration: Serial Four-Lane HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Figure 3: Typical Configuration: Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 4: 9 x 9 mm 63-Ball IBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 5: Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 6: Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 7: Imaging a Scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 8: Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 9: Default Pixel Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 10: LV Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 11: HiSPi Transmitter and Receiver Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 12: Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 13: Block Diagram of DLL Timing Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 14: Delaying the Clock with Respect to Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 15: Delaying Data with Respect to the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 16: Line Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 17: HDR Data Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 18: PLL-Generated Master Clock PLL Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 19: Eight Pixels in Normal and Column Mirror Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 20: Six Rows in Normal and Row Mirror Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 21: Frame Format with Embedded Data Lines Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 22: Format of Embedded Data Output within a Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 23: Format of Embedded Statistics Output within a Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 24: Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 25: Single READ from Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 26: Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 27: Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 28: Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 29: Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 30: Quantum Efficiency – Color Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 31: Estimated Quantum Efficiency – Monochrome Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 32: Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 33: I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 34: Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 35: Differential Output Voltage for Clock or Data Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 36: Eye Diagram for Clock and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 37: Skew Within the PHY and Output Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 38: Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 39: Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 40: 63-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
MT9M024_DS Rev. G Pub. 4/15 EN 5©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
List of Tables
List of Tables
Table 1: Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2: Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 1: Pin Descriptions, 9 x 9 mm, 63-ball iBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 2: Digital Gain Control for odd and even x_addr_start (R0x3004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3: Frame Time (Example Based on 1280 x 960, 45 Frames Per Second) . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 4: Frame Time: Long Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 5: Knee Points for Compression to 14 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 6: Knee Points for Compression to 12 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 7: Digital Gain Setting for Each T1/T2 and T2/T3Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 8: Real-Time Context-Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 9: Test Pattern Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 10: Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 11: I/O Timing Characteristics (2.8V VDD_IO)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 12: I/O Timing Characteristics (1.8V VDD_IO)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 13: I/O Rise Slew Rate (2.8V VDD_IO)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 14: I/O Fall Slew Rate (2.8V VDD_IO)1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 15: I/O Rise Slew Rate (1.8V VDD_IO)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 16: I/O Fall Slew Rate (1.8V VDD_IO)1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 17: DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 18: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 19: Operating Current Consumption in Parallel Output and Linear Mode . . . . . . . . . . . . . . . . . . . . . . . .47
Table 20: Operating Current Consumption in Parallel Output and HDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 21: Operating Currents in HiSPi Output and Linear Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 22: Operating Current in HiSPi Output and HDR Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 23: Standby Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 24: Input Voltage and Current (HiSPi Power Supply 0.4 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 25: Input Voltage and Current (HiSPi Power Supply 1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 26: Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 27: Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 28: Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
MT9M024_DS Rev. G Pub. 4/15 EN 6©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
General Description
General Description
The ON Semiconductor MT9M024 can be operated in its default mode or programmed
for frame size, exposure, gain, and other parameters. The default mode output is a 960p-
resolution image at 45 frames per second (fps). In linear mode, it outputs 12-bit raw
data, using either the parallel or serial (HiSPi™) output ports. In high dynamic range
mode, it outputs 12-bit compressed data using parallel output or 12-bit or 14-bit
compressed or 20-bit linearized data using the HiSPi port. The device may be operated
in video (master) mode or in single frame trigger mode.
FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a
synchronized pixel clock in parallel mode.
The MT9M024 includes additional features to allow application-specific tuning:
windowing and offset, adjustable auto-exposure control, auto black level correction, and
on-board temperature sensor. Optional register information and histogram statistic
information can be embedded in first and last 2 lines of the image frame.
The sensor is designed to operate in a wide temperature range (–30°C to +70°C).
Functional Overview
The MT9M024 is a progressive-scan sensor that generates a stream of pixel data at a
constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally
enabled to generate all internal clocks from a single master input clock running between
6 and 50 MHz The maximum output pixel rate is 74.25 Mp/s, corresponding to a clock
rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor.
Figure 1: Block Diagram
User interaction with the sensor is through the two-wire serial bus, which communi-
cates with the array control, analog signal chain, and digital signal chain. The core of the
sensor is a 1.2 Mp Active- Pixel Sensor array. The timing and control circuitry sequences
through the rows of the array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the pixels in the row integrate
incident light. The exposure is controlled by varying the time interval between reset and
Control Registers
Active Pixel Sensor
(APS)
Array
PLL
Memory
OTPM
Timing and Control
(Sequencer)
Analog Processing and
A/D Conversion
Auto Exposure
and Stats Engine
Pixel Data Path
(Signal Processing)
External
Clock
Parallel
Output
Two-Wire
Serial
Interface
Trigger
Power
MT9M024_DS Rev. G Pub. 4/15 EN 7©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Functional Overview
readout. Once a row has been read, the data from the columns is sequenced through an
analog signal chain (providing offset correction and gain), and then through an analog-
to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in
the array. The ADC output passes through a digital processing signal chain (which
provides further data path corrections and applies digital gain). The sensor also offers a
high dynamic range mode of operation where multiple images are combined on-chip to
produce a single image at 20-bit per pixel value. A compressing mode is further offered
to allow this 20-bit pixel value to be transmitted to the host system as a 12-bit value with
close to zero loss in image quality. The pixel data are output at a rate of up to 74.25 Mp/s,
in parallel to frame and line synchronization signals.
Figure 2: Typical Configuration: Serial Four-Lane HiSPi Interface
Notes: 1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for
slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
4. The parallel interface output pads can be left unconnected if the serial output interface is used.
5. ON Semiconductor recommends that 0.1μF and 10μF decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Check the MT9M024 demo headboard schematics for circuit recom-
mendations.
6. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-
pling with the digital power planes is minimized.
7. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
VDD_IO VDD_SLVS VDD_PLLVDD VAA
VDD VAA VAA_PIX
Master clock
(6–50 MHz)
S
DATA
SCLK
RESET_BAR
TEST
EXTCLK
D
GND
A
GND
Digital
ground
Analog
ground
Digital
Core
power
1
HiSPi
power
1
Analog
power
1
To
controller
From
controller
VDD_IO VDD_PLL
PLL
power
1
Digital
I/O
power
1
1.5kΩ
2
1.5kΩ
2, 3
Analog
power
1
VAA_PIX
SLVSC_N
SLVSC_P
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
SLVS3_N
VDD_SLVS
TRIGGER
OE_BAR
STANDBY
S
ADDR
MT9M024_DS Rev. G Pub. 4/15 EN 8©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Functional Overview
Figure 3: Typical Configuration: Parallel Pixel Data Interface
Notes: 1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for
slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
4. ON Semiconductor recommends that 0.1μF and 10μF decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Check the demo headboard schematics for circuit recommenda-
tions.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-
pling with the digital power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
7. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output inter-
face is used.
V
DD
Master clock
(6–50 MHz)
S
DATA
SCLK
TEST
FRAME_VALID
D
OUT
[11:0]EXTCLK
D
GND
Digital
ground
Analog
ground
Digital
core
power
1
To
controller
From
Controller
LINE_VALID
PIXCLK
RESET_BAR
V
DD
_IO
Digital
I/O
power
1
1.5kΩ
2
1.5kΩ
2, 3
V
AA
VAA_PIX
Analog
power
1
VDD_PLL
PLL
power
1
Analog
power
1
VAA_PIX
V
DD
_IO VDD_PLLV
DD
V
AA
TRIGGER
OE_BAR
STANDBY
AGND
SADDR
MT9M024_DS Rev. G Pub. 4/15 EN 9©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Functional Overview
Figure 4: 9 x 9 mm 63-Ball IBGA Package
A
B
C
D
E
F
G
H
Top View
(Ball Down)
SLVS0N SLVS0P SLVS1N SLVS1P VDD STANDBY
VDD_PLL SLVSCN SLVSCP SLVS2N SLVS2P VDD VAA VAA
EXTCLK VDD_
SLVS SLVS3N SLVS3P DGND VDD AGND
SADDR SCLK SDATA DGND DGND VDD VAA_PIX VAA_PIX
LINE_
VALID
FRAME_
VALID PIXCLK FLASH DGND VDD_IO NC
DOUT8DOUT9DOUT10 DOUT11 DGND VDD_IO TEST
DOUT4DOUT5DOUT6DOUT7DGND VDD_IO TRIGGER OE_BAR
DOUT0DOUT1DOUT2DOUT3DGND VDD_IO VDD_IO RESET_
BAR
12 3 567 84
VDD
AGND
NC
Reserved
MT9M024_DS Rev. G Pub. 4/15 EN 10 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Functional Overview
Table 1: Pin Descriptions, 9 x 9 mm, 63-ball iBGA
Name iBGA Pin Type Description
SLVS0N A2 Output HiSPi serial data, lane 0, differential N.
SLVS0P A3 Output HiSPi serial data, lane 0, differential P.
SLVS1N A4 Output HiSPi serial data, lane 1, differential N.
SLVS1P A5 Output HiSPi serial data, lane 1, differential P.
STANDBY A8 Input Standby-mode enable pin (active HIGH).
VDD_PLL B1 Power PLL power.
SLVSCN B2 Output HiSPi serial DDR clock differential N.
SLVSCP B3 Output HiSPi serial DDR clock differential P.
SLVS2N B4 Output HiSPi serial data, lane 2, differential N.
SLVS2P B5 Output HiSPi serial data, lane 2, differential P.
VAA B7, B8 Power Analog power.
EXTCLK C1 Input External input clock.
VDD_SLVS C2 Power HiSPi power.
SLVS3N C3 Output HiSPi serial data, lane 3, differential N.
SLVS3P C4 Output HiSPi serial data, lane 3, differential P.
DGND C5, D4, D5, E5, F5, G5, H5 Power Digital ground.
VDD A6, A7, B6, C6, D6 Power Digital power.
AGND C7, C8 Power Analog ground.
SADDR D1 Input Two-Wire Serial address select.
SCLK D2 Input Two-Wire Serial clock input.
SDATA D3 I/O Two-Wire Serial data I/O.
VAA_PIX D7, D8 Power Pixel power.
LINE_VALID E1 Output Asserted when DOUT line data is valid.
FRAME_VALID E2 Output Asserted when DOUT frame data is valid.
PIXCLK E3 Output Pixel clock out. DOUT is valid on rising edge of this clock.
VDD_IO E6, F6, G6, H6, H7 Power I/O supply power.
DOUT8 F1 Output Parallel pixel data output.
DOUT9 F2 Output Parallel pixel data output.
DOUT10 F3 Output Parallel pixel data output.
DOUT11 F4 Output Parallel pixel data output (MSB)
TEST F7 Input. Manufacturing test enable pin (connect to DGND).
DOUT4 G1 Output Parallel pixel data output.
DOUT5 G2 Output Parallel pixel data output.
DOUT6 G3 Output Parallel pixel data output.
DOUT7 G4 Output Parallel pixel data output.
TRIGGER G7 Input Exposure synchronization input.
OE_BAR G8 Input Output enable (active LOW).
DOUT0 H1 Output Parallel pixel data output (LSB)
DOUT1 H2 Output Parallel pixel data output.
DOUT2 H3 Output Parallel pixel data output.
DOUT3 H4 Output Parallel pixel data output.
MT9M024_DS Rev. G Pub. 4/15 EN 11 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Functional Overview
RESET_BAR H8 Input Asynchronous reset (active LOW). All settings are restored to
factory default.
FLASH E4 Output Flash control output.
NC E7, E8 No connection.
Reserved F8 No connection.
Table 1: Pin Descriptions, 9 x 9 mm, 63-ball iBGA
Name iBGA Pin Type Description
MT9M024_DS Rev. G Pub. 4/15 EN 12 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Pixel Data Format
Pixel Data Format
Pixel Array Structure
The MT9M024 pixel array is configured as 1412 columns by 1028 rows, (see Figure 5).
The dark pixels are optically black and are used internally to monitor black level. Of the
right 100 columns, 64 are dark pixels used for row noise correction. Of the top 24 rows of
pixels, 12 of the dark rows are used for black level correction. There are 1296 columns by
976 rows of optically active pixels. While the sensor's format is 1280 x 960, the additional
active columns and active rows are included for use when horizontal or vertical mirrored
readout is enabled, to allow readout to start on the same pixel. The pixel adjustment is
always performed for monochrome or color versions. The active area is surrounded with
optically transparent dummy pixels to improve image uniformity within the active area.
Not all dummy pixels or barrier pixels can be read out.
Figure 5: Pixel Array Description
2 light dummy + 4 barrier + 24 dark + 4 barrier + 6 dark dummy
Dark pixel Barrier pixel Light dummy
pixel Active pixel
2 light dummy + 4 barrier + 6 dark dummy
1412
2 light dummy + 4 barrier
2 light dummy + 4 barrier + 100 dark + 4 barrier
1028
1296 x 976 (1288 x 968 active)
4.86 x 3.66 mm2 (4.83 x 3.63 mm2)
MT9M024_DS Rev. G Pub. 4/15 EN 13 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Pixel Data Format
Figure 6: Pixel Color Pattern Detail (Top Right Corner)
Default Readout Order
By convention, the sensor core pixel array is shown with pixel (0,0) in the top right
corner (see Figure 6). This reflects the actual layout of the array on the die. Also, the first
pixel data read out of the sensor in default condition is that of pixel (112, 44).
When the sensor is imaging, the active surface of the sensor faces the scene as shown in
Figure 7. When the image is read out of the sensor, it is read one row at a time, with the
rows and columns sequenced as shown in Figure 7 on page 8.
Figure 7: Imaging a Scene
Active Pixel (0,0)
Physical Pixel (112, 44)
Row
Reado
ut Direction
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
Column Readout Direction
Lens
Pixel (0,0)
Row
Readout
Order
Column Readout Order
Scene
Sensor (rear view)
MT9M024_DS Rev. G Pub. 4/15 EN 14 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Pixel Data Format
Digital Gain Control
MT9M024 supports four digital gains for the color channels: Red, Green1 (green pixels
on the red rows), Green2 (green pixels on the blue rows), and Blue. Digital gain control of
the MT9M024 is dependent on the configuration of the x_addr_start register. Table 4
illustrates how the digital gains are applied when x_addr_start is even or odd number.
Table 2: Digital Gain Control for odd and even x_addr_start (R0x3004)
Pixels x_addr_start Gain Register
Red Even red_gain R0x305A
Odd green1_gain R0x3056
Green1 (on Red rows) Even green1_gain R0x3056
Odd red_gain R0x305A
Green2 (on Blue rows) Even green2_gain R0x305C
Odd blue_gain R0x3058
Blue Even blue_gain R0x3058
Odd green2_gain R0x305C
MT9M024_DS Rev. G Pub. 4/15 EN 15 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Output Data Format
Output Data Format
The MT9M024 image data is read out in a progressive scan. Valid image data is
surrounded by horizontal and vertical blanking (see Figure 8). The amount of horizontal
row time (in clocks) is programmable through R0x300C. The amount of vertical frame
time (in rows) is programmable through R0x300A. Line_Valid (LV) is HIGH during the
shaded region of Figure 8. Optional Embedded Register setup information and Histo-
gram statistic information are available in first 2 and last row of image data.
Figure 8: Spatial Illustration of Image Readout
Readout Sequence
Typically, the readout window is set to a region including only active pixels. The user has
the option of reading out dark regions of the array, but if this is done, consideration must
be given to how the sensor reads the dark regions for its own purposes.
P
0,0
P
0,1
P
0,2
.....................................P
0,n-1
P
0,n
P
1,0
P
1,1
P
1,2
.....................................P
1,n-1
P
1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P
m-1,0
P
m-1,1
.....................................P
m-1,n-1
P
m-1,n
P
m,0
P
m,1
.....................................P
m,n-1
P
m,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
VALID IMAGE HORIZONTAL
BLANKING
VERTICAL BLANKING VERTICAL/HORIZONTAL
BLANKING
MT9M024_DS Rev. G Pub. 4/15 EN 16 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Output Data Format
Parallel Output Data Timing
The output images are divided into frames, which are further divided into lines. By
default, the sensor produces 968 rows of 1284 columns each. The FV and LV signals indi-
cate the boundaries between frames and lines, respectively. PIXCLK can be used as a
clock to latch the data. For each PIXCLK cycle, with respect to the falling edge, one 12-bit
pixel datum outputs on the DOUT pins. When both FV and LV are asserted, the pixel is
valid. PIXCLK cycles that occur when FV is de-asserted are called vertical blanking.
PIXCLK cycles that occur when only LV is de-asserted are called horizontal blanking.
Figure 9: Default Pixel Output Timing
LV and FV
The timing of the FV and LV outputs is closely related to the row time and the frame time.
FV will be asserted for an integral number of row times, which will normally be equal to
the height of the output image.
LV will be asserted during the valid pixels of each row. The leading edge of LV will be
offset from the leading edge of FV by 6 PIXCLKs. Normally, LV will only be asserted if FV
is asserted; this is configurable as described below.
LV Format Options
The default situation is for LV to be de-asserted when FV is de-asserted. By configuring
R0x306E[1:0], the LV signal can take two different output formats. The formats for
reading out four lines and two vertical blanking lines are shown in Figure 10.
PIXCLK
FV
LV
DOUT[11:0]
P0 P1 P2 P3 P4 Pn
Vertical Blanking Horiz Blanking Valid Image Data Horiz Blanking Vertical Blanking
MT9M024_DS Rev. G Pub. 4/15 EN 17 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Output Data Format
Figure 10: LV Format Options
The timing of an entire frame is shown in Figure 16: “Line Timing and FRAME_VALID/
LINE_VALID Signals,” on page 15.
Serial Output Data Timing
The MT9M024 also uses ON Semiconductor's High-Speed Serial Pixel Interface
(“HiSPi”). The physical interface comprises differential serial data lines and a differential
clock line. The protocol layer formats the data and synchronization signals separately,
with Sync codes defined for active image boundaries. Figure 11 shows the configuration
between the HiSPi transmitter and the receiver. There are two options for HiSPi output
SLVS or HiVCM mode selectable through register 0x306E bit 9. Setting this bit to 0
selects SLVS ; setting the bit to 1 selects HiVCM.
Figure 11: HiSPi Transmitter and Receiver Interface Block Diagram
HiSPi Physical Layer
The HiSPi physical layer has four data lanes and an associated clock lane. Depending on
the sensor operating mode and data rate, it can be configured to use either 2, 3, or 4
lanes. The PHY will serialize a 12- to 20-bit data word and transmit each bit of data
Default
Continuous LV
FV
LV
FV
LV
A camera containing
the HiSPi transmitter
A host (DSP) containing
the HiSPi receiver
Dp0
Dn0
Dp1
Dn1
Dp2
Dn2
Dp3
Dn3
Cp0
Cn0
Tx
PHY0
Rx
PHY0
Dp0
Dn0
Dp1
Dn1
Dp2
Dn2
Dp3
Dn3
Cp0
Cn0
MT9M024_DS Rev. G Pub. 4/15 EN 18 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Output Data Format
centered on a rising edge of the clock, the second on the following falling edge of clock.
Figure 12 shows bit transmission. In this example, the word is transmitted in order of
MSB to LSB. The receiver latches data at the rising and falling edge of the clock.
Figure 12: Timing Diagram
DLL Timing Adjustment
The MT9M024 includes a DLL to compensate for differences in group delay for each
data lane. The DLL is connected to the clock lane and each data lane, which acts as a
control master for the output delay buffers. Once the DLL has gained phase lock, each
lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user
to increase the setup or hold time at the receiver circuits and can be used to compensate
for skew introduced in PCB design.
Delay compensation may be set for clock and/or data lines in the hispi_timing register
R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay
settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipa-
tion.
Figure 13: Block Diagram of DLL Timing Adjustment
c
p
dn
….
….
MSB LSB
TxPost
dp
cn
1 UI
TxPre
delay delay delay delaydelay
data_lane 0 data_lane 1 clock _lane 0 data_lane 2 data_lane3
CLOCK_DEL[2:0]
DATA0_DEL[2:0]
DATA1_DEL[2:0]
DATA2_DEL[2:0]
DATA3_DEL[2:0]
MT9M024_DS Rev. G Pub. 4/15 EN 19 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Output Data Format
Figure 14: Delaying the Clock with Respect to Data
Figure 15: Delaying Data with Respect to the Clock
dataN (DATAN_DEL = 000)
cp ( CLOCK_DEL = 000)
cp (CLOCK_DEL = 001)
cp (CLOCK_DEL = 010)
cp (CLOCK_DEL = 011)
cp ( CLOCK_DEL = 100)
cp (CLOCK_DEL = 101)
cp (CLOCK_DEL = 110)
cp ( CLOCK_DEL =111)
increasing CLOCK_DEL[2:0] increases clock delay
1 UI
1 UI
tDLLSTEP
cp (CLOCK_DEL = 000)
dataN (DATAN_DEL = 000)
dataN(DATAN_DEL = 001)
dataN(DATAN_DEL = 010)
dataN(DATAN_DEL = 011)
dataN(DATAN_DEL = 100)
dataN(DATAN_DEL = 101)
dataN(DATAN_DEL = 110)
dataN(DATAN_DEL = 111)
increasing DATAN_DEL[2:0] increases data delay
MT9M024_DS Rev. G Pub. 4/15 EN 20 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Output Data Format
Frame Time
The pixel clock (PIXCLK) represents the time needed to sample 1 pixel from the array.
The sensor outputs data at the maximum rate of 1 pixel per PIXCLK. One row time
(tROW) is the period from the first pixel output in a row to the first pixel output in the
next row. The row time and frame time are defined by equations in Table 3.
Figure 16: Line Timing and FRAME_VALID/LINE_VALID Signals
Sensor timing is shown in terms of pixel clock cycles (see Figure 8 on page 10). The
recommended pixel clock frequency is 74.25 MHz. The vertical blanking and the total
frame time equations assume that the integration time (coarse integration time plus fine
integration time) is less than the number of active lines plus the blanking lines:
Window Height + Vertical Blanking (EQ 1)
If this is not the case, the number of integration lines must be used instead to determine
the frame time, (see Table 4). In this example, it is assumed that the coarse integration
time control is programmed with 2000 rows and the fine shutter width total is zero.
For Master mode, if the integration time registers exceed the total readout time, then the
vertical blanking time is internally extended automatically to adjust for the additional
integration time required. This extended value is not written back to the
frame_length_lines register. The frame_length_lines register can be used to adjust
frame-to-frame readout time. This register does not affect the exposure time but it may
extend the readout time.
Table 3: Frame Time (Example Based on 1280 x 960, 45 Frames Per Second)
Parameter Name Equation Default Timing
at 74.25 MHz
AActive data time
Context A: R0x3008 - R0x3004 + 1
Context B: R0x308E - R0x308A + 1
1280 pixel clocks
= 17.23s
P1 Frame start blanking 6 (fixed) 6 pixel clocks
= 0.08s
P2 Frame end blanking 6 (fixed) 6 pixel clocks
= 0.08s
Q Horizontal blanking R0x300C - A 370 pixel clocks
= 4.98s
A+Q (tROW) Line (Row) time R0x300C 1650 pixel clocks
= 22.22s
V Vertical blanking Context A: (R0x300A-(R0x3006-R0x3002+1)) x (A + Q)
Context B: ((R0x30AA-(R0x3090-R0x308C+1)) x (A + Q)
49,500 pixel clocks
= 666.66s
Nrows x (A + Q) Frame valid time Context A: ((R0x3006-R0x3002+1)*(A+Q))-Q+P1+P2
Context B: ((R0x3090-R0x308C+1)*(A+Q))-Q+P1+P2
1,584,000 pixel clocks
= 21.33ms
F Total frame time V + (Nrows x (A + Q)) 1,633,500 pixel clocks
= 22.22ms
P1 A Q A Q A P2
Number of master clocks
FRAME_VALID
LINE_VALID
...
...
...
MT9M024_DS Rev. G Pub. 4/15 EN 21 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Output Data Format
Note: The MT9M024 uses column parallel analog-digital converters; thus short line timing is not possi-
ble. The minimum total line time is 1650 columns (horizontal width + horizontal blanking) for
HDR mode and 1400 for linear mode. The minimum horizontal blanking is 370.
Exposure
Total integration time is the result of Coarse_Integration_Time and Fine_Integration_-
Time registers, and depends also on whether manual or automatic exposure is selected.
The actual total integration time, tINT is defined as:
tINT = tINTCoarse - 410 - tINTFine (EQ 2)
= (number of lines of integration x line time) - (410 pixel clocks of conversion time over-
head) - (number of pixels of integration x pixel time)
where:
– Number of Lines of Integration (Auto Exposure Control: Enabled)
When automatic exposure control (AEC) is enabled, the number of lines of integra-
tion may vary from frame to frame, with the limits controlled by R0x311E (mini-
mum auto exposure time) and R0x311C (maximum auto exposure time).
– Number of Lines of Integration (Auto Exposure Control: Disabled)
If AEC is disabled, the number of lines of integration equals the value in R0x3012
(context A) or R0x3016 (context B).
– Number of Pixels of Integration
The number of fine shutter width pixels is independent of AEC mode (enabled or
disabled):
• Context A: the number of pixels of integration equals the value in R0x3014.
• Context B: the number of pixels of integration equals the value in R0x3018. Max-
imum value for tINTFine is line length pixel clocks - 611.
Typically, the value of the Coarse_Integration_Time register is limited to the number of
lines per frame (which includes vertical blanking lines), such that the frame rate is not
affected by the integration time. For more information on coarse and fine integration
time settings limits, please refer to the Register Reference document.
Note: In HDR mode, there are specific limitations on coarse_integration_time due to the
number of line buffers available. Please refer to the section called “HDR Specific
Exposure Settings” on page 19.
For best image quality, it is recommended that the integration time be set to two rows or
greater for the shortest exposure, particularly for monochrome sensors. For linear mode,
this would be the coarse integration time (R0x3012). For HDR mode, the integration
time should be set such that the T3 exposure is 2 rows or greater. Setting the exposure
time to 1 row may result in non-uniformity between rows.
Table 4: Frame Time: Long Integration Time
Parameter Name Equation
(Number of Pixel Clock Cycles) Default Timing
at 74.25 MHz
F’ Total frame time (long
integration time)
Context A: (R0x3012 x (A + Q)) + R0x3014 + P1 + P2
Context B: (R0x3016 x (A + Q)) + V R0x3018 + P1 + P2
3,300,012 pixel clocks
= 44.44ms
MT9M024_DS Rev. G Pub. 4/15 EN 22 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
High Dynamic Range Mode
High Dynamic Range Mode
By default, the sensor powers up in Linear Mode, however, the MT9M024 can be config-
ured to run in HDR mode. The HDR scheme used is multi-exposure HDR. This allows
the sensor to handle 120dB of dynamic range. The sensor also features a linear mode. In
HDR mode, the sensor sequentially captures three exposures by maintaining 3 separate
read and reset pointers that are interleaved within the rolling shutter readout. The inter-
mediate pixel values are stored in line buffers while waiting for the 3 exposures values to
be present. As soon as a pixel's 3 exposure values are available, they are combined to
create a linearized 20-bit value for each pixel’s response. This 20-bit value is then option-
ally compressed back to a 12- or 14-bit value for output. For 14-bit mode, the
compressing is lossless. In 12-bit mode, there is minimal data loss. Figure 17 shows the
HDR data compression:
Figure 17: HDR Data Compression
Signal Response to Light Intensity
Digital output
code
K1 = knee point 1
K2 = knee point 2
Pout = P
Decompressed linear
output
ADC max code
Piece-wise Compressed
Signal Output From
Sensor
MT9M024_DS Rev. G Pub. 4/15 EN 23 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
High Dynamic Range Mode
The HDR mode is selected when Operation_Mode_Ctrl, R0x3082[1:0] = 0. Further
controls on exposure time limits and compressing are controlled by R0x3082[5:2], and
R0x31D0. More details can be found in the MT9M024 Register Reference.
In HDR mode, when compression is used, there are two types of knee-points: (i) T1/T2
and T2/T3 capture knee-points and (ii) POUT and POUT2 compression knee-points
(Figure 17). Aligning the capture knee-points on top of the compression knee-points,
can avoid code losses (SNR loss) in the compression. Table 5 and Table 6 below show the
knee points for the different modes. Alternatively, the sensor automatically reports the
knee points and can be read directly from registers R0x319A and R0x319C.
Table 5: Knee Points for Compression to 14 Bits
T1/T2
Exposure Ratio
(R1)
R0x3082[3:2] P1 POUT1
= P1 P2 POUT2 = (P2 - P1)/
R1 + POUT1
T2/T3
Exposure Ratio
(R2)
R0x3082[5:4] PMAX
POUTMAX
= (PMAX - P2)/
(R1*R2) + POUT2
4x 212 4096 214 7168 4x 216 10240
8x 217 10752
16x 218 11008
8x 212 4096 215 7680 4x 217 10752
8x 218 11264
16x 219 11520
16x 212 4096 216 7936 4x 218 11008
8x 219 11520
16x 220 11776
Table 6: Knee Points for Compression to 12 Bits
T1/T2
Exposure Ratio
(R1)
R0x3082[3:2] P1 POUT1
= P1 P2 POUT2 = (P2 - P1)/
(R1* 4)+ POUT1
T2/T3
Exposure Ratio
(R2)
R0x3082[5:4] PMAX
POUTMAX
= (PMAX - P2)/
(R1*R2*4) + POUT2
4x 211 2048 214 2944 4x 216 3712
8x 217 3840
16x 218 3904
8x 211 2048 215 3008 4x 217 3776
8x 218 3904
16x 219 3968
16x 211 2048 216 3040 4x 218 3808
8x 219 3936
16x 220 4000
MT9M024_DS Rev. G Pub. 4/15 EN 24 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
High Dynamic Range Mode
HDR Specific Exposure Settings
In HDR mode, pixel values are stored in line buffers while waiting for all 3 exposures to
be available for final pixel data combination. There are 42 line buffers used to store inter-
mediate T1 data. Due to this limitation, the maximum coarse integration time possible is
equal to 42*T1/T2 lines.
For example, if R0x3082[3:2] = 2, the sensor is set to have T1/T2 ratio = 16x. Therefore the
maximum number of integration lines is 42*16 = 672 lines. If coarse integration time is
greater than this, the T2 integration time will stay at 42. The sensor will calculate the
ratio internally,enabling the linearization to be performed. If companding is being than
relinearization would still follow the programmed ratio. For example if the T1/T2 ratio
was programmed to 16x but coarse integration was increased beyond 672 than one
would still use the 16x relinearization formulas.
An additional limitation is the maximum number of exposure lines in relation to the
frame_length_lines register. In Linear mode, as described on page 20, maximum
coarse_integration_time = frame_length_lines - 1. However in HDR mode, since the
coarse integration time register controls T1, the max coarse_integration time is
frame_length_lines - 45.
Putting the two criteria listed above together, it can be summarized as follows:
(EQ 3)
In HDR mode, subline integration is not utilized. As such, fine integration time register
changes will have no effect on the image.
There is also a limitation of the minimum number of exposure lines that can be used.
This is summarized in the following formula:
(EQ 4)
Due to limitation on the internal floating point calculation, the exact ratio specified by
the RATIO_T2_T3 (R0x3082[5:4]) may not be achievable.
When using companded output in combination with certain exposure ratios (other than
T1/T2 = 16x and T2/T3 = 16x), digital gain needs to be set to a fixed value. Table below
provides the proper digital gain settings for each T1/T2 and T2/T3 ratio.
Table 7: Digital Gain Setting for Each T1/T2 and T2/T3Ratio
T1/T2 Ratio T2/T3 Ratio Setting for Digital Gain Register
(0x305E Context A or 0x30C4 Context B)
4 4 0x02h
4 8 0x04h
416 0x08h
8 4 0x04h
8 8 0x08h
816 0x10h
16 4 0x08h
16 8 0x10h
16 16 Any legal value
maximum coarse_integration_time minimum 42 T1 T2, frame_length_lines 45–
=
minimum coarse_integration_time 0.5*T1 T2
T2 T3
=
MT9M024_DS Rev. G Pub. 4/15 EN 25 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
High Dynamic Range Mode
Motion Compensation
In typical multi-exposure HDR systems, motion artifacts can be created when objects
move during the T1, T2 or T3 integration time. When this happens, edge artifacts can
potentially be visible and might look like a ghosting effect.
To correct this feature, the MT9M024 has special 2D motion compensation circuitry that
detects motion artifacts and corrects the image accordingly.
There are two motion compensation options available. One using the default HDR
motion compensation by setting R0x318C[14] = 1. Additional parameters are available to
control the extent of motion detection and correction as per the requirements of the
specific application. These can be set in R0x318C–R0x3190. The other is using the DLO
method of HDR combination. When using DLO, R0x318C[14] is ignored. DLO is
enabled by setting R0x3190[13] = 1. Noise filtering is enabled by setting R0x3190[14] = 1.
For more information, please refer to the MT9M024 Register Reference document.
MT9M024_DS Rev. G Pub. 4/15 EN 26 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Real-Time Context Switching
Real-Time Context Switching
In the MT9M024, the user may switch between two full register sets (listed in Table 8) by
writing to a context switch change bit in R0x30B0[13]. This context switch will change all
registers (no shadowing) at the frame start time and have the new values apply to the
immediate next exposure and readout time.
Features
See the MT9M024 Register Reference for additional details.
Reset
The MT9M024 may be reset by using RESET_BAR (active LOW) or the reset register.
Hard Reset of Logic
The RESET_BAR pin can be connected to an external RC circuit for simplicity. The
recommended RC circuit uses a 10k resistor and a 0.1F capacitor. The rise time for the
RC circuit is 1s maximum.
Soft Reset of Logic
Soft reset of logic is controlled by the R0x301A Reset register. Bit 0 is used to reset the
digital logic of the sensor while preserving the existing two-wire serial interface configu-
ration. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is
processing and starts a new frame. This bit is a self-resetting bit and also returns to “0”
during two-wire serial interface reads.
Table 8: Real-Time Context-Switch Registers
Register Description
Register Number
Context A Context B
Y_Addr_Start R0x3002 R0x308C
X_Addr_Start R0x3004 R0x308A
Y_Addr_End R0x3006 R0x3090
X_Addr_End R0x3008 R0x308E
Coarse_Integration_Time R0x3012 R0x3016
Fine_Integration_Time R0x3014 R0x3018
Y_Odd_Inc R0x30A6 R0x30A8
Column Gain R0x30B0[5:4] R0x30B0[9:8]
Green1_Gain (GreenR) R0x3056 R0x30BC
Blue_Gain R0x3058 R0x30BE
Red_Gain R0x305A R0x30C0
Green2_Gain (GreenB) R0x305C R0x30C2
Global_Gain R0x305E R0x30C4
Frame_Length_Lines R0x300A R0x30AA
Digital_Binning R0x3032[1:0] R0x3032[5:4]
Operation_Mode_Ctrl 0x3082 0x3084
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MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
Clocks
The MT9M024 requires one clock input (EXTCLK).
PLL-Generated Master Clock
The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to
multiply the prescaler output, and two divider stages to generate the output clock. The
clocking structure is shown in Figure 18. PLL control registers can be programmed to
generate desired master clock frequency.
Note: The PLL control registers must be programmed while the sensor is in the software
Standby state. The effect of programming the PLL divisors while the sensor is in the
streaming state is undefined.
Figure 18: PLL-Generated Master Clock PLL Setup
The PLL is enabled by default on the MT9M024. To configure and use the PLL:
1. Bring the MT9M024 up as normal; make sure that fEXTCLK is between 6 and 50MHz
and ensure the sensor is in software standby (R0x301A-B[2]= 0). PLL control registers
must be set in software standby.
2. Set pll_multiplier, pre_pll_clk_div, vt_sys_clk_siv, and vt_pix_clk_div based on the
desired input (fEXTCLK) and output (fPIXCLK) frequencies. Determine the M, N, P1, and
P2 values to achieve the desired fPIXCLK using this formula:
fPIXCLK= (fEXTCLK × M) / (N × P1 x P2)
where
M = PLL_Multiplier
N = Pre_PLL_Clk_Div
P1 = Vt_Sys_Clk_Div
P2 = Vt_PIX_Clk_Div
3. Wait 1ms to ensure that the VCO has locked.
4. Set R0x301A[2]=1 to enable streaming and to switch from EXTCLK to the PLL-gener-
ated clock.
Notes: 1. The PLL can be bypassed at any time (sensor will run directly off EXTCLK) by setting
R0x30B0[14]=1. The PLL is always bypassed in software standby mode. To disable the
PLL, the sensor must be in standby mode (R0x301A[2] = 0)
2. The following restrictions apply to the PLL tuning parameters:
Pre PLL
Div
(PFD)
Pre
_p
ll
_
clk
_
div
EXTCLK
PLL
Multiplier
(VCO)
PLL Output
Div 1
SYSCLK
PIXCLK
vt
_p
ix
_
clk
_
div vt
_
s
y
s
_
clk
_
div
PLL
Input
Clock
PLL Output
Clock
PLL Output
Div 2
pll_multiplier
32 M 255
1N63
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MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
3. The VCO frequency, defined as must be within
384-768 MHz.
4. When PLL_Multiplier is odd, 2 MHz <= fEXTCLK / N <= 24 MHz
5. If using HiSPi output mode, use the following settings for P2 (Vt_Pix_Clk_Div).
5a. If 20-bit mode (4 lanes): set P2 (R0x302A) = 5
5b. If 12-/14-bit mode (3 lanes): set P2 (R0x302A) = 5
5c. If 12-bit mode (2 lanes): set P2 (R0x302A) = 6
5d. If 14-bit mode (2 lanes): set P2 (R0x302A) = 7
The user can utilize the Register Wizard tool accompanying DevWare to generate PLL
settings given a supplied input clock and desired output frequency.
Spread-Spectrum Clocking
To facilitate improved EMI performance, the external clock input allows for spread spec-
trum sources, with no impact on image quality. Limits of the spread spectrum input
clock are:
• 5% maximum clock modulation
• 35 KHz maximum modulation frequency
• Accepts triangle wave modulation, as well as sine or modified triangle modulations.
Stream/Standby Control
The sensor supports two standby modes: Hard Standby and Soft Standby. In both
modes, external clock can be optionally disabled to further minimize power consump-
tion. If this is done, then the “Power-Up Sequence” on page 54 must be followed.
Soft Standby
Soft Standby is a low power state that is controlled through register R0x301A[2].
Depending on the value of R0x301A[4], the sensor will go to standby after completion of
the current frame readout (default behavior) or after the completion of the current row
readout. When the sensor comes back from Soft Standby, previously written register
settings are still maintained. Soft standby will not occur if the TRIGGER pin is held high.
A specific sequence needs to be followed to enter and exit from Soft Standby.
Entering Soft Standby:
1. Set R0x301A[2] = 0 and drive the TRIGGER pin LOW.
2. External clock can be turned off to further minimize power consumption (Optional)
Exiting Soft Standby:
1. Enable external clock if it was turned off
2. R0x301A[2] = 1 or drive the TRIGGER pin HIGH.
1P116(P1 = 1, 2, 4, 6,8, 10, 12, 14, 16)
4P216
fVCO fEXTCLK M
N
=
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MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
Hard Standby
Hard Standby puts the sensor in lower power state; previously written register settings
are still maintained.
A specific sequence needs to be followed to enter and exit from Hard Standby.
Entering Hard Standby:
1. R0x301A[8] = 1
2. Assert STANDBY pin
3. External clock can be turned off to further minimize power consumption (Optional)
Exiting Hard Standby:
1. Enable external clock if it was turned off
2. De-assert STANDBY pin
3. Set R0x301A[8] = 0
Window Control
Registers x_addr_start, x_addr_end, y_addr_start, and y_addr_end control the size and
starting coordinates of the image window.
The exact window height and width out of the sensor is determined by the difference
between the Y address start and end registers or the X address start and end registers,
respectively.
The MT9M024 allows different window sizes for context A and context B.
Blanking Control
Horizontal blank and vertical blank times are controlled by the line_length_pck and
frame_length_lines registers, respectively.
• Horizontal blanking is specified in terms of pixel clocks. It is calculated by subtracting
the X window size from the line_length_pck register. The minimum horizontal
blanking is 370 pixel clocks.
• Vertical blanking is specified in terms of numbers of lines. It is calculated by
subtracting the Y window size from the frame_length_lines register. The minimum
vertical blanking is 26 lines.
The actual imager timing can be calculated using Table 3 on page 15 and Table 4 on
page 16, which describe the Line Timing and FV/LV signals.
When in HDR mode, the maximum size is 1280 x 960.
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MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
Readout Modes
Digital Binning
By default, the resolution of the output image is the full width and height of the FOV as
defined above. The output resolution can be reduced by digital binning. For RGB and
monochrome mode, this is set by the register R0x3032. For Context A, use bits [1:0], for
Context B, use bits [5:4]. Available settings are:
00 = No binning
01 = Horizontal binning
10 = Horizontal and vertical binning
Binning gives the advantage of reducing noise at the cost of reduced resolution. When
both horizontal and vertical binning are used, a 2x improvement in SNR is achieved,
therefore improving low light performance. Binning results in a smaller resolution
image, but the FOVs between the binned and unbinned images are the same.
Bayer Space Resampling
All of the pixels in the FOV contribute to the output image in digital binning mode. This
can result in a more pleasing output image with reduced subsampling artifacts. It also
improves low-light performance. For RGB mode, resampling can be enabled by setting
of register 0x306E[4] = 1.
Mirror
Column Mirror Image
By setting R0x3040[14] = 1, the readout order of the columns is reversed, as shown in
Figure 19. The starting Bayer color pixel is maintained in this mode by a 1-pixel shift in
the imaging array.
When using horizontal mirror mode, the user must retrigger column correction. Please
refer to the column correction section to see the procedure for column correction retrig-
gering. Bayer resampling must be enabled, by setting bit 4 of register 0x306E[4] = 1.
Figure 19: Eight Pixels in Normal and Column Mirror Readout Modes
Row Mirror Image
By setting R0x3040[15] = 1, the readout order of the rows is reversed as shown in
Figure 20. The starting Bayer color pixel is maintained in this mode by a 1-pixel shift in
the imaging array. When using horizontal mirror mode, the user must retrigger column
correction. Please refer to the column correction section to see the procedure for
column correction retriggering.
G0[1
1:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0]
G3[11:0] R3[11:0] G2[11:0] R2[11:0] G1[11:0] R1[11:0]
DOUT[11:0]
LV
Normal readout
DOUT[11:0]
Reverse readout
G3[11:0] R3[11:0]
G0[11:0] R0[11:0]
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MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
Figure 20: Six Rows in Normal and Row Mirror Readout Modes
Maintaining a Constant Frame Rate
Maintaining a constant frame rate while continuing to have the ability to adjust certain
parameters is the desired scenario. This is not always possible, however, because register
updates are synchronized to the read pointer, and the shutter pointer for a frame is
usually active during the readout of the previous frame. Therefore, any register changes
that could affect the row time or the set of rows sampled causes the shutter pointer to
start over at the beginning of the next frame.
By default, the following register fields cause a “bubble” in the output rate (that is, the
vertical blank increases for one frame) if they are written in video mode, even if the new
value would not change the resulting frame rate. The following list shows only a few
examples of such registers; a full listing can be seen in the MT9M024 Register Reference.
•x_addr_start
• x_addr_end
• y_addr_start
• y_addr_end
• frame_length_lines
• line_length_pclk
• coarse_integration_time
• fine_integration_time
•read_mode
The size of this bubble is (Integration_Time × tROW ), calculating the row time according
to the new settings.
The Coarse_Integration_Time and Fine_Integration_Time fields may be written to
without causing a bubble in the output rate under certain circumstances. Because the
shutter sequence for the next frame often is active during the output of the current
frame, this would not be possible without special provisions in the hardware. Writes to
these registers take effect two frames after the frame they are written, which allows the
integration time to increase without interrupting the output or producing a corrupt
frame (as long as the change in integration time does not affect the frame time).
Synchronizing Register Writes to Frame Boundaries
Changes to most register fields that affect the size or brightness of an image take effect
on two frames after the one during which they are written. These fields are noted as
“synchronized to frame boundaries” in the MT9M024 Register Reference. To ensure that
a register update takes effect on the next frame, the write operation must be completed
after the leading edge of FV and before the trailing edge of FV.
Row0 [11:0] Row1 [11:0] Row2 [11:0] Row3 [11:0] Row4 [11:0] Row5 [11:0]
Row5 [11:0] Row4[11:0] Row3 [11:0] Row2[11:0] Row1 [11:0] Row0[11:0]
D
OUT
[11:0]
FV
Normal readout
D
OUT
[11:0]
Reverse readout
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MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
As a special case, in single frame mode, register writes that occur after FV but before the
next trigger will take effect immediately on the next frame, as if there had been a Restart.
However, if the trigger for the next frame occurs during FV, register writes take effect as
with video mode.
Fields not identified as being frame-synchronized are updated immediately after the
register write is completed. The effect of these registers on the next frame can be difficult
to predict if they affect the shutter pointer.
Restart
To restart the MT9M024 at any time during the operation of the sensor, write a “1” to the
Restart register (R0x301A[1] = 1). This has two effects: first, the current frame is inter-
rupted immediately. Second, any writes to frame-synchronized registers and the shutter
width registers take effect immediately, and a new frame starts (in video mode). The
current row completes before the new frame is started, so the time between issuing the
Restart and the beginning of the next frame can vary by about tROW.
Image Acquisition Modes
The MT9M024 supports two image acquisition modes: video(master) and single frame.
Video
The video mode takes pictures by scanning the rows of the sensor twice. On the first
scan, each row is released from reset, starting the exposure. On the second scan, the row
is sampled, processed, and returned to the reset state. The exposure for any row is there-
fore the time between the first and second scans. Each row is exposed for the same dura-
tion, but at slightly different point in time, which can cause a shear in moving subjects as
is typical with electronic rolling shutter sensors.
Single Frame
The single-frame mode operates similar to the video mode. It also scans the rows of the
sensor twice, first to reset the rows and second to read the rows. Unlike video mode
where a continuous stream of images are output from the image sensor, the single-frame
mode outputs a single frame in response to a high state placed on the TRIGGER input
pin. As long as the TRIGGER pin is held in a high state, new images will be read out. After
the TRIGGER pin is returned to a low state, the image sensor will not output any new
images and will wait for the next high state on the TRIGGER pin.
The TRIGGER pin state is detected during the vertical blanking period (i.e. the FV signal
is low). The pin is level sensitive rather than edge sensitive. As such, image integration
will only begin when the sensor detects that the TRIGGER pin has been held high for 3
consecutive clock cycles. If the trigger signal is applied to multiple sensors at the same
time, the single frame output of the sensors will be synchronized to within 1 PIXCLK if is
PLL disabled or 2 PIXCLKs if PLL is enabled.
During integration time of single-frame mode and video mode, the FLASH output pin is
at high.
Continuous Trigger
In certain applications, multiple sensors need to have their video streams synchronized
(E.g. surround view or panorama view applications). The TRIGGER pin can also be used
to synchronize output of multiple image sensors together and still get a video stream.
This is called continuous trigger mode. Continuous trigger is enabled by holding the
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MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
TRIGGER pin high. Alternatively, the TRIGGER pin can be held high until the stream bit
is enabled (R0x301A[2]=1) then can be released for continuous synchronized video
streaming.
If the TRIGGER pins for all connected MT9M024 sensors are connected to the same
control signal, all sensors will receive the trigger pulse at the same time. If they are
configured to have the same frame timing, then the usage of the TRIGGER pin guaran-
tees that all sensors will be synchronized within 1 PIXCLK cycle if PLL is disabled, or 2
PIXCLK cycles if PLL is enabled.
With continuous trigger mode, the application can now make use of the video streaming
mode while guaranteeing that all sensor outputs are synchronized. As long as the initial
trigger for the sensors takes place at the same time, all subsequent video streams will be
synchronous.
Temperature Sensor
The MT9M024 sensor has a built-in PTAT-based temperature sensor, accessible through
registers, that is capable of measuring die junction temperature.
The temperature sensor can be enabled by writing R0x30B4[0]=1 and R0x30B4[4]=1.
After this, the temperature sensor output value can be read from R0x30B2[10:0].
The value read out from the temperature sensor register is an ADC output value that
needs to be converted downstream to a final temperature value in degrees Celsius. Since
the PTAT device characteristic response is quite linear in the temperature range of oper-
ation required, a simple linear function in the format of listed in the equation below can
be used to convert the ADC output value to the final temperature in degrees Celsius.
(EQ 5)
For this conversion, a minimum of 2 known points are needed to construct the line
formula by identifying the slope and y-intercept "T0". These calibration values can be
read from registers R0x30C6 and R0x30C8 which correspond to value read at 70°C and
55°C respectively. Once read, the slope and y-intercept values can be calculated and
used in the above equation.
For more information on the temperature sensor registers, refer to the MT9M024
Register Reference.
Temperature slope R0x30B2 10:0T+
0
=
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MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
Automatic Exposure Control
The integrated automatic exposure control (AEC) is responsible for ensuring that
optimal settings of exposure and gain are computed and updated every other frame.
AEC can be enabled or disabled by R0x3100[0].
When AEC is disabled (R0x3100[0] = 0), the sensor uses the manual exposure value in
coarse and fine shutter width registers and the manual gain value in the gain registers.
When AEC is enabled (R0x3100[0]=1), the target luma value in linear mode is set by
R0x3102. For the MT9M024 this target luma has a default value of 0x0800 or about half
scale. For HDR mode, the luma target maximum auto exposure value is limited by
R0x311C; the minimum auto exposure is limited by R0x311E. These values are in units of
line-times.
The exposure control measures current scene luminosity by accumulating a histogram
of pixel values while reading out a frame. It then compares the current luminosity to the
desired output luminosity. Finally, the appropriate adjustments are made to the expo-
sure time and gain. All pixels are used, regardless of color or mono mode. In HDR mode,
the coarse and fine integration time is the longest integration time of the three integra-
tion, the other two shorter integration are generated automatically base on the pre-
defined exposure ratios. When using non-default HDR exposure ratios, auto_dg_en
should not be enabled (R0x3100[4] = 0) due to required digital gains as documented in
Table 7, “Digital Gain Setting for Each T1/T2 and T2/T3Ratio,” on page 19.
Embedded Data and Statistics
The MT9M024 has the capability to output image data and statistics embedded within
the frame timing. There are 2 types of information embedded within the frame readout:
1. Embedded Data: If enabled, these are displayed on the 2 rows immediately before the
first active pixel row is displayed.
2. Embedded Statistics: If enabled, these are displayed on the 2 rows immediately after
the last active pixel row is displayed.
Note: Embedded data and embedded statistics must be enabled or disabled together.
Figure 21: Frame Format with Embedded Data Lines Enabled
Image
Register Data
Status & Statistics Data
HBlank
VBlank
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MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
Embedded Data
The embedded data contains the configuration of the image being displayed. This
includes all register settings used to capture the current frame. The registers embedded
in these rows are as follows:
Line 1: Registers R0x3000 to R0x312F
Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF
Note: All non-defined registers will have a value of 0.
In parallel mode, since the pixel word depth is 12-bits/pixel, the sensor 16-bit register
data will be transferred over 2 pixels where the register data will be broken up into 8msb
and 8lsb. The alignment of the 8bit data will be on the 8MSB bits of the 12-bit pixel word.
For example, if a register value of 0x1234 is to be transmitted, it will be transmitted over
2, 12-bit pixels as follows: 0x120, 0x340.
The first pixel of each line in the embedded data is a tag value of 0x0A0. This signifies
that all subsequent data is 8 bit data aligned to the MSB of the 12-bit pixel.
The figure below summarizes how the embedded data transmission looks like. It should
be noted that data, as shown in Figure 22, is aligned to the MSB of each word:
Figure 22: Format of Embedded Data Output within a Frame
The data embedded in these rows are as follows:
•0x0A0 - identifier
• 0xAA0
• Register Address MSB of the first register
•0xA50
• Register Address LSB of the first register
•0x5A0
• Register Value MSB of the first register addressed
•0x5A0
• Register Value LSB of the first register addressed
•0x5A0
• Register Value MSB of the register at first address + 2
•0x5A0
• Register Value LSB of the register at first address + 2
•0x5A0
•etc.
{register_
value_LSB} 8'h5A
Data line 1
Data line 2
8'h5A
8'hAA {register_
address_MSB} 8'hA5 {register_
address_LSB} 8'h5A {register_
value_MSB} 8'h5A
{register_
value_LSB}
data_format_
code =8'h0A
8'hAA
{register_
address_MSB} 8'hA5 {register_
address_LSB} 8'h5A {register_
value_MSB} 8'h5A
data_format_
code =8'h0A
MT9M024_DS Rev. G Pub. 4/15 EN 36 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
Embedded Statistics
The embedded statistics contain frame identifiers and histogram information of the
image in the frame. This can be used by downstream auto-exposure algorithm blocks to
make decisions about exposure adjustment.
This histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for
digital code values 0 to 212, 120 evenly spaced bins for values 212 to 216, 60 evenly spaced
bins for values 216 to 220. In HDR with a 16x exposure ratio, this approximately corre-
sponds to the T1, T2, T3 exposures respectively.
The first pixel of each line in the embedded statistics is a tag value of 0x0B0. This signi-
fies that all subsequent statistics data is 10 bit data aligned to the MSB of the 12-bit pixel.
The figure below summarizes how the embedded statistics transmission looks like. It
should be noted that data, as shown in Figure 23, is aligned to the msb of each word:
Figure 23: Format of Embedded Statistics Output within a Frame
The statistics embedded in these rows are as follows:
Line 1:
• 0x0B0 - (identifier)
• Register 0x303A - frame_count
• Register 0x31D2 - frame ID
• Histogram data - histogram bins 0-243
Line 2:
•0x0B0 (identifier)
•Mean
•Histogram Begin
•Histogram End
•Low End Histogram Mean
• Percentage of Pixels Below Low End Mean
• Normal Absolute Deviation
Gain
Digital Gain
Digital gain can be controlled globally by R0x305E (Context A) or R0x30C4 (Context B).
There are also registers that allow individual control over each Bayer color (GreenR,
GreenB, Red, Blue).
{2'b00,frame
_count MSB}
{2'b00,frame
_count LSB}
{2'b00,frame
_ID MSB}
{2'b00,frame
_ID LSB}
histogram
bin0 [19:10]
histogram
bin0 [9:0]
histogram
bin1 [19:10]
histogram
bin1 [9:0]
# words =
10'h1EC
data_format_
code = 8'h0B
histogram
bin243 [19:10]
histogram
bin243 [9:0]
# words =
10'h00C
data_format_
code = 8'h0B
mean
[19:10]
mean
[9:0]
histBegin
[19:10]
histBegin
[9:0]
histEnd
[19:10]
histEnd
[9:0]
lowEndMean
[19:10]
lowEndMean
[9:0]
perc_lowEnd
[19:10]
perc_lowEnd
[9:0]
norm_abs_
dev [19:10]
norm_abs_
dev [9:0]
8'h07 8'h07
8'h07
stats line 1
stats line 2
MT9M024_DS Rev. G Pub. 4/15 EN 37 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
The format for digital gain setting is xxx.yyyyy where 0b00100000 represents a 1x gain
setting and 0b00110000 represents a 1.5x gain setting. The step size for yyyyy is 0.03125
while the step size for xxx is 1. Therefore to set a gain of 2.09375 one would set digital
gain to 01000011.
Analog Gain
The MT9M024 has a column parallel architecture and therefore has an Analog gain stage
per column.
There are 2 stages of analog gain, the first stage can be set to 1x, 2x, 4x or 8x. This can be
set in R0x30B0[5:4](Context A) or R0x30B0[9:8] (Context B). The second stage is capable
of setting an additional 1x or 1.25x gain which can be set in R0x3EE4[9:8].
This allows the maximum possible analog gain to be set to 10x.
Black Level Correction
Black level correction is handled automatically by the image sensor. No adjustments are
provided except to enable or disable this feature. Setting R0x30EA[15] disables the auto-
matic black level correction. Default setting is for automatic black level calibration to be
enabled.
The automatic black level correction measures the average value of pixels from a set of
optically black lines in the image sensor. The pixels are averaged as if they were light-
sensitive and passed through the appropriate gain. This line average is then digitally
low-pass filtered over many frames to remove temporal noise and random instabilities
associated with this measurement. The new filtered average is then compared to a
minimum acceptable level, low threshold, and a maximum acceptable level, high
threshold. If the average is lower than the minimum acceptable level, the offset correc-
tion value is increased by a predetermined amount. If it is above the maximum level, the
offset correction value is decreased by a predetermined amount. The high and low
thresholds have been calculated to avoid oscillation of the black level from below to
above the targeted black level.
Row-wise Noise Correction
Row (Line)-wise Noise Correction is handled automatically by the image sensor. No
adjustments are provided except to enable or disable this feature. Clearing R0x3044[10]
disables the row noise correction. Default setting is for row noise correction to be
enabled.
Row-wise noise correction is performed by calculating an average from a set of optically
black pixels at the start of each line and then applying each average to all the active
pixels of the line.
Column Correction
The MT9M024 uses column parallel readout architecture to achieve fast frame rate.
Without any corrections, the consequence of this architecture is that different column
signal paths have slightly different offsets that might show up on the final image as
structured fixed pattern noise.
MT9M024 has column correction circuitry that measures this offset and removes it from
the image before output. This is done by sampling dark rows containing tied pixels and
measuring an offset coefficient per column to be corrected later in the signal path.
MT9M024_DS Rev. G Pub. 4/15 EN 38 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
Column correction can be enabled/disabled via R0x30D4[15]. Additionally, the number
of rows used for this offset coefficient measurement is set in R0x30D4[3:0]. By default
this register is set to 0x7, which means that 8 rows are used. This is the recommended
value. Other control features regarding column correction can be viewed in the
MT9M024 Register reference. Any changes to column correction settings need to be
done when the sensor streaming is disabled and the appropriate triggering sequence
must be followed as described below.
Column Correction Triggering
Column correction requires a special procedure to trigger depending on which state the
sensor is in.
Column Triggering on Startup
When streaming the sensor for the first time after powerup, a special sequence needs to
be followed to make sure that the column correction coefficients are internally calcu-
lated properly.
1. Follow proper power up sequence for power supplies and clocks.
2. Apply sequencer settings if needed (Linear or HDR mode).
3. Apply frame timing and PLL settings as required by application.
4. Set analog gain to 1x and low conversion gain (R0x30B0=0x1300)
5. Enable column correction and settings (R0x30D4=0xE007).
6. Disable auto re-trigger for change in conversion gain or col_gain, and enable column
correction always (R0x30BA = 0x0008).
7. Enable streaming (R0x301A[2]=1)or drive the TRIGGER pin HIGH.
8. Wait 9 frames to settle (First frame after coming up from standby is internally column
correction disabled).
9. Disable streaming (R0x301A[2]=0).
After this, the sensor has calculated the proper column correction coefficients and the
sensor is ready for streaming. Any other settings (including gain, integration time and
conversion gain etc.) can be done afterwards without affecting column correction.
Column Correction Retriggering Due to Mode Change
Since column offsets is sensitive to changes in the analog signal path, such changes
require column correction circuitry to be retriggered for the new path. Examples of such
mode changes include: horizontal mirror, vertical mirror, changes to column correction
settings.
When such changes take place, the following sequence needs to take place:
1. Disable streaming (R0x301A[2]=0) or drive the TRIGGER pin LOW.
2. Enable streaming (R0x301A[2]=1) or drive the TRIGGER pin HIGH.
3. Wait 9 frames to settle.
Note: The above steps are not needed if the sensor is being reset (soft or hard reset) upon
the mode change.
Defective Pixel Correction
Defective Pixel Correction is intended to compensate for defective pixels by replacing
their value with a value based on the surrounding pixels, making the defect less notice-
able to the human eye. The defect pixel correction feature supports up to 200 defects.
MT9M024_DS Rev. G Pub. 4/15 EN 39 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
The locations of defective pixels are stored in a table on chip during the manufacturing
process; this table is accessible through the two-wire serial interface. There is no provi-
sion for later augmenting the defect table entries.
The DPC algorithm is one-dimensional, calculating the resulting averaged pixel value
based on nearby pixels within a row. The algorithm distinguishes between color and
monochrome parts; for color parts, the algorithm uses nearest neighbor in the same
color plane.
At high gain, long exposure, and high temperature conditions, the performance of this
function can degrade.
Test Patterns
The MT9M024 has the capability of injecting a number of test patterns into the top of
the datapath to debug the digital logic. With one of the test patterns activated, any of the
datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns
are selected by Test_Pattern_Mode register (R0x3070). Only one of the test patterns can
be enabled at a given point in time by setting the Test_Pattern_Mode register according
to Table 9. When test patterns are enabled the active area will receive the value specified
by the selected test pattern and the dark pixels will receive the value in Test_Pat-
tern_Green (R0x3074 and R0x3078) for green pixels, Test_Pattern_Blue (R0x3076) for
blue pixels, and Test_Pattern_Red (R0x3072) for red pixels.
Note: Turn off black level calibration (BLC) when Test Pattern is enabled.
Color Field
When the color field mode is selected, the value for each pixel is determined by its color.
Green pixels will receive the value in Test_Pattern_Green, red pixels will receive the value
in Test_Pattern_Red, and blue pixels will receive the value in Test_Pattern_Blue.
Vertical Color Bars
When the vertical color bars mode is selected, a typical color bar pattern will be sent
through the digital pipeline.
Walking 1s
When the walking 1s mode is selected, a walking 1s pattern will be sent through the
digital pipeline. The first value in each row is 1.
Table 9: Test Pattern Modes
Test_Pattern_Mode Test Pattern Output
0 No test pattern (normal operation)
1 Solid color test pattern
2 100% color bar test pattern
3 Fade-to-gray color bar test pattern
256 Walking 1s test pattern (12-bit)
MT9M024_DS Rev. G Pub. 4/15 EN 40 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Two-Wire Serial Register Interface
The two-wire serial interface bus enables read/write access to control and status regis-
ters within the MT9M024.The interface protocol uses a master/slave model in which a
master controls one or more slave devices. The sensor acts as a slave device. The master
generates a clock (SCLK) that is an input to the sensor and is used to synchronize trans-
fers. Data is transferred between the master and the slave on a bidirectional signal
(SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or
master device can drive SDATA LOW—the interface protocol determines which device is
allowed to drive SDATA at any given time.
The protocols described in the two-wire serial interface specification allow the slave
device to drive SCLKLOW; the MT9M024 uses SCLK as an input only and therefore never
drives it LOW.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of low-
level protocol elements:
1. a (repeated) start condition
2. a slave address/data direction byte
3. an (a no) acknowledge bit
4. a message byte
5. a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a
start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. SDATA can change when SCLK
is LOW and must be stable while SCLK is HIGH.
MT9M024_DS Rev. G Pub. 4/15 EN 41 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The
default slave addresses used by the MT9M024 are 0x20 (write address) and 0x21 (read
address) in accordance with the specification. Alternate slave addresses of 0x30 (write
address) and 0x31 (read address) can be selected by enabling and asserting the SADDR
input.
An alternate slave address can also be programmed through R0x31FC.
Message Byte
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-
edge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver does not drive SDATA LOW
during the SCLK clock period following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
Typical Sequence
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a read or a write, where a “0” indi-
cates a write and a “1” indicates a read. If the address matches the address of the slave
device, the slave device acknowledges receipt of the address by generating an acknowl-
edge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
the WRITE should take place. This transfer takes place as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master then transfers the data as an 8-bit sequence; the slave sends an
acknowledge bit at the end of the sequence. The master stops writing by generating a
(re)start or stop condition.
If the request was a READ, the master sends the 8-bit write slave address/data direction
byte and 16-bit register address, the same way as with a WRITE request. The master then
generates a (re)start condition and the 8-bit read slave address/data direction byte, and
clocks out the register data, eight bits at a time. The master generates an acknowledge
bit after each 8-bit transfer. The slave’s internal register address is automatically incre-
mented after every 8 bits are transferred. The data transfer is stopped when the master
sends a no-acknowledge bit.
MT9M024_DS Rev. G Pub. 4/15 EN 42 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Single READ from Random Location
This sequence (Figure 24) starts with a dummy WRITE to the 16-bit address that is to be
used for the READ. The master terminates the WRITE by generating a restart condition.
The master then sends the 8-bit read slave address/data direction byte and clocks out
one byte of register data. The master terminates the READ by generating a no-acknowl-
edge bit followed by a stop condition. Figure 24 shows how the internal register address
maintained by the MT9M024 is loaded and incremented as the sequence proceeds.
Figure 24: Single READ from Random Location
Single READ from Current Location
This sequence (Figure 25) performs a read using the current value of the MT9M024
internal register address. The master terminates the READ by generating a no-acknowl-
edge bit followed by a stop condition. The figure shows two independent READ
sequences.
Figure 25: Single READ from Current Location
Sequential READ, Start from Random Location
This sequence (Figure 26) starts in the same way as the single READ from random loca-
tion (Figure 24). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte READs until “L” bytes have been read.
Figure 26: Sequential READ, Start from Random Location
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
slave to master
master to slave
Slave Address 0
S A Reg Address[15:8] A Reg Address[7:0] Slave Address AA 1Sr Read Data P
Previous Reg Address, N Reg Address, M M+
1
A
Slave Address 1S A Read Data Slave Address A1SP Read Data P
Previous Reg Address, N Reg Address, N+1 N+2
AA
Slave Address 0
S Sr
AReg Address[15:8]
Read Data Read Data
AReg Address[7:0] ARead DataSlave Address
Previous Reg Address, N Reg Address, M
M+1 M+2
M+1
M+3
A1
Read Data Read Data
M+L-2 M+L-1 M+L
AP
A
AAA
MT9M024_DS Rev. G Pub. 4/15 EN 43 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Sequential READ, Start from Current Location
This sequence (Figure 27) starts in the same way as the single READ from current loca-
tion (Figure 25). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte READs until “L” bytes have been read.
Figure 27: Sequential READ, Start from Current Location
Single WRITE to Random Location
This sequence (Figure 28) begins with the master generating a start condition. The slave
address/data direction byte signals a WRITE and is followed by the HIGH then LOW
bytes of the register address that is to be written. The master follows this with the byte of
write data. The WRITE is terminated by the master generating a stop condition.
Figure 28: Single WRITE to Random Location
Sequential WRITE, Start at Random Location
This sequence (Figure 29) starts in the same way as the single WRITE to random location
(Figure 28). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte WRITEs until “L” bytes have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 29: Sequential WRITE, Start at Random Location
Read Data Read Data
Previous Reg Address, N N+1 N+2 N+L-1 N+L
Read DataSlave Address A1 Read Data A PS A A A
Slave Address 0
SAReg Address[15:8] AReg Address[7:0] AP
Previous Reg Address, N Reg Address, M M+
1
A
A
Write Data
Slave Address 0
SAReg Address[15:8]
A
AReg Address[7:0] A
Previous Reg Address, N Reg Address, M
M+1 M+2
M+1
M+3
A
AA
M+L-2 M+L-1 M+L
A
AP
Write Data
Write Data Write Data Write DataWrite Data
MT9M024_DS Rev. G Pub. 4/15 EN 44 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Spectral Characteristics
Spectral Characteristics
Figure 30: Quantum Efficiency – Color Sensor
0
10
20
30
40
50
60
70
red green blue
350
Wavelength (nm)
Quantum Efficiency (%)
400 450 500 550 600 650 700 750 800 850 900 950 1000 1050
MT9M024_DS Rev. G Pub. 4/15 EN 45 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Spectral Characteristics
Figure 31: Estimated Quantum Efficiency – Monochrome Sensor
MT9M024_DS Rev. G Pub. 4/15 EN 46 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Electrical Specifications
Unless otherwise stated, the following specifications apply to the following conditions:
VDD = 1.8V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V ± 0.3V;
TA = -30°C to +70°C; output load = 10pF;
frequency = 74.25 MHz; HiSPi off.
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are
shown in Figure 32 and Table 10.
Figure 32: Two-Wire Serial Bus Timing Parameters
Note: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register
address are issued.
Table 10: Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Parameter Symbol
Standard-Mode Fast-Mode
UnitMin Max Min Max
SCLK Clock Frequency fSCL 0 100 0 400 KHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD;STA 4.0 - 0.6 - S
LOW period of the SCLK clock tLOW 4.7 - 1.3 - S
HIGH period of the SCLK clock tHIGH 4.0 - 0.6 - S
Set-up time for a repeated START
condition
tSU;STA 4.7 - 0.6 - S
Data hold time: tHD;DAT 043.455060.95S
Data set-up time tSU;DAT 250 - 1006-nS
SSr
tSU;STO
tSU;STA
tHD;STA tHIGH
tLOW tSU;DAT
tHD;DAT
tf
SDATA
SCLK
PS
tBUF
tr
tf
trtHD;STA
MT9M024_DS Rev. G Pub. 4/15 EN 47 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Notes: 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I2C-compatible.
3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the MT9M024 launches pixel data, FV, and LV with the falling edge of PIXCLK.
The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of
PIXCLK. This can be changed using register R0x3028.
See Figure 33 and Table 11 for I/O timing (AC) characteristics.
Rise time of both SDATA and SCLK signals tr - 1000 20 + 0.1Cb7300 nS
Fall time of both SDATA and SCLK signals tf - 300 20 + 0.1Cb7300 nS
Set-up time for STOP condition tSU;STO 4.0 - 0.6 - S
Bus free time between a STOP and START
condition
tBUF 4.7 - 1.3 - S
Capacitive load for each bus line Cb - 400 - 400 pF
Serial interface input pin capacitance CIN_SI - 3.3 - 3.3 pF
SDATA max load capacitance CLOAD_SD - 30 - 30 pF
SDATA pull-up resistor RSD 1.5 4.7 1.5 4.7 K
Table 10: Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Parameter Symbol
Standard-Mode Fast-Mode
UnitMin Max Min Max
MT9M024_DS Rev. G Pub. 4/15 EN 48 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Figure 33: I/O Timing Diagram
Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
at 2.5 V, and -30°C at 3.1 V. All values are taken at the 50% transition point. The loading used is 10
pF.
2. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
Table 11: I/O Timing Characteristics (2.8V VDD_IO)1
Symbol Definition Condition Min Typ Max Unit
fEXTCLK Input clock frequency 6 – 50 MHz
tEXTCLK Input clock period 20 – 166 ns
tR Input clock rise time – 3 – ns
tF Input clock fall time – 3 – ns
tJITTER Input clock jitter – – 600 ps
tRP Pixclk rise time PCLK slew rate = 6 1.2 – 2.9 ns
tFP Pixclk fall time PCLK slew rate = 6 1.2 – 2.9 ns
Pixclk duty cycle 45 50 55 %
fPIXCLK PIXCLK frequency26 – 74.25 MHz
tPD PIXCLK to data valid PCLK slew rate = 6,
Parallel slew rate = 7
–2 – 2.5 ns
tPFH PIXCLK to FV HIGH PCLK slew rate = 6,
Parallel slew rate = 7
–2 – 2.5 ns
tPLH PIXCLK to LV HIGH PCLK slew rate = 6,
Parallel slew rate = 7
–2 – 2.5 ns
tPFL PIXCLK to FV LOW PCLK slew rate = 6,
Parallel slew rate = 7
–2 – 2.5 ns
tPLL PIXCLK to LV LOW PCLK slew rate = 6,
Parallel slew rate = 7
–2 – 2.5 ns
Data[11:0]
LINE_VALID/
PIXCLK
EXTCLK
tR
tEXTCLK
tF
FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
FRAME_VALID trails
LINE_VALID by 6 PIXCLKs.
tPLH
tPFH
tPFL
tPLL
tPD
Pxl_0 Pxl _1 Pxl _2 Pxl_n
90%
10%
tRP tFP
90%
10%
FRAME_VALID
MT9M024_DS Rev. G Pub. 4/15 EN 49 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
at 1.7 V, and -30°C at 1.95V. All values are taken at the 50% transition point. The loading used is
10 pF.
2. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
at 2.5V, and -30°C at 3.1 V. The loading used is 10 pF.
Table 12: I/O Timing Characteristics (1.8V VDD_IO)1
Symbol Definition Condition Min Typ Max Unit
fEXTCLK Input clock frequency 6-50MHz
tEXTCLK Input clock period 20 - 166 ns
tRInput clock rise time -3-ns
tFInput clock fall time -3-ns
tJITTER Input clock jitter – – 600 ps
tRP Pixel rise time PCLK slew rate = 6 1.8 - 4.8 ns
tFP Pixel fall time PCLK slew rate = 6 1.7 - 4.5 ns
Pixel duty cycle 45 50 55 %
fPIXCLK PIXCLK frequency2674.25MHz
tPD PIXCLK to data valid PCLK slew rate = 6,
Parallel slew rate = 7
–2.5 – 2 ns
tPFH PIXCLK to FV HIGH PCLK slew rate = 6,
Parallel slew rate = 7
–2.5 – 2 ns
tPLH PIXCLK to LV HIGH PCLK slew rate = 6,
Parallel slew rate = 7
–2.5 – 2 ns
tPFL PIXCLK to FV LOW PCLK slew rate = 6,
Parallel slew rate = 7
–2.5 – 2 ns
tPLL PIXCLK to LV LOW PCLK slew rate = 6,
Parallel slew rate = 7
–2.5 – 2 ns
Table 13: I/O Rise Slew Rate (2.8V VDD_IO)1
Parallel Slew Rate
(R0x306E[15:13]) Conditions Min Typ Max Units
7 Default 1.08 1.77 2.72 V/ns
6 Default 0.77 1.26 1.94 V/ns
5 Default 0.58 0.95 1.46 V/ns
4 Default 0.44 0.70 1.08 V/ns
3 Default 0.32 0.51 0.78 V/ns
2 Default 0.23 0.37 0.56 V/ns
1 Default 0.16 0.25 0.38 V/ns
0 Default 0.10 0.15 0.22 V/ns
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
MT9M024_DS Rev. G Pub. 4/15 EN 50 ©Semiconductor Components Industries, LLC,2015.
Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
at 2.5 V, and -30°C at 3.1V. The loading used is 10 pF.
Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
at 1.7 V, and -30°C at 1.95V. The loading used is 10 pF.
Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
at 1.7 V, and -30°C at 1.95V. The loading used is 10 pF.
Table 14: I/O Fall Slew Rate (2.8V VDD_IO)1
Parallel Slew Rate
(R0x306E[15:13]) Conditions Min Typ Max Units
7 Default 1.00 1.62 2.41 V/ns
6 Default 0.76 1.24 1.88 V/ns
5 Default 0.60 0.98 1.50 V/ns
4 Default 0.46 0.75 1.16 V/ns
3 Default 0.35 0.56 0.86 V/ns
2 Default 0.25 0.40 0.61 V/ns
1 Default 0.17 0.27 0.41 V/ns
0 Default 0.11 0.16 0.24 V/ns
Table 15: I/O Rise Slew Rate (1.8V VDD_IO)1
Parallel Slew Rate
(R0x306E[15:13]) Conditions
Min Typ Max Units
7 Default 0.41 0.65 1.10 V/ns
6 Default 0.30 0.47 0.79 V/ns
5 Default 0.24 0.37 0.61 V/ns
4 Default 0.19 0.28 0.46 V/ns
3 Default 0.14 0.21 0.34 V/ns
2 Default 0.10 0.15 0.24 V/ns
1 Default 0.07 0.10 0.16 V/ns
0 Default 0.04 0.06 0.10 V/ns
Table 16: I/O Fall Slew Rate (1.8V VDD_IO)1
Parallel Slew Rate
(R0x306E[15:13]) Conditions Min Typ Max Units
7 Default 0.42 0.68 1.11 V/ns
6 Default 0.32 0.51 0.84 V/ns
5 Default 0.26 0.41 0.67 V/ns
4 Default 0.20 0.32 0.52 V/ns
3 Default 0.16 0.24 0.39 V/ns
2 Default 0.12 0.18 0.28 V/ns
1 Default 0.08 0.12 0.19 V/ns
0 Default 0.05 0.07 0.11 V/ns
MT9M024_DS Rev. G Pub. 4/15 EN 51 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
DC Electrical Characteristics
The DC electrical characteristics are shown in the tables below.
Table 17: DC Electrical Characteristics
Caution Stresses greater than those listed in Table 14 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other con-
ditions above those indicated in the operational sections of this specification is not implied.
Notes: 1. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. To keep dark current and shot noise artifacts from impacting image quality, keep operating tem-
perature at a minimum.
Symbol Definition Condition Min Typ Max Unit
VDD Core digital voltage 1.7 1.8 1.95 V
VDD_IO I/O digital voltage 1.7/2.5 1.8/
2.8
1.9/3.1 V
VAA Analog voltage 2.5 2.8 3.1 V
VAA_PIX Pixel supply voltage 2.5 2.8 3.1 V
VDD_PLL PLL supply voltage 2.5 2.8 3.1 V
VDD_SLVS HiSPi supply voltage for SLVS mode 0.3 0.4 0.6 V
VDD_SLVS HiSPi supply voltage for HiVcm
mode
1.7 1.8 1.95 V
VIH Input HIGH voltage VDD_IO*0.7 – – V
VIL Input LOW voltage – – VDD_IO*0.3 V
IIN Input leakage current No pull-up resistor; VIN = VDD_IO or
DGND
––20A
VOH Output HIGH voltage VDD_IO-0.3 – – V
VOL Output LOW voltage – – 0.4 V
IOH Output HIGH current At specified VOH -22 – – mA
IOL Output LOW current At specified VOL ––22mA
Table 18: Absolute Maximum Ratings
Symbol Parameter Minimum Maximum Unit Symbol
VSUPPLY Power supply voltage (all supplies) –0.3 4.5 V VSUPPLY
ISUPPLY Total power supply current – 200 mA ISUPPLY
IGND Total ground current – 200 mA IGND
VIN DC input voltage –0.3 VDD_IO + 0.3 V VIN
VOUT DC output voltage –0.3 VDD_IO + 0.3 V VOUT
TSTG1Storage temperature –40 +150 °C TSTG1
MT9M024_DS Rev. G Pub. 4/15 EN 52 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Notes: 1. Operating currents are measured at the following conditions:
VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8 V
VDD =1.8 V
PLL Enabled and PIXCLK = 74.25 MHz
TA = 25°C
CLOAD = 10 pF Measured in dark
Table 20: Operating Current Consumption in Parallel Output and HDR Mode
Notes: 1. Operating currents are measured at the following conditions:
VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8 V
VDD = 1.8 V
PLL Enabled and PIXCLK = 74.25 MHz
TA= 25°C
CLOAD = 10 pF Measured in dark
Table 19: Operating Current Consumption in Parallel Output and Linear Mode
Definition Condition Symbol Min Typ Max Unit
Digital operating current Streaming, 1280x960 45 fps IDD1 – 63 90 mA
I/O digital operating current Streaming, 1280x960 45 fps IDD_IO – 35 40 mA
Analog operating current Streaming, 1280x960 45 fps IAA – 30 45 mA
Pixel supply current Streaming, 1280x960 45 fps IAA_PIX – 10 15 mA
PLL supply current Streaming, 1280x960 45 fps IDD_PLL – 7 15 mA
Digital operating current Streaming, 720p 60 fps IDD1 – 63 90 mA
I/O digital operating current Streaming, 720p 60 fps IDD_IO - 35 40 mA
Analog operating current Streaming, 720p 60 fps IAA – 30 45 mA
Pixel supply current Streaming, 720p 60 fps IAA_PIX – 10 15 mA
PLL supply current Streaming, 720p 60f ps IDD_PLL – 7 15 mA
Definition Condition Symbol Min Typ Max Unit
Digital operating current Streaming, 1280x960 45 fps IDD –95115 mA
I/O digital operating current Streaming, 1280x960 45 fps IDD_IO – 35 40 mA
Analog operating current Streaming, 1280x960 45 fps IAA – 65 75 mA
Pixel supply current Streaming, 1280x960 45 fps IAA_PIX – 15 20 mA
PLL supply current Streaming, 1280x960 45 fps IDD_PLL – 7 15 mA
Digital operating current Streaming, 720p 60 fps IDD –95115mA
I/O digital operating current Streaming, 720p 60 fps IDD_IO – 35 40 mA
Analog operating current Streaming, 720p 60 fps IAA – 61 75 mA
Pixel supply current Streaming, 720p 60 fps IAA_PIX – 15 20 mA
PLL supply current Streaming, 720p 60 fps IDD_PLL – 7 15 mA
MT9M024_DS Rev. G Pub. 4/15 EN 53 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Notes: 1. Operating currents are measured at the following conditions:
VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V
VDD = 1.8V
VDD_SLVS = 0.4V (LoVCM)
VDD_SLVS = 1.8V (HiVCM)
PLL Enabled and PIXCLK = 74.25 Mhz
TA = 25°C
Cload = 10pF Measured in dark
Table 21: Operating Currents in HiSPi Output and Linear Mode
Definition Condition Symbol Min Typ Max Unit
Digital Operating Current Streaming 1280x960 45 fps IDD –95115mA
I/O digital operating current Streaming 1280x960 45 fps IDD_IO – 100 150 A
Analog operating current Streaming 1280x960 45 fps IAA –3045mA
Pixel Supply Current Streaming 1280x960 45 fps IAA_PIX – 10 15 mA
PLL Supply Current Streaming 1280x960 45 fps IDD_PLL – 7 15 mA
SLVS Supply Current
Current LoVCM Mode
Streaming 1280x960 45 fps
IDD_SLVS – 8 15 mA
Current HiVCM Mode
Streaming 1280x960 45 fps
–1625mA
Digital Operating Current Streaming 720p 60 fps IDD –95115mA
I/O digital operating current Streaming 720p 60 fps IDD_IO – 100 150 A
Analog operating current Streaming 720p 60 fps IAA –3045mA
Pixel Supply Current Streaming 720p 60 fps IAA_PIX – 10 15 mA
PLL Supply Current Streaming 720p 60 fps IDD_PLL – 7 15 mA
SLVS Supply Current
Current LoVCM Mode
Streaming 720p 60 fps
IDD_SLVS – 8 15 mA
Current HiVCM Mode
Streaming 1280x960 60 fps
–1625mA
MT9M024_DS Rev. G Pub. 4/15 EN 54 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Notes: 1. Operating currents are measured at the following conditions:
VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8 V
VDD = 1.8 V
VDD_SLVS = 0.4 V (LoVCM)
VDD_SLVS = 1.8 V (HiVCM)
PLL Enabled and PIXCLK=74.25 MHz
TA = 25°C
Cload = 10 pF Measured in dark
Table 22: Operating Current in HiSPi Output and HDR Mode
Definition Condition Symbol Min Typ Max Unit
Digital Operating Current Streaming 1280x960 45 fps IDD – 115 130 mA
I/O digital operating current Streaming 1280x960 45 fps IDD_IO – 100 150 A
Analog operating current Streaming 1280x960 45 fps IAA –6575mA
Pixel Supply Current Streaming 1280x960 45 fps IAA_PIX – 15 20 mA
PLL Supply Current Streaming 1280x960 45 fps IDD_PLL – 7 15 mA
SLVS Supply Current
Current LoVCM Mode
Streaming 1280x960 45 fps
IDD_SLVS – 8 15 mA
Current HiVCM Mode
Streaming 1280x960 45 fps
–1625mA
Digital Operating Current Streaming 720p 60 fps IDD – 115 130 mA
I/O digital operating current Streaming 720p 60 fps IDD_IO – 100 150 A
Analog operating current Streaming 720p 60 fps IAA –6575mA
Pixel Supply Current Streaming 720p 60 fps IAA_PIX – 15 20 mA
PLL Supply Current Streaming 720p 60 fps IDD_PLL – 7 15 mA
SLVS Supply Current
Current LoVCM Mode
Streaming 720p 60 fps
IDD_SLVS – 8 15 mA
Current HiVCM Mode
Streaming 1280x960 60fps
–1625mA
MT9M024_DS Rev. G Pub. 4/15 EN 55 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Notes: 1. Analog – VAA + VAA_PIX + VDD_PLL
2. Digital – VDD + VDD_IO
Figure 34: Power Supply Rejection Ratio
Table 23: Standby Current Consumption
Definition Condition Symbol Min Typ Max Unit
Hard standby (clock off) Analog, 2.8 V –– 30 100 μA
Digital, 1.8 V – – 85 2500 μA
Hard standby (clock on) Analog, 2.8 V – – 30 100 μA
Digital, 1.8 V ––1.55 4 mA
Soft standby (clock off) Analog, 2.8 V –– 85 100 μA
Digital, 1.8 V – – 85 2500 μA
Soft standby (clock on) Analog, 2.8 V –– 30 100 μA
Digital, 1.8 V ––1.55 4 mA
0
10
20
30
40
50
60
70
1000 10000 100000 1000000
P
S
R
R
(
d
B
)
Frequency(Hz)
PowerSupplyRejectionRatio
MT9M024_DS Rev. G Pub. 4/15 EN 56 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
HiSPi Electrical Specifications
The HiSPi transmitter electrical specifications are listed at 700 MHz.
Table 24: Input Voltage and Current (HiSPi Power Supply 0.4 V)
Measurement Conditions: Max Freq 700 MHz
Parameter Symbol Min Typ Max Unit
Supply current (PWRHiSPi)
(driving 100 load)
IDD_SLVS – 10 15 A
HiSPi common mode voltage
(driving 100 load)
VCMD VDD_SLVS x 0.45 VDD_SLVS/2 VDD_SLVS x 0.55 V
HiSPi differential output voltage
(driving 100 load)
|VOD|VDD_SLVS x 0.36 VDD_SLVS/2 VDD_SLVS x 1.64 V
Change in VCM between logic 1 and 0 VCM 25 mV
Change in |VOD| between logic 1 and
0
|VOD|25mV
Vod noise margin NM -30 30
Difference in VCM between any two
channels
|VCM|50mV
Difference in VOD between any two
channels
|VOD|100mV
Common-mode AC voltage (pk)
without VCM cap termination
VCM_ac 50 mV
Common-mode AC voltage (pk) with
VCM cap termination
VCM_ac 25 mV
Max overshoot peak |VOD|VOD_ac 1.2*|VOD|V
Max overshoot Vdiff pk-pk Vdiff_pkpk 2.4*|VOD|V
Eye Height Veye 0.5*VDD_SLVS
Single-ended output impedance Ro 35 50 70
Output impedance mismatch Ro 20 %
Table 25: Input Voltage and Current (HiSPi Power Supply 1.8 V)
Measurement Conditions: Max Freq 700 MHz
Parameter Symbol Min Typ Max Unit
Supply current (PWRHiSPi)
(driving 100 load)
IDD_HiVCM – 15 25 mA
HiSPi common mode voltage (driving 100 load) VCMD 0.76 0.9 1.07 V
HiSPi differential output voltage (driving 100
load)
|VOD| 200 280 350 V
Change in VCM between logic 1 and 0 VCM 25
Change in |VOD| between logic 1 and 0 VOD|25
VOD noise margin NM -30 30
Difference in VCM between any two channels VCM|50
Difference in VOD between any two channels VOD|100
Common-mode AC voltage (pk) without VCMcap
termination
VCM_ac 50
Common-mode AC voltage (pk) with VCM cap
termination
VCM_ac 30
MT9M024_DS Rev. G Pub. 4/15 EN 57 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Figure 35: Differential Output Voltage for Clock or Data Pairs
Notes: 1. One UI is defined as the normalized mean time between one edge and the following edge of the
clock.
2. Taken from 0V crossing point w/ DLL off.
3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance
may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum
0.3UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any
edges.
5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY
between any edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the
absolute time between the two complementary edges at mean VCM point.
Max overshoot peak |VOD|VOD_ac 1.2*|VOD|
Max overshoot Vdiff pk-pk Vdiff_pkpk 2.4*|VOD|V
Eye Height Veye 320
Single-ended Output impedance Ro 40 70 100
Output impedance mismatch Ro 20 %
Table 26: Rise and Fall Times
Measurement Conditions: HiSPi Power Supply 0.4V or 1.8V, Max Freq 700 MHz
Parameter Symbol Min Typ Max Unit
Data Rate 1/UI 280 – 700 Mb/s
Max setup time from transmitter TxPRE 0.3 – – UI1
Max hold time from transmitter TxPost 0.3 – – UI
Clock jitter (RMS) CLKJITTER – 50 – ps
Rise time (20% - 80%) RISE – 0.325UI –
Fall time (20% - 80%) FALL 150ps 0.3 UI –
Clock duty PLL_DUTY 45 50 55 %
Bitrate Period tpw 1.43 3.57 ns1
Eye Width teye 0.3 UI1, 2
Data Total jitter (pk pk)@1e-9 ttotaljit 0.2 UI1, 2
Clock Period Jitter(RMS) tckjit 50 ps2
Clock cycle to cycle jitter (RMS) tcyjit 100 ps2
Clock to Data Skew tchskew -0.1 0.1 UI1, 2
PHY-to-PHY Skew tPHYskew 2.1 UI1, 5
Table 25: Input Voltage and Current (HiSPi Power Supply 1.8 V)
Measurement Conditions: Max Freq 700 MHz
Parameter Symbol Min Typ Max Unit
0V Diff)
VDIFFmax
VDIFFmin
Output Signal is 'Cp - Cn' or 'Dp - D
MT9M024_DS Rev. G Pub. 4/15 EN 58 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Figure 36: Eye Diagram for Clock and Data Signals
Figure 37: Skew Within the PHY and Output Channels
CLKJITTER
T ri gger/ R eference
VdiffMax
Vdiff
UI/ 2 UI/ 2
Vdiff
TxPre TxPost
CLOCK MASK
DATA MASK
RISE
FALL
20%
80%
tCMPSKEW
VCMD
tCHSKEW1PHY
MT9M024_DS Rev. G Pub. 4/15 EN 59 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Power-On Reset and Standby Timing
Power-On Reset and Standby Timing
Power-Up Sequence
The recommended power-up sequence for the MT9M024 is shown in Figure 29. The
available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have
the separation specified below.
1. Turn on VDD_PLL power supply.
2. After 0–10s, turn on VAA and VAA_PIX power supply.
3. After 0–10s, turn on VDD_IO power supply.
4. After the last power supply is stable, enable EXTCLK.
5. Assert RESET_BAR for at least 1ms.
6. Wait 850000 EXTCLKs (for internal initialization into software standby).
7. Configure PLL, output, and image settings to desired values.
8. Wait 1ms for the PLL to lock.
9. Set streaming mode (R0x301A[2] = 1).
Figure 38: Power Up
VDD_PLL (2.8)
VAA_PIX
VAA (2.8)
VDD_IO (1.8/2.8)
VDD (1.8)
VDD_SLVS (0.4)
EXTCLK
RESET_B
t0
t1
t2
t3
tx
t4
t5 t6
Hard Reset Internal
Initialization
Software
Standby PLL Lock Streaming
MT9M024_DS Rev. G Pub. 4/15 EN 60 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Power-On Reset and Standby Timing
Notes: 1. Xtal settling time is component-dependent, usually taking about 10 – 100 ms.
2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard
reset is held down by RC circuit, then the RC time must include the all power rail settle time and
Xtal settle time.
3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered
before or at least at the same time as the others. If the case happens that VDD_PLL is powered after
other supplies then sensor may have functionality issues and will experience high current draw on
this supply.
Table 27: Power-Up Sequence
Definition Symbol Minimum Typical Maximum Unit
VDD_PLL to VAA/VAA_PIX3t0 0 10 – s
VAA/VAA_PIX to VDD_IO t1 0 10 – s
VDD_IO to VDD t2 0 10 – s
VDD to VDD_SLVS t3 0 10 – s
Xtal settle time tx – 301–ms
Hard Reset t4 12–– ms
Internal Initialization t5 850000 – – EXTCLKS
PLL Lock Time t6 1 – – ms
MT9M024_DS Rev. G Pub. 4/15 EN 61 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Power-On Reset and Standby Timing
Power-Down Sequence
The recommended power-down sequence for the MT9M024 is shown in Figure 30. The
available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have
the separation specified below. Power may be removed from all supplies simultaneously,
and a sudden loss of power on all rails does not cause damage or affect the lifetime of the
device.
1. Disable streaming if output is active by setting standby R0x301A[2] = 0
2. The soft standby state is reached after the current row or frame, depending on config-
uration, has ended.
3. Turn off VDD_SLVS.
4. Turn off VDD.
5. Turn off VDD_IO
6. Turn off VAA/VAA_PIX.
7. Turn off VDD_PLL.
Figure 39: Power Down
Note: t4 is required between power down and next power up time; all decoupling caps from regulators
must be completely discharged.
Table 28: Power-Down Sequence
Definition Symbol Minimum Typical Maximum Unit
VDD_SLVS to VDD t0 0 – – s
VDD to VDD_IO t1 0 – – s
VDD_IO to VAA/VAA_PIX t2 0 – – s
VAA/VAA_PIX to VDD_PLL t3 0 – – s
PwrDn until Next PwrUp Time t4 100 – – ms
VDD_IO (1.8/2.8)
t4
t 0
t1
t3
t2
EXTCLK
V
DD
_SLVS (0.4)
V
DD
(1.8)
V
AA
_PIX
V
AA
(2.8)
V
DD
_PLL (2.8)
Power Down until next Power up cycle
MT9M024_DS Rev. G Pub. 4/15 EN 62 ©Semiconductor Components Industries, LLC,2015
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Package Dimensions
Package Dimensions
Figure 40: 63-Ball iBGA Package Outline Drawing
MT9M024_DS Rev. G Pub. 4/15 EN 63 ©Semiconductor Components Industries, LLC,2015
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Package Dimensions
Note: All dimensions are in millimeters.
MT9M024_DS Rev. G Pub. 4/15 EN 64 ©Semiconductor Components Industries, LLC,2015.
MT9M024: 1/3-Inch CMOS Digital Image Sensor
Revision History
Revision History
Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/15/15
• Updated “Ordering Information” on page 2
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/27/15
• Converted to ON Semiconductor template
• Removed Confidential marking
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/22/13
• Updated temperature range in “General Description” on page 1
• Updated Figure 2: “Typical Configuration: Serial Four-Lane HiSPi Interface,” on
page 2
• Updated Figure 3: “Typical Configuration: Parallel Pixel Data Interface,” on page 3
• Updated “Pixel Array Structure” on page 7
• Updated Figure 6: “Pixel Color Pattern Detail (Top Right Corner),” on page 8
• Updated “Default Readout Order” on page 8
• Added “Digital Gain Control” on page 9
• Added “DLL Timing Adjustment” on page 13
• Updated “Exposure” on page 16
• Updated Equation 2 on page 16
• Updated Table 8, “Real-Time Context-Switch Registers,” on page 21
• Updated “PLL-Generated Master Clock” on page 22
• Updated “Hard Standby” on page 24
• Updated title of Figure 19: “Eight Pixels in Normal and Column Mirror Readout
Modes,” on page 25
• Added note at the end of “Embedded Data and Statistics” on page 29
• Updated “Embedded Data” on page 30
• Updated Figure 23: “Format of Embedded Statistics Output within a Frame,” on
page 31
• Updated “Column Triggering on Startup” on page 33
• Updated “Column Correction Retriggering Due to Mode Change” on page 33
• Updated “I/O Timing” on page 42
• Updated Figure 33: “I/O Timing Diagram,” on page 43
• Deleted Table 9, “I/O Timing Characteristics
• Added Table 11, “I/O Timing Characteristics (2.8V Vdd_IO)1,” on page 43
• Added Table 12, “I/O Timing Characteristics (1.8V Vdd_IO)1,” on page 44
• Added Table 13, “I/O Rise Slew Rate (2.8V Vdd_IO)1,” on page 44
• Added Table 14, “I/O Fall Slew Rate (2.8V Vdd_IO)1,” on page 45
• Added Table 15, “I/O Rise Slew Rate (1.8V Vdd_IO)1,” on page 45
• Updated Table 20, “Operating Current Consumption in Parallel Output and HDR
Mode,” on page 47
• Added Figure 34: “Power Supply Rejection Ratio,” on page 50
• Updated “Power-Up Sequence” on page 54
• Updated Table 27, “Power-Up Sequence,” on page 55
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/10/12
• Updated Table 1, “Pin Descriptions, 9 x 9 mm, 63-ball iBGA,” on page 5
• Updated Figure 4: “9 x 9 mm 63-Ball IBGA Package,” on page 4
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MT9M024: 1/3-Inch CMOS Digital Image Sensor
Revision History
MT9M024_DS Rev. G Pub. 4/15 EN 65 ©Semiconductor Components Industries, LLC,2015 .
• Updated “Hard Standby” on page 24
• Updated “Embedded Data and Statistics” on page 29
• Updated Table 11, “I/O Timing Characteristics (2.8V Vdd_IO)1,” on page 43
• Updated Table 24, “Input Voltage and Current (HiSPi Power Supply 0.4 V),” on page 51
• Updated Table 25, “Input Voltage and Current (HiSPi Power Supply 1.8 V),” on page 51
• Updated Table 26, “Rise and Fall Times,” on page 52
• Deleted old Table 20, “Channel, PHY, and Intra-PHY Skew
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/29/11
• Updated Table 1, “Key Parameters,” on page 1
• Updated Table 2, “Available Part Numbers,” on page 1
• Updated “Exposure” on page 16
• Updated “HDR Specific Exposure Settings” on page 19
• Updated “Motion Compensation” on page 20
• Updated “PLL-Generated Master Clock” on page 22
• Table 8, “Real-Time Context-Switch Registers,” on page 21Updated “Hard Standby”
on page 24
• Updated Figure 19: “Eight Pixels in Normal and Column Mirror Readout Modes,” on
page 25
• Updated Table 17, “DC Electrical Characteristics,” on page 46
• Updated notes for Table 19, “Operating Current Consumption in Parallel Output and
Linear Mode ,” on page 47 and Table 20, “Operating Current Consumption in Parallel
Output and HDR Mode,” on page 47
• Updated Table 22, “Operating Current in HiSPi Output and HDR Mode,” on page 49
• Updated Table 23, “Standby Current Consumption ,” on page 50
• Updated conditions for Table 26, “Rise and Fall Times,” on page 52 and Table 22,
“Channel, PHY, and Intra-PHY Skew,” on page 45
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/19/10
• Updated Table 1, “Key Parameters,” on page 1
• Updated Table 10, “Two-Wire Serial Bus Characteristics,” on page 41
• Updated storage temperature max in Table 18, “Absolute Maximum Ratings,” on
page 46
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/20/10
•Initial release
