ATDS1130PC - Atmel Corporation

Features

•Comprehensive CPLD/PLD Design Environment

•User-friendly Microsoft Windows™ Interface (Win 95, Win 98, Win NT)

•Powerful Project Navigator

–Utilizes Intelligent Device Fitters for Automatic Logic Synthesis and

Device Resource Assignment

–Allows Design Specifica tion wi th Schematic Entry or the ABEL-HDL

•Integrated ABEL Text Design Entry and Synthesis

–Friendly Windows-based User Interface is Easy to Learn and Use

–ABEL-HDL Design Entry Provides Detailed Support for

Programmable Logic Devices

–Full Hierarchical Support Makes Large Designs Easier to Manage; Large

All-behavioral Designs can be Created without Drawing any Schematics

•Integrated Verilog™ Timing Simulator (Optional)

–Fast, Functional Simulation is Performed Directly from the Schematic

or Behavioral Source File, Providing Quick Feedback on Logic Errors

as the Design is Entered

–Full Timing Simulation with Delay-annotated Models Provides

Comprehensive Support for Timing Problems in Routed Devices

–Logic-analyzer-like Waveform Viewer Provides Flexible Results Viewing,

and Updates Every Time you Single-step the Simulator

–Cross-probing Capabilities between the Schematic and Waveform Viewer Tie

Simulation Results Directly Back to the Source Design, Making Results

Easier to Interpret

–Interactive Debugging Provides Forc e/Preset/Monitor Acces s to all of the Design’s

Signals, for Fast and Easy, On-the-fly Changes

–Industry-standard Verilog HDL Simulation Language Ensures Timely

Support for New Device Architectures

•IEEE 1076 VHDL Synthesis and Simulation (Optional)

Description

Atmel- Synario is an i ntegrated C PLD/PLD desi gn tool. It sup ports all propri etary, and

JEDEC standard devices offered by Atmel. The usual CAE tool capability is combined

with CPLD specific functionality. A tightly integrated Windows environment gives the

user a friendly, and powerful interface. The system combines schematic and behav-

ioral entry methods. Functional and timing simulation are also supported. An

intelli gent des ign manage r, superv ises file manipu lation an d controls the design flow.

This function allows a user to move quickly from one design to another and evaluate

different implementations for an optimal solution.

Atmel-Synario

CPLD/PLD

Design

Software

ATDS1100PC

ATDS1120PC

ATDS1130PC

ATDS1140PC

Rev. 0714C–09/99

ATDS1100PC/1120PC/1130PC/1140PC

Pro j ect Navig a t o r

Atmel-Synario Project Navigator is the core of the system.

It is a powerful and simple design flow controller. Built-in

intel ligence , gives fil e and run op tion know ledge for each

device. Select the ATF1500 and all the steps required to

design, simula te, compile and fit will appear. Change to

ATF22V10 and the steps change accordingly. You may

even choose to design without a particular architecture and

pick it later in the design process (Virtual or Generic

Device).

Project Navigator also tracks and displays status of the

design process. Each design step is clearly delineated, and

can be performed independently of the complete flow. Or,

you can perform a complete compilation in a single step.

Project Navigator will netlist all the schematics in your

design, and compile, optimize, and synthesize all the

behavioral modules. If only a portion of the design changes

(a module or a single schematic), you don’t have to netlist

and compile the whole design. Project Navigator knows

everyt hing else is cu rrent by keeping track of all the files .

Finally, processing options are intelligently defaulted (but

can also be customized). Detailed device-specific help is

available for each step.

ATDS1100PC/1120PC/1130PC/1140PC

ECS – Schematic Entry

Atmel-Synario schematic tool is a MS Windows-based

environment. Schematic Capture in Navigator mode gives

an onlin e view of the connectivity database. Push into a

lower-level schematic and upper level signal names are

visible below. Highli ght a net and you can follow it up a nd

down the hierarchy. Run a design-rule check, and errors

appear in a box; click on an error, and the schematic jumps

to the page and lo cation of the erro r. Whe never a new

device is targeted, libraries are changed automatically.

Device-independent Design

Device-independent design is a useful design technique. It

frees the designer from architectural knowledge, and

allows the best device fit to each application. Until now

each architecture required a different library, with different

symbol s. Atmel -Synari o solves thi s problem with its power-

ful and unique device-independent library. Using the

standard building blocks the device-independent library

provides, you ca n draw entire sc hematics that can be tar -

geted to any device. The sy mbols have all the “smarts” to

map efficiently and simulate correctly in any target device.

You can build device-independent soft macros the same

way. I f you desire architect ure specific functions, simply

use the Atmel-Specific library for more effici ent utilization.

Now going from a 5 ns ATF16V8C to a high-density

ATF1508 CPLD is only a compilation away.

ATDS1100PC/1120PC/1130PC/1140PC

ABEL Integration into Atmel-Synar io:

Behavioral Entry and Simulation

ABEL is one of the tools integrated into Atmel-Synario.

Therefore, importing existing PLD designs into a larger

design s is stra ight forw ard. Addi ng new logi c, and reim ple-

menting into a larger CPLD is simple. Experienced ABEL

users can ge t star te d using S yn ario A BEL tool , then gra du-

ally use more of the extended Atmel-Synario capability.

Atme l-Synari o Behav ioral Entry has hierar chical capabi lity.

Large, al l-behav iora l des igns can be e ntered wit hout draw-

ing any schematics. Device-specific logic synthesis allows

easy design migration to all supported devices.

Fastest way to migrate from simple PLDs to CPLDs:

•Use existing leg ac y desig ns in new des igns

•Convert from one architecture to another

•Upgrade designs to new technologies

ABEL – Functional Sim ulatio n

ABEL has built-in functional simulation capability. This

allows for early design cycle verification (before fitting).

This also enables quick design on small projects. Full

Synari o functio nality w ith legacy ABEL d esigns is also a n

advantage of ABEL functional simulation.

VHDL – Synthesis Option

Atmel-Synario gives you full VHDL support. IEEE-1076

compliant synthesis is tightly integrated into the environ-

ment, wh ich all ows quick impl ementa tion in to all suppor ted

devices. Atmel -Synario V HDL provides a full package of

IEEE-1076 analysis, synthesis, and source-level simulation

capab ility. Even mixi ng VHDL en try with ABE L and sche-

matics is a simple task. A full capability VHDL design

environment can be created with an additional functional

simulator.

ATDS1100PC/1120PC/1130PC/1140PC

Verilog – Functional and Timing Simulation Option

Verilog simulat ion is anothe r of the Atmel-Synario tools.

This standard simulation package gives functional and full

timin g simul ation . The sim ulati on pac kage is fully c ompat i-

ble with Open-Verilog, which allows construction of

powerful test benches and result analysis and summary

functions. Atmel-Synario Simulation creates simula tion

models dire ctly f rom S ynario ’s sourc e files. Th is, couple d

with an extremely fast simulator, qui ckly tells you whether

your logic is correc t while you’r e entering it – even before

the synthesis and fitting steps. After fitting to a specific

device , the us er may v erify t he d esired timing . Solve tough

timing problems wi th full delay-annotated simulation mod-

els created by the fitter.

Atme l-Synari o Simul ator doesn ’t n eed a rch itec ture sp ecif ic

libraries and models. Simply identify which portion of the

design you want to simulate and the stimulus you want

applied. T he n p re ss “go”. In ba tch m ode , y ou can start an d

stop simulation from the control panel. Or you can explore

your circuit’s functionality interactive ly. Verilog language

support also assures timely device support.

The Verilog simulation option i ncludes a waveform viewer

display that resembles a logic analyzer format. The wave-

form viewer updates whenever you simulate, even after

each step of single-step s ession. Once a simulatio n runs,

the values at the cursor in the waveform viewer are

“dynamically backnotated” into the sc hematic. This allows

you to debug your hierarchical design by viewing the logic

values of the bur ie d ne ts i n th e sc he mat ic as you mov e th e

cursor in the wavefor m viewer. To v iew a new s ignal, just

“probe” the new in the sc hem atic and the signa l wil l app ear

in the waveform viewer.

Note: Cross-probing between the schematic and waveform viewer ties simulation results directly back to the source for faster and

easier interpretation. Results update each time you single-step the simulator.

Multiple entry methods:

•Use the best one fir the application

•Mix methods for efficient design

•Quick translation of existing designs

ATDS1100PC/1120PC/1130PC/1140PC

Wavefor m Ed itor/ Viewer

Fast simulation analysis and debug are at your fingertips

with waveform editor. The powerful waveform editor

enables simple stimulus generation, and easy result

viewing. It’s simple to add, delete, or move signals and

show buses as a group. The viewer display is updated

while simulating (for each simulation step).

Peak VHDL – Simulator Option

The Accolade Peak VHDL professional edition simulator is

a powerful, easy-to-use system for design entry and simu-

lation us ing VHDL. The prod uct includ es advanced, hig h-

speed VHDL analyzer and elaborator, and support for

IEEE-1076.1987 and IEEE-1076.1993 language

standards. Built-in, accelerated support for IEEE-1164

standard logic is included as well as support for IEEE-

1076.3 (synthesis/numeric) package. A VHDL hierarchy

browser, waveform interface and context-sensitive VHDL

code editor add to the powerful capabilities of this option.

ATDS1100PC/1120PC/1130PC/1140PC

Ordering Information

Part Number System Descriptio n

ATDS1100PC Atmel-Synario Basic Schematic and ABEL entry with fitters

ATDS1120PC Atmel-Synario Verilog Simulation (Option) Verilog functional and timing simulator

ATDS1130PC Atmel-Synario VHDL Synthesis (Option) Synthesis - IEEE-1076.1993

ATDS1140PC Atmel-Synario VHDL Simulation (Option) Peak VHDL simulator

System Requirements

Environment Windows (95, 98 or NT)

RAM 16MB

Hard Disk 80MB

Processor Intel or compatible Pentium

System Peripherals

Parallel Port For security key

Microsoft Mouse or compatible Pointing device

CD-ROM For program loading and updates

3-1/2" disk driv e For progra m updates

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life support devices or systems.

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Printed on recycled paper.

0714C–09/99/xM

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