ATDS1100PC/1120PC/1130PC/1140PC
5
Verilog – Functional and Timing Simulation Option
Verilog simulat ion is anothe r of the Atmel-Synario tools.
This standard simulation package gives functional and full
timin g simul ation . The sim ulati on pac kage is fully c ompat i-
ble with Open-Verilog, which allows construction of
powerful test benches and result analysis and summary
functions. Atmel-Synario Simulation creates simula tion
models dire ctly f rom S ynario ’s sourc e files. Th is, couple d
with an extremely fast simulator, qui ckly tells you whether
your logic is correc t while you’r e entering it – even before
the synthesis and fitting steps. After fitting to a specific
device , the us er may v erify t he d esired timing . Solve tough
timing problems wi th full delay-annotated simulation mod-
els created by the fitter.
Atme l-Synari o Simul ator doesn ’t n eed a rch itec ture sp ecif ic
libraries and models. Simply identify which portion of the
design you want to simulate and the stimulus you want
applied. T he n p re ss “go”. In ba tch m ode , y ou can start an d
stop simulation from the control panel. Or you can explore
your circuit’s functionality interactive ly. Verilog language
support also assures timely device support.
The Verilog simulation option i ncludes a waveform viewer
display that resembles a logic analyzer format. The wave-
form viewer updates whenever you simulate, even after
each step of single-step s ession. Once a simulatio n runs,
the values at the cursor in the waveform viewer are
“dynamically backnotated” into the sc hematic. This allows
you to debug your hierarchical design by viewing the logic
values of the bur ie d ne ts i n th e sc he mat ic as you mov e th e
cursor in the wavefor m viewer. To v iew a new s ignal, just
“probe” the new in the sc hem atic and the signa l wil l app ear
in the waveform viewer.
Note: Cross-probing between the schematic and waveform viewer ties simulation results directly back to the source for faster and
easier interpretation. Results update each time you single-step the simulator.
Multiple entry methods:
•Use the best one fir the application
•Mix methods for efficient design
•Quick translation of existing designs