SN74LVC1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES220S - APRIL 1999 - REVISED NOVEMBER 2007 FEATURES 1 * Available in the Texas Instruments NanoFreeTM Package * Supports 5-V VCC Operation * Inputs Accept Voltages to 5.5 V * Max tpd of 4 ns at 3.3 V * Low Power Consumption, 10-A Max ICC * 24-mA Output Drive at 3.3 V * Ioff Supports Partial-Power-Down Mode Operation * 2 DBV PACKAGE (TOP VIEW) D 1 5 DCK PACKAGE (TOP VIEW) D VCC CLK CLK 2 GND 3 GND 4 * Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) 1 5 DRL PACKAGE (TOP VIEW) VCC 2 3 4 D 1 CLK 2 GND 3 5 VCC YZP PACKAGE (BOTTOM VIEW) GND CLK 4 Q D 3 4 Q 2 1 5 VCC Q Q See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output. NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2007, Texas Instruments Incorporated SN74LVC1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES220S - APRIL 1999 - REVISED NOVEMBER 2007 ORDERING INFORMATION TA PACKAGE (1) (2) NanoFreeTM - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) -40C to 85C SOT (SOT-23) - DBV SOT (SC-70) - DCK SOT (DOT-553) - DRL (1) (2) (3) ORDERABLE PART NUMBER Reel of 3000 SN74LVC1G79YZPR Reel of 3000 SN74LVC1G79DBVR Reel of 250 SN74LVC1G79DBVT Reel of 3000 SN74LVC1G79DCKR Reel of 250 SN74LVC1G79DCKT Reel of 4000 SN74LVC1G79DRLR TOP-SIDE MARKING (3) _ _ _CR_ C79_ CR_ CR_ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free). FUNCTION TABLE INPUTS OUTPUT Y CLK D H H L L L X Q0 LOGIC DIAGRAM (POSITIVE LOGIC) CLK 2 C C C 4 TG C C Q C C D 2 1 TG TG TG C C C Submit Documentation Feedback Copyright (c) 1999-2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79 SN74LVC1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES220S - APRIL 1999 - REVISED NOVEMBER 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range -0.5 6.5 V VI Input voltage range (2) -0.5 6.5 V -0.5 6.5 V -0.5 VCC + 0.5 (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off state VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current 50 mA 100 mA Continuous current through VCC or GND JA Tstg (1) (2) (3) (4) Package thermal impedance (4) DBV package 206 DCK package 252 DRL package 142 YZP package 132 Storage temperature range -65 150 V C/W C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright (c) 1999-2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79 3 SN74LVC1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES220S - APRIL 1999 - REVISED NOVEMBER 2007 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 1.65 5.5 1.5 VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V 0.7 x VCC 0.35 x VCC VCC = 1.65 V to 1.95 V Low-level input voltage V V 2 VCC = 4.5 V to 5.5 V VIL UNIT 0.65 x VCC VCC = 1.65 V to 1.95 V VIH MIN VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 V 0.3 x VCC VCC = 4.5 V to 5.5 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 1.65 V -4 VCC = 2.3 V IOH High-level output current -8 -16 VCC = 3 V VCC = 4.5 V -32 VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current t/v Input transition rise or fall rate 8 16 VCC = 3 V 32 VCC = 1.8 V 0.15 V, 2.5 V 0.2 V 20 VCC = 3.3 V 0.3 V 10 (1) 4 Operating free-air temperature mA 24 VCC = 4.5 V VCC = 5 V 0.5 V TA mA -24 ns/V 5 -40 85 C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright (c) 1999-2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79 SN74LVC1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES220S - APRIL 1999 - REVISED NOVEMBER 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -100 A VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = -8 mA 2.3 V 1.9 4.5 V IOL = 100 A 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 32 mA All inputs 3.8 0.4 3V IOL = 24 mA II 2.3 IOH = -32 mA IOL = 16 mA VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ICC One input at VCC - 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND (1) All typical values are at VCC = 3.3 V, TA = 25C. V 0.55 4.5 V 0.55 0 to 5.5 V 10 A 0 10 A 1.65 V to 5.5 V 10 A 500 A VI = 5.5 V or GND Ioff UNIT V 2.4 3V IOH = -24 mA TYP (1) MAX VCC - 0.1 IOH = -4 mA IOH = -16 mA VOL MIN 3 V to 5.5 V 3.3 V 4 pF Timing Requirements over operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time before CLK th Hold time, data after CLK VCC = 1.8 0.15 V VCC = 2.5 0.2 V MIN MIN MAX 160 VCC = 3.3 V 0.3 V MAX MIN 160 MAX VCC = 5 V 0.5 V MIN 160 160 2.5 2.5 2.5 2.5 Data high 2.2 1.4 1.3 1.2 Data low 2.6 1.4 1.3 1.2 0.3 0.4 1 0.5 Submit Documentation Feedback Copyright (c) 1999-2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79 UNIT MAX MHz ns ns ns 5 SN74LVC1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES220S - APRIL 1999 - REVISED NOVEMBER 2007 Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) CLK Q fmax tpd VCC = 1.8 V 0.15 V MIN MAX 160 2.5 VCC = 2.5 V 0.2 V MIN MAX 160 9.1 VCC = 3.3 V 0.3 V MIN MAX 160 1.2 6 VCC = 5 V 0.5 V MIN 160 1 4 UNIT MAX MHz 0.8 3.8 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd VCC = 1.8 V 0.15 V MIN MAX 160 CLK Q 3.9 VCC = 2.5 V 0.2 V MIN MAX 160 9.9 2 VCC = 3.3 V 0.3 V MIN MAX 160 7 1.7 VCC = 5 V 0.5 V MIN 160 5 UNIT MAX 1 MHz 4.5 ns Operating Characteristics TA = 25C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 26 26 27 30 Submit Documentation Feedback UNIT pF Copyright (c) 1999-2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79 SN74LVC1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES220S - APRIL 1999 - REVISED NOVEMBER 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 15 pF 15 pF 15 pF 15 pF 1 MW 1 MW 1 MW 1 MW 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH - VD VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright (c) 1999-2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79 7 SN74LVC1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES220S - APRIL 1999 - REVISED NOVEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL tPLZ VLOAD/2 VM tPZH VM VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH - VD VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright (c) 1999-2007, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79 PACKAGE OPTION ADDENDUM www.ti.com 6-Jan-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC1G79DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G79YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Jan-2010 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC1G79 : * Enhanced Product: SN74LVC1G79-EP NOTE: Qualified Version Definitions: * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G79DBVR SOT-23 DBV 5 3000 178.0 9.2 SN74LVC1G79DBVR SOT-23 DBV 5 3000 178.0 SN74LVC1G79DBVT SOT-23 DBV 5 250 178.0 SN74LVC1G79DBVT SOT-23 DBV 5 250 SN74LVC1G79DCKR SC70 DCK 5 SN74LVC1G79DCKR SC70 DCK SN74LVC1G79DCKT SC70 DCK SN74LVC1G79DCKT SC70 SN74LVC1G79DRLR SN74LVC1G79DRLR SN74LVC1G79YZPR 3.3 3.2 1.55 4.0 8.0 Q3 9.0 3.23 3.17 1.37 4.0 8.0 Q3 9.2 3.3 3.2 1.55 4.0 8.0 Q3 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SOT DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3 SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G79DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G79DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G79DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G79DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G79DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G79DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G79DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G79DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G79DRLR SOT DRL 5 4000 180.0 180.0 30.0 SN74LVC1G79DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74LVC1G79YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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