100350 Low Power Hex D-Latch General Description Features The 100350 contains six D-type latches with true and complement outputs, a pair of common Enables (Ea and Eb), and a common Master Reset (MR). A Q output follows its D input when both Ea and Eb are LOW. When either Ea or Eb (or both) are HIGH, a latch stores the last valid data present on its D input before Ea or Eb went HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 kX pull-down resistors. Y Y Y Y 20% power reduction of the 100150 2000V ESD protection Pin/function compatible with 100150 Voltage compensated operating range e b 4.2V to b 5.7V Logic Symbol Pin Names D0 -D5 Ea, Eb MR Q0 -Q5 Q0 -Q5 Description Data Inputs Common Enable Inputs (Active LOW) Asynchronous Master Reset Input Data Outputs Complementary Data Outputs TL/F/9884 - 10 Connection Diagrams 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak TL/F/9884 - 3 TL/F/9884 - 2 TL/F/9884-1 C1995 National Semiconductor Corporation TL/F/9884 RRD-B30M115/Printed in U. S. A. 100350 Low Power Hex D-Latch July 1992 Logic Diagram TL/F/9884 - 4 Truth Tables (Each Latch) Asynchronous Operation Latch Operation Inputs Outputs Inputs Outputs Dn Ea Eb MR Qn Dn Ea Eb MR Qn L H X X L L H X L L X H L L L L L H Latched* Latched* X X X H L *Retains data present before E positive transition H e HIGH Voltage Level L e LOW Voltage Level X e Don't Care 2 Absolute Maximum Ratings Recommended Operating Conditions Above which the useful life may be impaired. (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65 C to a 150 C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) Case Temperature (TC) Commercial Military 0 C to a 85 C b 55 C to a 125 C Supply Voltage (VEE) b 5.7V to b 4.2V a 175 C a 150 C b 7.0V to a 0.5V VEE to a 0.5V b 50 mA t 2000V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics VEE e b4.5V to b5.7V, VCC e VCCA e GND, TC e 0 C to a 85 C (Note 3) Symbol Parameter Min Typ Max VOH Output HIGH Voltage b 1025 b 955 b 870 VOL Output LOW Voltage b 1830 b 1705 b 1620 VOHC Output HIGH Voltage b 1035 VOLC Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IIH Input HIGH Current MR Dn Ea, Eb IEE Power Supply Current Units Conditions mV VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V mV VIN e VIH (Min) or VIL (Max) Loading with 50X to b2.0V b 1610 b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs mA VIN e VIL (Min) 240 240 240 mA VIN e VIH (Max) b 44 b 44 mA 0.50 b 89 b 93 Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V Note 3: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. 3 Commercial Version (Continued) DIP AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e 0 C Max Min TC e a 25 C TC e a 85 C Min Max Min Max 0.50 1.40 0.50 1.50 Units Conditions tPLH tPHL Propagation Delay Dn to Output (Transparent Mode) 0.50 tPLH tPHL Propagation Delay Ea, Eb to Output 0.75 1.85 0.75 1.85 0.75 2.05 ns tPLH tPHL Propagation Delay MR to Output 0.90 2.10 0.90 2.10 0.90 2.10 ns Figures 1 and 3 tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.35 1.30 0.35 1.30 0.35 1.30 ns Figures 1 and 2 ts Setup Time D0 - D5 MR (Release Time) 1.00 1.60 1.00 1.60 1.00 1.60 ns th Hold Time, D0 - D5 0.40 0.40 0.40 ns Figure 4 tpw(L) Pulse Width LOW Ea, Eb 2.00 2.00 2.00 ns Figure 2 tpw(H) Pulse Width HIGH, MR 2.00 2.00 2.00 ns Figure 3 1.40 ns Figures 1 and 2 Figures 3 and 4 PCC and Cerpak AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e a 25 C TC e a 85 C Min TC e 0 C Max Min Max Min Max Units Conditions tPLH tPHL Propagation Delay Dn to Output (Transparent Mode) 0.50 1.20 0.50 1.20 0.50 1.30 ns tPLH tPHL Propagation Delay Ea, Eb to Output 0.75 1.65 0.75 1.65 0.75 1.85 ns tPLH tPHL Propagation Delay MR to Output 0.90 1.90 0.90 1.90 0.90 1.90 ns Figures 1 and 3 tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1 and 2 ts Setup Time D0 - D5 MR (Release Time) 0.90 1.50 0.90 1.50 0.90 1.50 ns th Hold Time, D0 - D5 0.30 0.30 0.30 ns Figure 4 tpw(L) Pulse Width LOW Ea, Eb 2.00 2.00 2.00 ns Figure 2 tpw(H) Pulse Width HIGH, MR 2.00 2.00 2.00 ns Figure 3 Figures 1 and 2 4 Figures 3 and 4 Military VersionPreliminary DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b55 C to a 125 C Parameter Min Max Units TC VOH Symbol Output HIGH Voltage b 1025 b 870 mV 0 C to a 125 C b 1085 b 870 mV b 55 C VOL Output LOW Voltage b 1830 b 1620 mV 0 C to a 125 C b 1830 b 1555 mV b 55 C mV 0 C to a 125 C VOHC Output HIGH Voltage b 1035 b 1085 VOLC VIN e VIH(Max) or VIL (Min) Loading with 50X to b2.0V 1, 2, 3 VIN e VIH(Min) or VIL (Min) Loading with 50X to b2.0V 1, 2, 3 mV b 55 C mV 0 C to a 125 C b 1555 mV b 55 C b 1165 b 870 mV b 55 C to a 125 C Guaranteed HIGH Signal for All Inputs 1, 2, 3, 4 b 1830 b 1475 mV b 55 C to a 125 C Guaranteed LOW Signal for All Inputs 1, 2, 3, 4 mA b 55 C to a 125 C VEE e b4.2V VIN e VIL (Min) 0 C to a 125 C Output LOW Voltage Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IIH Input HIGH Current MR Dn Ea, Eb 300 250 520 mA MR Dn Ea, Eb 450 350 750 mA b 55 C b 64 mA b 55 C to a 125 C Power Supply Current Notes b 1610 VIH IEE Conditions 0.50 b 138 1, 2, 3 VEE e b5.7V VIN e VIH (Max) 1, 2, 3 Inputs Open 1, 2, 3 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at b 55 C, a 25 C, and a 125 C, Subgroups 1, 2, 3, 7, and 8. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b 55 C, a 25 C, and a 125 C, Subgroups A1, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input condition and testing VOH/VOL. 5 Military Version-Preliminary (Continued) AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e b55 C TC e a 25 C TC e a 125 C Min Max Min Max Min Max 1.50 0.50 1.40 0.50 1.50 Units Conditions tPLH tPHL Propagation Delay Dn to Output (Transparent Mode) 0.45 tPLH tPHL Propagation Delay Ea, Eb to Output 0.75 2.05 0.75 1.85 0.75 2.05 ns tPLH tPHL Propagation Delay MR to Output 0.80 2.40 0.90 2.40 0.90 2.60 ns Figures 1 and 3 tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.45 1.70 0.45 1.60 0.45 1.60 ns Figures 1 and 2 tS Setup Time D0-D5 MR (Release Time) 0.70 2.10 0.70 2.10 0.70 2.10 ns Figures 1 and 2 tH Hold Time, D0-D5 0.70 0.70 0.70 ns Figure 4 tpw(L) Pulse Width LOW Ea, Eb 2.00 2.00 2.00 ns Figure 2 tpw(L) Pulse Width HIGH, MR 2.00 2.00 2.00 ns Figure 3 Notes ns Figures 1 and 2 1, 2, 3 4 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at a 25 C, temperature only, Subgroup A9. Note 3: Sample tested (Method 5005, Table I) on each Mfg. lot at a 25 C, Subgroup A9, and at a 125 C, and b 55 C temp., Subgroups A10 and A11. Note 4: Not tested at a 25 C, a 125 C, and b 55 C temperature (design characterization data). 6 Test Circuit Notes: VCC, VCCA e a 2V, VEE e b 2.5V L1 and L2 e equal length 50X impedance lines RT e 50X terminator internal to scope Decoupling 0.1 mF from GND to VCC and VEE All unused outputs are loaded with 50X to GND CL e Fixture and stray capacitance s 3 pF TL/F/9884 - 5 FIGURE 1. AC Test Circuit Switching Waveforms TL/F/9884 - 6 FIGURE 2. Enable Timing 7 Switching Waveforms (Continued) TL/F/9884 - 7 FIGURE 3. Reset Timing TL/F/9884 - 8 Notes: ts is the minimum time before the transition of the enable that information must be present at the data input. th is the minimum time after the transition of the enable that information must remain unchanged at the data input. FIGURE 4. Data Setup and Hold Time Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 100350 D Device Type (Basic) C QB Special Variation QB e Military grade device with environmental processing shipped in tubes Package Code D e Ceramic DIP F e Flatpak P e Plastic DIP Q e Plastic Leaded Chip Carrier (PCC) Temperature Range C e Commercial (0 C to a 85 C) M e Military (b55 C to a 125 C) 8 9 Physical Dimensions inches (millimeters) 24-Lead Ceramic Dual-In-Line Package (0.400x Wide) (D) NS Package Number J24E 24-Lead Plastic Dual-In-Line Package (P) NS Package Number N24E 10 Physical Dimensions inches (millimeters) (Continued) 28-Lead Plastic Chip Carrier (Q) NS Package Number V28A 11 100350 Low Power Hex D-Latch Physical Dimensions inches (millimeters) (Continued) Lit. Y 103902 24-Lead Quad Cerpak (F) NS Package Number W24B LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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