June 2003 1
© 2003 Actel Corporation
v3.1
54SX Family FPGAs
Leading Edge Performance
• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Set-Up
• 0.25 ns Clock Skew
Specifications
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1080 Flip-Flops
• 0.35µ CMOS
Features
• 66 MHz PCI
• CPLD and FPGA Integration
• Single Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3V Operation with 5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug capability with
Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
SX Product Profile
A54SX08 A54SX16 A54SX16P A54SX32
Capacity
Typical Gates
System Gates 8,000
12,000 16,000
24,000 16,000
24,000 32,000
48,000
Logic Modules
Combinatorial Cells 768
512 1,452
924 1,452
924 2,880
1800
Register Cells (Dedicated Flip-Flops) 256 528 528 1,080
Maximum User I/Os 130 175 175 249
Clocks 3333
JTAG YesYesYesYes
PCI ——Yes—
Clock-to-Out 3.7 ns 3.9 ns 4.4 ns 4.6 ns
Input Set-Up (External) 0.8 ns 0.5 ns 0.5 ns 0.1 ns
Speed Grades Std, –1, –2, –3 Std, –1, –2, –3 Std, –1, –2, –3 Std, –1, –2, –3
Temperature Grades C, I, M C, I, M C, I, M C, I, M
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
84
208
100
144, 176
—
144
—
208
100
176
—
—
—
208
100
144, 176
—
—
—
208
—
144, 176
313, 329
—
54SX Family FPGAs
2 v3.1
General Description
Actel’s SX family of FPGAs features a sea-of-modules
architecture that delivers device performance and
integration levels not currently achieved by any other FPGA
architecture. SX devices greatly simplify design time, enable
dramatic reductions in design costs and power
consumption, and further decrease time to market for
performance-intensive applications.
Actel’s SX architecture features two types of logic modules,
the combinatorial cell (C-cell) and the register cell (R-cell),
each optimized for fast and efficient mapping of synthesized
logic functions. The routing and interconnect resources are
in the metal layers above the logic modules, providing
optimal use of silicon. This enables the entire floor of the
device to be spanned with an uninterrupted grid of
fine-grained, synthesis-friendly logic modules (or
“sea-of-modules”), which reduces the distance signals have
to travel between logic modules. To minimize signal
propagation delay, SX devices employ both local and ge neral
routing resources. The high-speed local routing resources
(DirectConnect and FastConnect) enable very fast local
signal propagation that is optimal for fast counters, state
machines, and datapath logic. The general system of
segmented routing tracks allows any logic module in the
array to be connected to any other logic or I/O module.
Within this system, propagation delay is minimized by
limiting the number of antifuse interconnect elements to
five (90 percent of connections typically use only three
antifuses). The unique local and general routing structure
featured in SX devices gives fast and predictable
performance, allows 100percent pin-locking with full logic
utilization, enables concurrent PCB development, reduces
design time, and allows designers to achieve performance
goals with minimum effort.
Further complementing SX’s flexible routing structure is a
hard-wired, constantly loaded clock network that has been
tuned to provide fast clock propagation with minimal clock
skew. Additionally, the high performance of the internal
logic has eliminated the need to embed latches or flip-flops
in the I/O cells to achieve fast clock-to-out or fast input
set-up times. SX devices have easy-to-use I/O cells that do
not require HDL i nsta ntiation, facilitating design re-use and
reducing design and verification time.
Ordering Information
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
PP = Pre-production
Package Type
BG = Ball Grid Array
PL = Plastic Lead ed Chip Carrier
PQ =Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Qu ad Flat Pack
FG = Fine Pitch Ball Grid Array (1.0 mm)
Speed Grade
Blank = Standard Speed
–1 =Approximately 15% Faster than Standard
–2 =Approximately 25% Faster than Standard
–3 = App roximately 35% Faster than Standard
Part Number
A54SX08 = 12,000 System Gates
A54SX16 = 24,000 System Gates
A54SX16P = 24,000 System Gates
A54SX32 = 48,000 System Gates
Package Lead Count
A54SX16 – PQ 208
2
Blank = Not PCI Compliant
P =PCI Compliant
P
v3.1 3
54SX Family FPGAs
Product Plan
Speed Grade* Application
Std–1–2–3 C I
†M•
A54SX08 Device
84-Pin Plastic Leaded Chip Carrier (PLCC) ✔✔✔✔ ✔✔—
100-Pin Very Thin Plastic Quad Flat Pack (VQFP) ✔✔✔✔ ✔✔—
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔—
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔ ✔✔—
176-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔—
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔ ✔✔—
A54SX16 Device
100-Pin Very Thin Plastic Quad Flat Pack (VQFP) ✔✔✔✔ ✔✔P
176-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔P
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔ ✔✔P
A54SX16P Device
100-Pin Very Thin Plastic Quad Flat Pack (VQFP) ✔✔✔✔ ✔✔—
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔—
176-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔—
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔ ✔✔—
A54SX32 Device
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔P
176-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔P
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔ ✔✔P
313-Pin Plastic Ball Grid Array (PBGA) ✔✔✔✔ ✔✔—
329-Pin Plastic Ball Grid Array (PBGA) ✔✔✔✔ ✔✔—
Contact your Actel sales representat ive for product availabili ty.
Applications:C = CommercialAvailability:✔= Available*Speed Grade:–1 = Approx. 15% faster than Standard
I = Industrial P = Planned –2 = Approx. 25% faster than Standard
M = Military — = Not Planned –3 = Approx. 35% faster than Standard
† Only Std, –1, –2 Speed Grade
• Only Std, –1 Speed Grade
Plastic Device Resources
User I/Os (including clock buffers)
Device PLCC
84-Pin VQFP
100-Pin PQFP
208-Pin TQFP
144-Pin TQFP
176-Pin PBGA
313-Pin PBGA
329-Pin FBGA
144-Pin
A54SX08 69 81 130 113 128 — — 111
A54SX16 — 81 175 — 147 — — —
A54SX16P — 81 175 113 147 — — —
A54SX32 — — 174 113 147 249 249 —
Package Definitions (Consult your local Actel sales representative for product availability.)
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,
PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch (1.0 mm) Ball Grid Array
54SX Family FPGAs
4 v3.1
SX Family Architecture
The SX family architecture was designed to satisfy
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
Programmable Interconnect Element
The SX family provides efficient use of silicon by locating the
routing interconnect resources between the Metal 2 (M2)
and Metal 3 (M3) layers (Figure 1). This completely
eliminates the channels of routing and interconnect
resources be tween lo gic module s (as implemented on SRAM
FPGAs and previous generations of antifuse FPGAs), and
enables the entire floor of the device to be spanned with an
uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
The extremely small size of these interconnect elements
gives t h e SX famil y abundant routing resources and provides
excellent protection against design pirating. Reverse
engineering is virtually impossible because it is extremely
difficult to distinguish between programmed and
unprogrammed antifuses, and there is no configuration
bitstream to intercept.
Additionally, the interconnect (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
Logic Module Design
The SX family architecture is described as a
“sea-of-modules” architecture because the entire floor of
the device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel’s SX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable (using the S0 and S1
lines) control signals (Figure 2 on page 5). The R-cell
registers feature programmable clock polarity selectable on
a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized functions
into the SX FPGA. The clock source for the R-cell can be
chosen from either the hard-wired clock or the routed clock.
Figure 1 • SX Family Interconnect Elements
Silicon Substrate
Tungsten Plug
Contact
Metal 1
Metal 2
Metal 3
Routing Tracks
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
v3.1 5
54SX Family FPGAs
The C-cell implements a range of combinatorial functions
up to 5-inputs (Figure 3). Inclusion of the DB input and its
associated inverter function dramatically increases the
number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to integrate
a 3-input exclusive-OR function into a single C-cell. This
facilitates construction of 9-bit parity-tree functions with 2
ns propagation delays. At the same time, the C-cell
structure is extremely synthesis friendly, simplifying the
overall design and reducing synthesis time.
Chip Architecture
The SX family’s chip architecture provides a unique
approach to module organization and chip routing that
delivers the best register/logic mix for a wide variety of new
and emerging applications.
Module Organization
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into
SuperClusters
(Figure4 on page 6). SuperCluster 1 is a two-wide grouping
of Type 1 clusters. SuperCluster 2 is a two-wide group
containing one Type 1 cluster and one Type 2 cluster. SX
devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
significantly more combinatorial logic than flip-flops.
Figure 2 • R-Cell
Figure 3 • C-Cell
Direct
Connect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS CKP
CLRB
PSETB
YDQ
Routed
Data Input
S0 S1
D0
D1
D2
D3
DB
A0 B0 A1 B1
Sa Sb
Y
54SX Family FPGAs
6 v3.1
Routing Resources
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 5 and Figure 6 on
page 7). This routing ar chitecture also dram aticall y reduces
the number of antifuses required to complete a circuit,
ensuring the highest possible performance.
DirectConnect is a horizon tal routing res ourc e that provide s
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.4 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100 percent
automatic place and route software to minimize signal
propagation delays.
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hard wired from
the HCLK buffer to the clock select MUX in each R-cell. This
provides a fast propagation path for the clock signal,
enabling the 3.7 ns clock-to-out (pin-to-pin) performance of
the SX devices. The hard-wired clock is tuned to provide
clock skew as low as 0.25 ns. The remaining two clocks
(CLKA, CLKB) are global clocks that can be sourced from
external pins or from internal logic signals within the SX
device.
Figure 4 • Cluster Organization
Type 1 SuperCluster Type 2 SuperCluster
Cluster 1 Cluster 2 Cluster 2 Cluster 1
R-Cell C-Cell
D0
D1
D2
D3
DB
A0 B0 A1 B1
Sa Sb
Y
Direct
Connect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS CKP
CLRB
PSETB
YDQ
Routed
Data Input
S0 S1
v3.1 7
54SX Family FPGAs
Other Architectural Features
Technology
Actel’s SX family is implem ented on a high-voltage twin-well
CMOS process using 0.35µ design rules. The metal-to-metal
antifuse is made up of a combination of amorphous silicon
and dielectric material with barrier metals and has a
programmed (“on” state) resistance of 25Ω with
capacitance of 1.0 fF for low signal impedance.
Figure 5 • DirectConnect and FastConnect for Type 1 SuperClusters
Figure 6 • DirectConnect and FastConnect for Type 2 SuperClusters
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Fast Connect
• One antifuse
• 0.4 ns routing delay
Direct Connect
• No antifuses
• 0.1 ns routing delay
Type 2 SuperClusters
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Fast Connect
• One antifuse
• 0.4 ns routing delay
Direct Connect
• No antifuses
• 0.1 ns routing delay
54SX Family FPGAs
8 v3.1
Performance
The combination of architectural features described above
enables SX devices to operate with internal clock
frequencies exceeding 300 MHz, enabling very fast
execution of even complex logic functions. Thus, the SX
family is an optimal platform upon which to integrate the
functionality previously contained in multiple CPLDs. In
addition, designs that previously would have required a gate
array to meet performance goals can now be integrated into
an SX device with dramatic improvements in cost and time
to market. Using timing-driven place and route tools,
designers can achieve highly deterministic device
performance. With SX devices, designers do not need to use
complicated performance-enhancing design techniques
such as the use of redundant logic to reduce fanout on
critical nets or the instantiation of macros in HDL code to
achieve high performance.
I/O Modules
Each I/O on an SX device can be configured as an input, an
output, a tristate output, or a bidirectional pin. Even wi thout
the inclusion of dedicated I/O registers, these I/Os, in
combination with array registers, can achieve clock-to-out
(pad-to-pad) timing as fast as 3.7 ns. I/O cells that have
embedded latches and flip-flops require instantiation in
HDL code; this is a design complication not encountered in
SX FPGAs. Fast pin-to-pin timing ensures that the device
will have little trouble interfacing with any other device in
the system, which in turn enables parallel design of system
components and reduces overall design time.
Power Requirements
The SX family supports 3.3V operation and is designed to
tolerate 5.0V inputs. (Table 1). Power consumption is
extremely low due to the very short distances signals are
required to travel to complete a circuit. Power requirements
are further reduced because of the small number of
low-resistance antifuses in the path. The antifuse
architecture does not require active circuitry to hold a
charge (as do SRAM or EPROM), making it the lowest-power
architectur e on the market.
Boundary Scan Testing (BST)
All SX devices are IEEE 1149.1 compliant. SX devices offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
These functions are controlled through the special test pins
in conjunction with the program fuse. The functionality of
each pin is described in Table 2.In the dedicated test mode,
TCK, TDI and TDO are dedicated pins and cannot be used as
regular I/Os. In flexible mode, TMS should be set HIGH
through a pull-up resistor of 10kΩ. TMS can be pulled LOW
to initiate the test sequence.
The program fuse determines whether the device is in
dedicated or flexible mode. The default (fuse not blown) is
flexible mode. .
Development Tool Support
The SX devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Advantage tools. The Actel DeskTOP series is an
integrated de sign environment for PCs that includes design
entry, simulation, synthesis, and place and route tools.
Designer Advantage, Actel’s suite of FPGA development
point tools for PCs and Workstations, includes the ACTgen
Macro Builder, Designer with DirectTime timing driven
place and route and analysis tools, and device programming
software.
In addition, the SX devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
enabling 100-percent real-time observation and analysis of a
device's internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer II, an
easy-to-use integrated verification and logic analysis tool
that can sample da ta at 100 MHz (asynchron ous) or 66 MHz
(synchronous). Silicon Explorer II attaches to a PC’s
standard COM port, turning the PC into a fully functional
18-channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at
their desks and reduces verification time from several hours
per cycle to only a few seconds.
Table 1 • Supply Voltag es
VCCA VCCI VCCR
Maximum
Input
Tolerance
Maximum
Output
Drive
A54SX08
A54SX16
A54SX32 3.3V 3.3V 5.0V 5.0V 3.3V
A54SX16-P 3.3V
3.3V
3.3V
3.3V
3.3V
5.0V
3.3V
5.0V
5.0V
3.3V
5.0V
5.0V
3.3V
3.3V
5.0V
Note: A54SX16-P has three different entries because it is capable of
both a 3.3V and a 5V drive.
Table 2 • Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode) Program Fuse Not Blown
(Flexible Mod e)
TCK, TDI, TDO are
dedicated BST pins TCK, TDI, TDO are flexible
and may be used as I/Os
No need for pull-up resistor
for TMS Use a pull-up resistor of 10k
Ω on TMS
v3.1 9
54SX Family FPGAs
SX Probe Circuit Control Pins
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 7 illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification. The TR ST pin is equipped
with a pull-up resistor. To remove the boundary scan state
machine from the reset state during probing, it is
recommended that the TRST pin be left floating.
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Because these pins are
active during probing, critical signals input through these
pins are not available while probing. In addition, the
Security Fuse should not be programmed because doing so
disables the Probe Circuitry.
Figure 7 • Probe Setup
SX FPGA
TDI
TCK
TDO
TMS
PRA
PRB
Serial Conne ction
16
Channel
Silicon Explorer II
54SX Family FPGAs
10 v3.1
3.3V/5V Operating Conditions
Absolute Maximum Ratings1
Symbol Parameter Limits Units
VCCR2DC Supply Vol tage3–0.3 to +6.0 V
VCCA2DC Supply Voltage –0.3 to +4.0 V
VCCI2DC Supply Voltage
(A54SX08, A54SX16,
A54SX32) –0.3 to +4.0 V
VCCI2DC Supply Voltage
(A54SX16P) –0.3 to +6.0 V
VIInput Voltage –0.5 to +5.5 V
VOOutput Voltage –0.5 to +3.6 V
IIO I/O Source Sink
Current3–30 to +5.0 mA
TSTG Storage Temperature –65 to +150 °C
Notes:
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be
operated outside the Recommended Operating Conditions.
2. VCCR in the A54SX16P must be greater than or equal to VCCI
during power-up and power-down sequences and during
normal operation.
3. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than VCC + 0.5V or less than GND – 0.5V, the internal protection
diodes will forward-bias and can draw excessive current.
Recommended Operating Conditions
Parameter Commer
cial Industrial Military Units
Temperature
Range10 to+70 –40 to +85 –55 to +125 °C
3.3V Power
Supply
Tolerance ±10 ±10 ±10 %VC
C
5.0V Power
Supply
Tolerance ±5±10 ±10 %VC
C
Note:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
Electrical Specifications
Commercial Industrial
Symbol Parameter Min. Max. Min. Max. Units
VOH
(IOH = -20uA) (CMOS)
(IOH = -8mA ) (TTL)
(IOH = -6mA ) (TTL)
(VCCI – 0.1)
2.4 VCCI
VCCI
(VCCI – 0.1)
2.4
VCCI
VCCI
V
VOL
(IOL= 20uA) (CMOS)
(IOL = 12mA) (TTL)
(IOL = 8mA) (TTL)
0.10
0.50 0.50 V
VIL 0.8 0.8 V
VIH 2.0 2.0 V
tR, tFInput Transition Time tR, tF50 50 ns
CIO CIO I/O Capacitance 10 10 pF
ICC Standby Current, ICC 4.0 4.0 mA
ICC(D) ICC(D) IDynamic VCC Supply Current See “Evaluating Power in 54SX Devices” on page 18
v3.1 11
54SX Family FPGAs
PCI Compliance for the 54SX Family
The 54SX family supports 3.3V and 5V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
A54SX16P DC Specifications (5.0V PCI Operation)
Symbol Parameter Condition Min. Max. Units
VCCA Supply Voltage for Array 3.0 3.6 V
VCCR Supply Voltage required for Internal Biasing 4.75 5.25 V
VCCI Supply Voltage for IOs 4.75 5.25 V
VIH Input High Voltage12.0 VCC + 0.5 V
VIL Input Low Voltage1–0.5 0.8 V
IIH Input High Leakage Current VIN = 2.7 70 µA
IIL Input Low Leakage Current VIN = 0.5 –70 µA
VOH Output High V oltage IOUT = –2 mA 2.4 V
VOL Output Low Voltage2IOUT = 3 mA, 6 mA 0.55 V
CIN Input Pin Capacitance310 pF
CCLK CLK Pin Capacitance 5 12 pF
CIDSEL IDSEL Pin Capa citance48pF
Notes:
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-st ate outputs.
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter include,
FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
54SX Family FPGAs
12 v3.1
A54SX16P AC Specifications for (PCI Operation)
Symbol Parameter Condition Min. Max. Units
IOH(AC) Switching Current High
0 < VOUT ≤ 1.41–44 mA
1.4 ≤ VOUT < 2.41, 2 –44 + (VOUT – 1.4)/0.0 24 mA
3.1 < VOUT < VCC1, 3 Equation A: on
page 13
(Test Point) VOUT = 3.13–142 mA
IOL(AC) Switching Current High
VOUT ≥ 2.2195 mA
2.2 > VOUT > 0.551VOUT/0.023
0.71 > VOUT > 01, 3 Equation B: on
page 13 mA
(Test Point) VOUT = 0.713206 mA
ICL Low Clamp Current –5 < VIN ≤ –1 –25 + (VIN + 1)/0.015 mA
slewROutput Rise Slew Rate 0.4V to 2.4V load415V/ns
slewFOutput Fall Slew Rate 2.4V to 0.4V load415V/ns
Notes:
1. Refer to the V/I curves in Figure 8. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here;
i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# wh ich are system outputs.
“Switching Current High” s pecification ar e not relevant t o SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward
the voltage rail (as is done in the pull-down c urve). Thi s differenc e is intend ed to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B)
are provided with the respective diagrams in Figure 8. The equation defined maxima should be met by design. In order to facilitate
component testing, a maximum current test point is defined for each side of t he output driver.
4. This parameter i s to be int erp reted as the c umulati ve edge rate across the spe cified range, rather t han the instantaneous rate at any poin t
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is
now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to
revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard
designers must bear in mind that rise and fall times faster than this specification could occur, and should ensure that signal integrity
modeling accounts for this. Rise slew rate does not apply to open drain outputs.
output
buffer
1/2 in. max.
VCC
1kΩ
10 pF
1kΩ
pin
v3.1 13
54SX Family FPGAs
Figure 8 shows the 5.0V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P family.
Equation A:
IOH = 11.9 * (VOUT – 5.25) * (VOUT + 2.45)
for VCC > VOUT > 3.1V
Equation B: IOL = 78.5 * VOUT * (4.4 – VOUT)
for 0V < VOUT < 0.71V
Figure 8 • 5.0V PCI Curve for A54SX16P Family
123456
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Voltage Out
Current (A)
SX PCI IOL
SX PCI IOH
PCI IOL Maximum
PCI IOH Maximum
PCI IOH Mininum
PCI IOL Mininum
54SX Family FPGAs
14 v3.1
A54SX16P DC Specifications (3.3V PCI Operation)
Symbol Parameter Condition Min. Max. Units
VCCA Supply Voltage for Array 3.0 3.6 V
VCCR Supply Voltage required for Internal Biasing 3.0 3.6 V
VCCI Supply Vol tage for IOs 3.0 3.6 V
VIH Input High Voltage 0.5V CC VCC + 0.5 V
VIL Input Low Voltage –0.5 0.3VCC V
IIPU Input Pull-up Voltage10.7VCC V
IIL Input Leakage Current20 < VIN < VCC ±10 µA
VOH Output High V oltage IOUT = –500 µA 0.9VCC V
VOL Output Low Voltage IOUT = 1500 µA 0.1VCC V
CIN Input Pin Capacitance310 pF
CCLK CLK Pin Capacitance 5 12 pF
CIDSEL IDSEL Pin Capa citance48pF
Notes:
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated
network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this
input voltage.
2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-st ate outputs.
3. Absolute maximum pi n ca pacit anc e for a PCI i nput is 10pF ( excep t fo r CLK ).
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
v3.1 15
54SX Family FPGAs
A 54SX16P AC Specifications (3.3V PCI Operation)
Symbol Parameter Condition Min. Max. Units
Switching Current High
0 < VOUT ≤ 0.3VCC1 mA
0.3VCC ≤ VOUT < 0.9VCC1–12VCC mA
IOH(AC) 0.7VCC < VOUT < VCC1, 2 –17.1 + (VCC – VOUT)Equation C: on
page 16
(Test Point) VOUT = 0.7VCC2–32VCC mA
Switching Current High VCC > VOUT ≥ 0.6VCC1mA
0.6VCC > VOUT > 0.1VCC116VCC mA
IOL(AC) 0.18VCC > VOUT > 01, 2 26.7VOUT on page 16 mA
(Test Point) VOUT = 0.18VCC238VCC
ICL Low Clamp Current –3 < VIN ≤ –1 –25 + (VIN + 1)/0.015 mA
ICH High Clamp Current –3 < VIN ≤ –1 25 + (VIN – VOUT – 1)/0.015 mA
slewROutput Rise Slew Rate30.2VCC to 0.6VCC load 1 4 V/ns
slewFOutput Fall Slew Rate30.6VCC to 0.2VCC load 1 4 V/ns
Notes:
1. Refer to the V/I curves in Figure9. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here;
i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs.
“Switching Current High” spec ification are not relevant t o SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D)
are provided with the respective diagrams in Figure9. The equation defined maxima should be met by design. In order to facilitate
component testing, a maximum current test poin t is defined for each side of t he output drive r.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.
output
buffer
1/2 in. max.
VCC
1kΩ
10 pF
1kΩ
pin
54SX Family FPGAs
16 v3.1
Figure 9 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P family.
Equation C:
IOH = (98.0/VCC) * (VOUT – VCC) * (VOUT + 0.4VCC)
for VCC > VOUT > 0.7 VCC
Equation D:
IOL = (256/VCC) * VOUT * (VCC – VOUT)
for 0V < VOUT < 0.18 VCC
Figure 9 • 3.3V PCI Curve for A54SX16P Family
123456
Voltage Out
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Current (A)
SX PCI IOL
SX PCI IOH
PCI IOL Maximum
PCI IOH Maximum
PCI IOH Minimum
PCI IOL Minimum
v3.1 17
54SX Family FPGAs
Power-Up Sequencing
Power-Down Sequencing
VCCA VCCR VCCI Power-Up Sequence Comments
A54SX08, A54SX16, A54SX32
3.3V 5.0V 3.3V
5.0V First
3.3V Second No possible damage to device.
3.3V First
5.0V Second Possible damage to device.
A54SX16P
3.3V 3.3V 3.3V 3.3V Only No possible damage to device.
3.3V 5.0V 3.3V
5.0V First
3.3V Second No possible damage to device.
3.3V First
5.0V Second Possible damage to device.
3.3V 5.0V 5.0V
5.0V First
3.3V Second No possible damage to device.
3.3V First
5.0V Second No possible damage to device.
VCCA VCCR VCCI Power-Down Sequence Comments
A54SX08, A54SX16, A54SX32
3.3V 5.0V 3.3V
5.0V First
3.3V Second No possible damage to device.
3.3V First
5.0V Second Possible damage to device.
A54SX16P
3.3V 3.3V 3.3V 3.3V Only No possible damage to device.
3.3V 5.0V 3.3V
5.0V First
3.3V Second Possible damage to device.
3.3V First
5.0V Second No possible damage to device.
3.3V 5.0V 5.0V
5.0V First
3.3V Second No possible damage to device.
3.3V First
5.0V Second No possible damage to device.
54SX Family FPGAs
18 v3.1
Evaluating Power in 54SX Devices
A critical element of system reliability is the ability of
electronic devices to safely dissipate the heat generated
during operation. The thermal characteristics of a circuit
depend on the device and package used, the operating
temperature, the operating current, and the system's ability
to dissipate heat.
You should complete a power evaluation early in the design
process to help identify potential heat-related problems in
the system and to prevent the system from exceeding the
device’s maximum allowed junction temperature.
The actual power dissipated by most applications is
significantly lower than the power the package can
dissipate. However, a thermal analysis should be performed
for all projects. To perform a power evaluation, follow these
steps:
• Estimate the power consumption of the application.
• Calculate the maximum power allowed for the device and
package.
• Compare the estimated power and maximum power
values.
Estimating Power Consumption
The total power dissipation for the 54SX family is the sum of
the DC power dissipation and the AC powe r dissi patio n. Use
Equation 1 to calculate the estimated power consumption of
your application.
PTotal = PDC + PAC (1)
DC Power Dissipation
The power due to standby current is typically a small
component of the overall power. The Standby power is
shown below for commercial, worst case conditions (70°C).
The DC power dissipation is defined in Equation 2 as
follows:
PDC = (Istandby)*VCCA + (Istandby)*VCCR +
(Istandby)*VCCI + x*VOL*IOL + y*(VCCI – VOH)*VOH (2)
AC Power Dissipation
The power dissipation of the 54SX Family is usually
dominated by the dynamic power dissipation. Dynamic
power dissipation is a function of frequency, equivalent
capacitance and power supply voltage. The AC power
dissipation is defined as follows:
PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net +
POutput Buffer + PInput Buffer (3)
PAC = VCCA2 * [(m * CEQM * fm)Module +
(n * CEQI * fn)Input Buffer+ (p * (CEQO + CL) * fp)Output Buffer+
(0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))RCLKA +
(0.5 * (q2 * CEQCR * fq2)+ (r2 * fq2))RCLKB +
(0.5 * (s1 * CEQHV * fs1) + (CEQHF * fs1))HCLK](4)
Definition of Terms Used in Formula
Table 3 •
ICC VCC Power
4mA 3.6V 14.4mW
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
p = Number of ou tput buffers switching at fp
q1= Number of clock loads on the first routed array
clock
q2= Number of clock loads on the second routed
array clock
x = Number of I/Os at logic low
y = Number of I/Os at logic high
r1= Fixed capacitance due to first routed array
clock
r2= Fixed capacitance due to second routed array
clock
s1= Number of clock loads on the dedicated array
clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in
pF
CEQHV = Variable capacitance of dedicated array clock
CEQHF = Fixed capacitance of dedicated array clock
CL= Output lead capacitance in pF
fm= Average logic module switching rate in MHz
fn= Average input buffer switching rate in MHz
fp= Average output buffer switching rate in MHz
fq1 = Average first routed array clock rate in MHz
fq2 = Average second routed array clock rate in MHz
fs1 = Average dedicated array clock rate in MHz
A54SX08 A54SX16 A54SX16P A54SX32
CEQM (pF) 4.0 4.0 4.0 4.0
CEQI (pF) 3.4 3.4 3.4 3.4
CEQO (pF) 4.7 4.7 4.7 4.7
CEQCR (pF)1.6 1.6 1.6 1.6
CEQHV 0.615 0.615 0.615 0.615
CEQHF 60 96 96 140
r1 (pF) 87 138 138 17 1
r2 (pF) 87 138 138 17 1
v3.1 19
54SX Family FPGAs
Guidelines for Calculating Power
Consumption
The following guidelines are meant to represent worst-case
scenarios so that they can be generally used to predict the
upper limits of power dissipation. These guidelines are as
follow:
Sample Power Calculation
One of the designs used to characterize the A54SX family
was a 528 bit serial in serial out shift register. The design
utilized 100% of the dedicated flip-flops of an A54SX16P
device. A pattern of 0101… was clocked into the device at
frequencies ranging from 1 MHz to 200 MHz. Shifting in a
series of 0101… caused 50% of the flip-flops to toggle from
low to high at every clock cycle.
Follow the steps below to estimate power consumption. The
values provided for the sample calculation below are for the
shift register design above. This method for estimating
power consumption is conservative and the actual power
consumption of your design may be less than the estimated
power consumption.
The total power dissipation for the 54SX family is the sum of
the AC power dissipation and the DC power dissipation.
PTotal = PAC (dynamic power) + PDC (static power) (5)
AC Power Dissipation
PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net +
POutput Buffer + PInput Buffer (6)
PAC = VCCA2 * [(m * CEQM * fm)Module +
(n * CEQI * fn)Input Buffer+ (p * (CEQO + CL) * fp)Output
Buffer+
(0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))RCLKA +
(0.5 * (q2 * CEQCR * fq2)+ (r2 * fq2))RCLKB +
(0.5 * (s1 * CEQHV * fs1) + (CEQHF * fs1))HCLK](7)
Step #1: Define Terms Used in Formula
Logic Modules (m) = 20% of modules
Inputs Switching (n) = # inputs/4
Outputs Switching (p) = # output/4
First Routed Array Clock Loads (q1) = 20% of register
cells
Second Routed Array Clock Loads (q2) = 20% of register
cells
Load Capacitance (CL)=35 pF
Average Logic Module Switching Rate
(fm)=f/10
Average Input Switching Rate (fn)=f/5
Average Output Switching Rate (fp)=f/10
Average First Routed Array Clock Rate
(fq1)=f/2
Average Second Routed Array Clock
Rate (fq2)=f/2
Average Dedicated Array Clock Rate
(fs1) =f
Dedicated Clock Array clock loads (s1)=20% of regular
modules
VCCA 3.3
Module
Number of logic modules switching at fm
(Used 50%) m264
Average logic modules switching rate
fm (MHz) (Guidelines: f/10) fm20
Module capacitance CEQM (pF) CEQM 4.0
Input Buffer
Number of input buffers switching at fnn1
Average input switching rate fn (MHz)
(Guidelines: f/5) fn40
Input buffer capacitance CEQI (pF) CEQI 3.4
Output Buffer
Number of ou tput buffers switching at fpp1
Average output buffers switching rate
fp(MHz) (Guidelines: f/10) fp20
Output buffers buffer Capacitance CEQO (pF)CEQO 4.7
Output Load capacitance CL (pF) CL35
RCLKA
Number of Clock loads q1q1528
Capacitance of routed array clock (pF) CEQCR 1.6
Average clock rate (MHz) fq1 200
Fixed capacitance (pF) r1138
RCLKB
Number of Clock loads q2q20
Capacitance of routed array clock (pF) CEQCR 1.6
Average clock rate (MHz) fq2 0
Fixed capacitance (pF) r2138
HCLK
Number of Clock loads s10
Variable capacitance of dedicated
array clock (pF) CEQHV 0.615
Fixed capacitance of dedicated
array clock (pF) CEQHF 96
Average clock rate (MHz) fs1 0
54SX Family FPGAs
20 v3.1
Step #2: Calculate Dynamic Power Consum ption
Step #3: Calculate DC Power Dissipation
DC Power Dissipation
PDC = (Istandby)*VCCA + (Istandby)*VCCR + (Istandby)*VCCI +
X*VOL*IOL + Y*(VCCI – VOH)*VOH (8)
For a rough estimate of DC Power Dissipation, only use
PDC =(I
standby)*VCCA. The rest of the formula provides a
very small number that can be considered negligible.
PDC = (Istandby)*VCCA
PDC = .55mA*3.3V
PDC = 0.001815W
Step #4: Calculate Total Power Consump tion
PTotal = PAC + PDC
PTotal = 1.461 + 0.001815
PTotal = 1.4628W
Step #5: Compare Estimated Power Consumption agai nst
Characterized Power Consumption
The estimated total power consumption for this design is
1.46W. The characterized power consumption for this design
at 200 MHz is 1.0164W. Figure 10 shows the characterized
power dissipation numbers for the shift register design
using frequencies ranging from 1 MHz to 200 MHz.
VCCA*VCCA 10.89
m*fm*CEQM 0.02112
n*fn*CEQI 0.000136
p*fp*(CEQO+CL) 0.000794
0.5*(q1*CEQCR*fq1)+(r1*fq1) 0.11208
0.5*(q2*CEQCR*fq2)+(r2*fq2)0
0.5 *(s1 * CEQHV * fs1)+(CEQHF*fs1)0
PAC = 1.461W
Figure 10 • Power Dissipation
0
200
400
600
800
1000
1200
Frequency MHz
Power Dissipation mW
200 40 60 80 100 120 140 160 180 200
v3.1 21
54SX Family FPGAs
Junction Temperature (TJ)
The temperature that you select in Designer Series software
is the junction temperature, not ambient temperature. This
is an important distinction be cause the heat generated f rom
dynamic power consumption is usually hotter than the
ambient temperature. Use the equation below to calculate
junction temperature.
Junction Temperature = ∆T + Ta
Where:
Ta = Ambient Temperature
∆T = Temperature gradient between junction (silicon) and
ambient
∆T = θja * P
P = Power calculated from Estimating Power Consumption
section
θja = Junction to ambient of package. θja numbers are
located in Package Thermal Characteristics section.
Package Thermal Characteristics
The device junction to case thermal characteristic is θjc,
and the junction to ambient air characteristic is θja. The
thermal characteristics for θja are shown with two different
air flow rates.
The maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a TQFP 176-pin package at
commercial temperature and still air is as follows:
Package Type Pin Count θjc
θja
Still Air θja
300 ft/min Units
Plastic Leaded Chip Carrier (PLCC) 84 12 32 22 °C/W
Thin Quad Flat Pack (TQFP) 144 11 32 24 °C/W
Thin Quad Flat Pack (TQFP) 176 11 28 21 °C/W
Very Thin Quad Flatpack (VQFP) 100 10 38 32 °C/W
Plastic Quad Flat Pack (PQFP) without Heat Spreader 208 8 30 23 °C/W
Plastic Quad Flat Pack (PQFP) with Heat Spreader 208 3.8 20 17 °C/W
Plastic Ball Grid Array (PBGA) 272 3 20 14.5 °C/W
Plastic Ball Grid Array (PBGA) 313 3 23 17 °C/W
Plastic Ball Grid Array (PBGA) 329 3 18 13.5 °C/W
Fine Pitch Ball Grid Array (FBGA) 144 3.8 38.8 26.7 °C/W
Note: SX08 does not have a heat spreader.
Maximum Power Allowed Max. junction temp. (°C) – Max. ambient temp. (°C)
θja (°C/W)
------------------------------------------------------------------------------------------------------------------------------ 150°C – 70°C
28°C/W
--------------------------------- 2.86W===
54SX Family FPGAs
22 v3.1
54SX Timing Model*
Hard-Wired Clock
External Set-Up = tINY + tIRD1 + tSUD – tHCKH
= 1 .5 + 0.3 + 0.5 – 1.0 = 1.3 ns
Clock-to-Out (Pin-to-Pin)
=t
HCKH + tRCO + tRD1 + tDHL
= 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns
Routed Clock
External Set-Up = tINY + tIRD1 + tSUD – tRCKH
= 1.5 + 0.3 + 0.5 – 1.5 = 0.8 ns
Clock-to-Out (Pin-to-Pin)
=t
RCKH + tRCO + tRD1 + tDHL
= 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns
*Values shown for A54SX08-3, worst-case commercial conditions.
Output DelaysInternal DelaysInput Delays
Hard-Wired
I/O Module
FHMAX = 320 MHz
tINY = 1.5 ns tIRD2 = 0.6 ns
Combinatorial
Cell
tPD =0.6 ns
Register
Cell
I/O Module
tRD1 = 0.3 ns tDHL = 1.6 ns
I/O Module
Routed
Clock
FMAX = 250 MHz
DQDQ
tDHL = 1.6 ns
tENZH = 2.3 ns
tRD1 = 0.3 ns
tRCO = 0.8 ns
tSUD = 0.5 ns
tHD = 0.0 ns
tRD4 = 1.0 ns
tRD8 = 1.9 ns
Predicted
Routing
Delays
tRCKH = 1.5 ns (100% Load)
tRD1 = 0.3 ns
Register
Cell
tRCO = 0.8 ns
Clock tHCKH = 1.0 ns
v3.1 23
54SX Family FPGAs
Output Buffer Delays
AC Test Loads
Input Buffer Delays C-Cell Delays
To AC test loads (shown below)
PAD
D
E
TRIBUFF
In VCC GND
50%
Out
VOL
VOH
1.5V
tDLH
50%
1.5V
tDHL
En VCC GND
50%
Out VOL
1.5V
tENZL
50%
10%
tENLZ
En VCC GND
50%
Out
GND
VOH
1.5V
tENZH
50%
90%
tENHZ
VCC
Load 1
(Used to measure Load 2
(Used to measure enable de lays)
35 pF
To the output VCC GND
35 pF
To the output R to VCC for tPZL
R to GND for tPZH
R = 1 kΩ
propagation delay)
under test
under test
Load 3
(Used to measure disable delays)
VCC GND
5 pF
To the outpu t R to VCC for tPLZ
R to GND for tPHZ
R = 1 kΩ
under test
PAD Y
INBUF
In 3V 0V
1.5V
Out
GND
VCC
50%
tINY
1.5V
50%
tINY
S
A
BY
S, A or B
Out
GND
VCC
50%
tPD
Out
GND
GND
VCC
50%
50% 50%
VCC
50% 50%
tPD
tPD
tPD
54SX Family FPGAs
24 v3.1
Timing Characteristics
Timing characteristics for 54SX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all 54SX family members.
Internal routing delays are device dependent. Design
dependency means actual delays are not determined until
after placement and routing of the use r’s design is complete.
Delay values may then be determined by using the
DirectTime Analyzer utility or performing simulation with
post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
time-critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up to
6% of the nets in a design may be designated as critical,
while 90% of the nets in a design are typical.
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three and sometimes five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout (FO=24) routing
delays in the data sheet specifications section.
Timing Derating
54SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 3.0V)
Register Cell Timing Characteristics
Flip-Flops
(Positi v e edge trigger e d)
D
CLK CLR
Q
D
CLK
Q
CLR
t
HPWH
,
t
WASYN
t
HD
t
SUD
t
HP
t
HPWL
,
t
RCO
t
CLR
t
RPWL
t
RPWH
PRESET
t
PRESET
PRESET
VCCA
Junction Temperature (TJ)
–55 –40 0 25 70 85 125
3.0 0.75 0.78 0.87 0.89 1.00 1.04 1.16
3.3 0.70 0.73 0.82 0.83 0.93 0.97 1.08
3.6 0.66 0.69 0.77 0.78 0.87 0.92 1.02
v3.1 25
54SX Family FPGAs
A54SX08 Timing Characteristics
(Worst-Case Commercial Conditions, VCCR= 4.75V, VCCA,VCCI = 3.0V, TJ = 70°C)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Units
C-Cell Prop agation Delays1
tPD Internal Array Module 0.6 0.7 0.8 0.9 ns
Predicted Routing Delays2
tDC FO=1 Routing Delay, Direct
Connect 0.1 0.1 0.1 0.1 ns
tFC FO=1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns
tRD1 FO=1 Routing Delay 0.3 0.4 0.4 0.5 ns
tRD2 FO=2 Routing Delay 0.6 0.7 0.8 0.9 ns
tRD3 FO=3 Routing Delay 0.8 0.9 1.0 1.2 ns
tRD4 FO=4 Routing Delay 1.0 1.2 1.4 1.6 ns
tRD8 FO=8 Routing Delay 1.9 2.2 2.5 2.9 ns
tRD12 FO=12 Routing Delay 2.8 3.2 3.7 4.3 ns
R-Cell Timing
tRCO Sequential Clock-to-Q 0.8 1.1 1.2 1.4 ns
tCLR Asynchronous Clear-to-Q 0.5 0.6 0.7 0.8 ns
tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns
tSUD Flip-Flop Data Input Set-Up 0.5 0.5 0.7 0.8 ns
tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns
tWASYN Asynchronous Pulse Width 1.4 1.6 1.8 2.1 ns
Input Module Propagation Delays
tINYH Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns
tINYL Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns
Input Module Predicted Routing Delays2
tIRD1 FO=1 Routing Delay 0.3 0.4 0.4 0.5 ns
tIRD2 FO=2 Routing Delay 0.6 0.7 0.8 0.9 ns
tIRD3 FO=3 Routing Delay 0.8 0.9 1.0 1.2 ns
tIRD4 FO=4 Routing Delay 1.0 1.2 1.4 1.6 ns
tIRD8 FO=8 Routing Delay 1.9 2.2 2.5 2.9 ns
tIRD12 FO=12 Routing Delay 2.8 3.2 3.7 4.3 ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
54SX Family FPGAs
26 v3.1
A54SX08 Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network
tHCKH Input LOW to HIGH
(Pad to R-Cell Input) 1.0 1.1 1.3 1.5 ns
tHCKL Input HIGH to LOW
(Pad to R-Cell Input) 1.0 1.2 1.4 1.6 ns
tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 ns
tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 ns
tHCKSW Maximum Skew 0.1 0.2 0.2 0.2 ns
tHP Minimum Period 2.7 3.1 3.6 4.2 ns
fHMAX Maximum Frequency 350 320 280 240 MHz
Routed Array Clock Networks
tRCKH Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) 1.3 1.5 1.7 2.0 ns
tRCKL Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) 1.4 1.6 1.8 2.1 ns
tRCKH Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) 1.4 1.7 1.9 2.2 ns
tRCKL Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) 1.5 1.7 2.0 2.3 ns
tRCKH Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) 1.5 1.7 1.9 2.2 ns
tRCKL Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) 1.5 1.8 2.0 2.3 ns
tRPWH Min. Pulse Width HIGH 2.1 2.4 2.7 3.2 ns
tRPWL Min. Pulse Width LOW 2.1 2.4 2.7 3.2 ns
tRCKSW Maximum Skew (Light Load) 0.1 0.2 0.2 0.2 ns
tRCKSW Maximum Skew (50% Load) 0.3 0.3 0.4 0.4 ns
tRCKSW Maximum Skew (100% Load) 0.3 0.3 0.4 0.4 ns
TTL Output Mo dule Timing1
tDLH Data-to-Pad LOW to HIGH 1.6 1.9 2.1 2.5 ns
tDHL Data-to-Pad HIGH to LOW 1.6 1.9 2.1 2.5 ns
tENZL Enable-to-Pad, Z to L 2.1 2.4 2.8 3.2 ns
tENZH Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 ns
tENLZ Enable-to-Pad, L to Z 1.4 1.7 1.9 2.2 ns
tENHZ Enable-to-Pad, H to Z 1.3 1.5 1.7 2.0 ns
Note:
1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
v3.1 27
54SX Family FPGAs
A54SX16 Timing Characteristics
(Worst-Case Commercial Conditions, VCCR= 4.75V, VCCA,VCCI = 3.0V, TJ = 70°C)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Units
C-Cell Prop agation Delays1
tPD Internal Array Module 0.6 0.7 0.8 0 .9 ns
Predicted Routing Delays2
tDC FO=1 Routing Delay, Direct
Connect 0.1 0.1 0.1 0.1 ns
tFC FO=1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns
tRD1 FO=1 Routing Delay 0.3 0.4 0.4 0.5 ns
tRD2 FO=2 Routing Delay 0.6 0.7 0.8 0.9 ns
tRD3 FO=3 Routing Delay 0.8 0.9 1.0 1.2 ns
tRD4 FO=4 Routing Delay 1.0 1.2 1.4 1.6 ns
tRD8 FO=8 Routing Delay 1.9 2.2 2.5 2.9 ns
tRD12 FO=12 Routing Delay 2.8 3.2 3.7 4.3 ns
R-Cell Timing
tRCO Sequential Clock-to-Q 0.8 1.1 1.2 1.4 ns
tCLR Asynchronous Clear-to-Q 0 .5 0.6 0.7 0.8 ns
tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns
tSUD Flip-Flop Data Input Set-Up 0.5 0.5 0.7 0.8 ns
tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns
tWASYN Asynchronous Pulse Width 1.4 1.6 1.8 2.1 ns
Input Modul e Pr opagation Del ays
tINYH Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns
tINYL Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns
Predicted Input Routing Delays2
tIRD1 FO=1 Routing Delay 0.3 0.4 0.4 0.5 ns
tIRD2 FO=2 Routing Delay 0.6 0.7 0.8 0.9 ns
tIRD3 FO=3 Routing Delay 0.8 0.9 1.0 1.2 ns
tIRD4 FO=4 Routing Delay 1.0 1.2 1.4 1.6 ns
tIRD8 FO=8 Routing Delay 1.9 2.2 2.5 2.9 ns
tIRD12 FO=12 Routing Delay 2.8 3.2 3.7 4.3 ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
54SX Family FPGAs
28 v3.1
A54SX16 Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network
tHCKH Input LOW to HIGH
(Pad to R-Cell Input) 1.2 1.4 1.5 1.8 ns
tHCKL Input HIGH to LOW
(Pad to R-Cell Input) 1.2 1.4 1.6 1.9 ns
tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 ns
tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 ns
tHCKSW Maximum Skew 0.2 0.2 0.3 0.3 ns
tHP Minimum Period 2.7 3.1 3.6 4.2 ns
fHMAX Maximum Frequency 350 320 280 240 MHz
Routed Array Clock Networks
tRCKH Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) 1.6 1.8 2.1 2.5 ns
tRCKL Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) 1.8 2.0 2.3 2.7 ns
tRCKH Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) 1.8 2.1 2.5 2.8 ns
tRCKL Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) 2.0 2.2 2.5 3.0 ns
tRCKH Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) 1.8 2.1 2.4 2.8 ns
tRCKL Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) 2.0 2.2 2.5 3.0 ns
tRPWH Min. Pulse Width HIGH 2.1 2.4 2.7 3.2 ns
tRPWL Min. Pulse Width LOW 2.1 2.4 2.7 3.2 ns
tRCKSW Maximum Skew (Light Load) 0.5 0.5 0.5 0.7 ns
tRCKSW Maximum Skew (50% Load) 0.5 0.6 0.7 0.8 ns
tRCKSW Maximum Skew (100% Load) 0.5 0.6 0.7 0.8 ns
TTL Output Mo duleTiming1
tDLH Data-to-Pad LOW to HIGH 1.6 1.9 2.1 2.5 ns
tDHL Data-to-Pad HIGH to LOW 1.6 1.9 2.1 2.5 ns
tENZL Enable-to-Pad, Z to L 2.1 2.4 2 .8 3.2 ns
tENZH Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 ns
tENLZ Enable-to-Pad, L to Z 1.4 1.7 1.9 2.2 ns
tENHZ Enable-to-Pad, H to Z 1.3 1.5 1.7 2.0 ns
Note:
1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
v3.1 29
54SX Family FPGAs
A54SX16P Timing Characteristics
(Worst-Case Commercial Conditions, VCCR= 4.75V, VCCA,VCCI = 3.0V, TJ = 70°C)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Units
C-Cell Prop agation Delays1
tPD Internal Array Module 0.6 0.7 0.8 0 .9 ns
Predicted Routing Delays2
tDC FO=1 Routing Delay, Direct
Connect 0.1 0.1 0.1 0.1 ns
tFC FO=1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns
tRD1 FO=1 Routing Delay 0.3 0.4 0.4 0.5 ns
tRD2 FO=2 Routing Delay 0.6 0.7 0.8 0.9 ns
tRD3 FO=3 Routing Delay 0.8 0.9 1.0 1.2 ns
tRD4 FO=4 Routing Delay 1.0 1.2 1.4 1.6 ns
tRD8 FO=8 Routing Delay 1.9 2.2 2.5 2.9 ns
tRD12 FO=12 Routing Delay 2.8 3.2 3.7 4 .3 ns
R-Cell Timing
tRCO Sequential Clock-to-Q 0.9 1.1 1.3 1.4 ns
tCLR Asynchronous Clear-to-Q 0 .5 0.6 0.7 0.8 ns
tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns
tSUD Flip-Flop Data Input Set-Up 0.5 0.5 0.7 0.8 ns
tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns
tWASYN Async hr onous Pulse W id th 1.4 1.6 1.8 2.1 ns
Input Modul e Pr opagation Del ays
tINYH Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns
tINYL Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns
Predicted Input Routing Delays2
tIRD1 FO=1 Routing Delay 0.3 0.4 0.4 0.5 ns
tIRD2 FO=2 Routing Delay 0.6 0.7 0.8 0.9 ns
tIRD3 FO=3 Routing Delay 0.8 0.9 1.0 1.2 ns
tIRD4 FO=4 Routing Delay 1.0 1.2 1.4 1.6 ns
tIRD8 FO=8 Routing Delay 1.9 2.2 2.5 2.9 ns
tIRD12 FO=12 Routing Delay 2.8 3.2 3.7 4.3 ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
54SX Family FPGAs
30 v3.1
A54SX16P Timing Characteristics (continued)
(Worst-Case Commercial Conditions, VCCR= 4.75V, VCCA,VCCI = 3.0V, TJ = 70°C)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network
tHCKH Input LOW to HIGH
(Pad to R-Cell Input) 1.2 1.4 1.5 1.8 ns
tHCKL Input HIGH to LOW
(Pad to R-Cell Input) 1.2 1.4 1.6 1.9 ns
tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 ns
tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 ns
tHCKSW Maximum Skew 0.2 0.2 0.3 0.3 ns
tHP Minimum Period 2.7 3.1 3.6 4.2 ns
fHMAX Maximum Frequency 350 320 280 240 MHz
Routed Array Clock Networks
tRCKH Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) 1.6 1.8 2.1 2.5 ns
tRCKL Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) 1.8 2.0 2.3 2.7 ns
tRCKH Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) 1.8 2.1 2.5 2.8 ns
tRCKL Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) 2.0 2.2 2.5 3.0 ns
tRCKH Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) 1.8 2.1 2.4 2.8 ns
tRCKL Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) 2.0 2.2 2.5 3.0 ns
tRPWH Min. Pulse Width HIGH 2.1 2.4 2.7 3.2 ns
tRPWL Min. Pulse Width LOW 2.1 2.4 2.7 3.2 ns
tRCKSW Maximum Skew (Light Load) 0.5 0.5 0.5 0.7 ns
tRCKSW Maximum Skew (50% Load) 0.5 0.6 0.7 0.8 ns
tRCKSW Maximum Skew (100% Load) 0.5 0.6 0.7 0.8 ns
TTL Output Mo dule Timing
tDLH Data-to-Pad LOW to HIGH 2.4 2.8 3.1 3.7 ns
tDHL Data-to-Pad HIGH to LOW 2.3 2.9 3.2 3.8 ns
tENZL Enable-to-Pad, Z to L 3.0 3.4 3 .9 4.6 ns
tENZH Enable-to-Pad, Z to H 3.3 3.8 4.3 5.0 ns
tENLZ Enable-to-Pad, L to Z 2.3 2.7 3.0 3.5 ns
tENHZ Enable-to-Pad, H to Z 2.8 3.2 3.7 4.3 ns
TTL/PCI Output Module Timing
tDLH Data-to-Pad LOW to HIGH 1.5 1.7 2.0 2.3 ns
tDHL Data-to-Pad HIGH to LOW 1.9 2.2 2.4 2.9 ns
tENZL Enable-to-Pad, Z to L 2.3 2.6 3 .0 3.5 ns
tENZH Enable-to-Pad, Z to H 1.5 1.7 1.9 2.3 ns
tENLZ Enable-to-Pad, L to Z 2.7 3.1 3.5 4.1 ns
tENHZ Enable-to-Pad, H to Z 2.9 3.3 3.7 4.4 ns
v3.1 31
54SX Family FPGAs
A54SX16P Timing Characteristics (continued)
(Worst-Case Commercial Conditions VCCR = 3.0V, VCCA, VCCI = 3.0V, TJ = 70°C)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Units
PCI Output Module Timing1
tDLH Data-to-Pad LOW to HIGH 1.8 2.0 2.3 2.7 ns
tDHL Data-to-Pad HIGH to LOW 1.7 2.0 2.2 2.6 ns
tENZL Enable-to-Pad, Z to L 0.8 1.0 1 .1 1.3 ns
tENZH Enable-to-Pad, Z to H 1.2 1.2 1.5 1.8 ns
tENLZ Enable-to-Pad, L to Z 1.0 1.1 1.3 1.5 ns
tENHZ Enable-to-Pad, H to Z 1.1 1.3 1.5 1.7 ns
TTL Output Mo dule Timing
tDLH Data-to-Pad LOW to HIGH 2.1 2.5 2.8 3.3 ns
tDHL Data-to-Pad HIGH to LOW 2.0 2.3 2.6 3.1 ns
tENZL Enable-to-Pad, Z to L 2.5 2.9 3 .2 3.8 ns
tENZH Enable-to-Pad, Z to H 3.0 3.5 3.9 4.6 ns
tENLZ Enable-to-Pad, L to Z 2.3 2.7 3.1 3.6 ns
tENHZ Enable-to-Pad, H to Z 2.9 3.3 3.7 4.4 ns
Note:
1. Delays based on 10 pF loading.
54SX Family FPGAs
32 v3.1
A54SX32 Timing Characteristics
(Worst-Case Commercial Conditions, VCCR= 4.75V, VCCA,VCCI = 3.0V, TJ = 70°C)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Units
C-Cell Prop agation Delays1
tPD Internal Array Module 0.6 0.7 0.8 0.9 ns
Predicted Routing Delays2
tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 ns
tFC FO=1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns
tRD1 FO=1 Routing Delay 0.3 0.4 0.4 0.5 ns
tRD2 FO=2 Routing Delay 0.7 0.8 0.9 1.0 ns
tRD3 FO=3 Routing Delay 1.0 1.2 1.4 1.6 ns
tRD4 FO=4 Routing Delay 1.4 1.6 1.8 2.1 ns
tRD8 FO=8 Routing Delay 2.7 3.1 3.5 4.1 ns
tRD12 FO=12 Routing Delay 4.0 4.7 5.3 6.2 ns
R-Cell Timing
tRCO Sequential Clock-to-Q 0.8 1.1 1.3 1.4 ns
tCLR Asynchronous Clear-to-Q 0.5 0.6 0.7 0.8 ns
tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns
tSUD Flip-Flop Data Input Set-Up 0.5 0.6 0.7 0.8 ns
tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns
tWASYN Asynchronous Pulse Width 1.4 1.6 1.8 2.1 ns
Input Modul e Pr opagation Delays
tINYH Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns
tINYL Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns
Predicted Input Routing Delays2
tIRD1 FO=1 Routing Delay 0.3 0.4 0.4 0.5 ns
tIRD2 FO=2 Routing Delay 0.7 0.8 0.9 1.0 ns
tIRD3 FO=3 Routing Delay 1.0 1.2 1.4 1.6 ns
tIRD4 FO=4 Routing Delay 1.4 1.6 1.8 2.1 ns
tIRD8 FO=8 Routing Delay 2.7 3.1 3.5 4.1 ns
tIRD12 FO=12 Routing Delay 4.0 4.7 5.3 6.2 ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
v3.1 33
54SX Family FPGAs
A54SX32 Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network
tHCKH Input LOW to HIGH
(Pad to R-Cell Input) 1.9 2.1 2.4 2.8 ns
tHCKL Input HIGH to LOW
(Pad to R-Cell Input) 1.9 2.1 2.4 2.8 ns
tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 ns
tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 ns
tHCKSW Maximum Skew 0.3 0.4 0.4 0.5 ns
tHP Minimum Period 2.7 3.1 3.6 4.2 ns
fHMAX Maximum Frequency 350 320 280 240 MHz
Routed Array Clock Networks
tRCKH Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) 2.4 2.7 3.0 3.5 ns
tRCKL Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) 2.4 2.7 3.1 3.6 ns
tRCKH Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) 2.7 3.0 3.5 4.1 ns
tRCKL Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) 2.7 3.1 3.6 4.2 ns
tRCKH Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) 2.7 3.1 3.5 4.1 ns
tRCKL Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) 2.8 3.2 3.6 4.3 ns
tRPWH Min. Pulse Width HIGH 2.1 2.4 2.7 3.2 ns
tRPWL Min. Pulse Width LOW 2.1 2.4 2.7 3.2 ns
tRCKSW Maximum Skew (Light Load) 0.85 0.98 1.1 1.3 ns
tRCKSW Maximum Skew (50% Load) 1.23 1.4 1 .6 1.9 ns
tRCKSW Maximum Skew (100% Load) 1.30 1.5 1.7 2.0 ns
TTL Output Mo dule Timing1
tDLH Data-to-Pad LOW to HIGH 1.6 1.9 2.1 2.5 ns
tDHL Data-to-Pad HIGH to LOW 1.6 1.9 2.1 2.5 ns
tENZL Enable-to-Pad, Z to L 2.1 2.4 2 .8 3.2 ns
tENZH Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 ns
tENLZ Enable-to-Pad, L to Z 1.4 1.7 1.9 2.2 ns
tENHZ Enable-to-Pad, H to Z 1.3 1.5 1.7 2.0 ns
Note:
1. Delays based on 35pF loading, except tENZL and tENZH . For tENZL an d t ENZH the loading is 5pF.
54SX Family FPGAs
34 v3.1
Pin Description
CLKA/B Clock A and B
These pins are 3.3V/5.0V PCI/TTL clock inputs for clock
distribution networks. The clock input is buffered prior to
clocking the R-cells. If not used, this pin must be set LOW or
HIGH on the board. It must not be left floating. (For
A54SX72A, these clocks can be configured as bidirectional.)
GND Ground
LOW supply voltage.
HCLK Dedicated (Hard-wired)
Array Clock
This pin is the 3.3V/5.0V PCI/TTL clock input for sequential
modules. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
I/O Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL, LVTTL,
3.3V PCI or 5.0V PCI specifications. Unused I/O pins are
automatically tristated by the Designer Series software.
NC No Connection
This pin is not connected to circuitry within the device.
PRA, I/O Probe A
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with
the Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-def ined I/O when veri fica tion ha s been c omplete d.
The pin’s probe capabilities ca n be permanently disabled to
protect programmed design confidentiality.
PRB, I/O Probe B
The Probe B pin is used to output data from any node within
the device. This diagnostic pin can be used in conjunction
with the Probe A pin to allow rea l-time diagnostic ou tput of
any signal path within the device. The Probe B pin can be
used as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be permanently
disabled to protect programmed design confidentiality.
TCK Test Clock
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (refer to Table 2 on page 8). This pin
functions as an I/O when the boundary scan state machine
reaches the “logic reset” state.
TDI Test Data Input
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to Table 2 on page 8). This pin functions as an I/O
when the boundary scan state machine reaches the “logic
reset” state.
TDO Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to Table 2
on page 8). This pin functions as an I/O when the boundary
scan state machine reaches the “logic reset” state.
TMS Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO). In flexible mode when the TMS
pin is set LOW, the TCK, TDI, and TDO pins are boundary
scan pins (refer to Table 2 on page 8). Once the boundary
scan pins are in test mode, they will remain in that mode
until the internal boundary scan state machine reaches the
“logic reset” state. At this point, the boundary scan pins will
be released and will function as regular I/O pins. The “logic
reset” state is reached 5 TCK cycles after the TMS pin is set
HIGH. In dedicated test mode, TMS functions as specifie d in
the IEEE 1149.1 specifications.
VCCI Supply Voltage
Supply voltage for I/Os. See Table 1 on page 8.
VCCA Supply Voltage
Supply voltage for Array. See Table 1 on page 8.
VCCR Supply Voltage
Supply voltage for input tolerance (required for internal
biasing) See Table 1 on page 8.
v3.1 35
54SX Family FPGAs
Package Pin Assignments
84-Pin PLCC (Top View)
184
84-Pin
PLCC
54SX Family FPGAs
36 v3.1
84-Pin PLCC Package
Pin
Number A54SX08
Function Pin
Number A54SX08
Function
1V
CCR 43 VCCR
2GND 44 I/O
3V
CCA 45 HCLK
4 PRA, I/O 46 I/O
5I/O 47I/O
6I/O 48I/O
7V
CCI 49 I/O
8I/O 50I/O
9I/O 51I/O
10 I/O 52 TDO, I/O
11 TCK, I/O 53 I/O
12 TD I, I/O 54 I/O
13 I/O 55 I/O
14 I/O 56 I/O
15 I/O 57 I/O
16 TMS 58 I/O
17 I/O 59 VCCA
18 I/O 60 VCCI
19 I/O 61 GND
20 I/O 62 I/O
21 I/O 63 I/O
22 I/O 64 I/O
23 I/O 65 I/O
24 I/O 66 I/O
25 I/O 67 I/O
26 I/O 68 VCCA
27 GND 69 GND
28 VCCI 70 I/O
29 I/O 71 I/O
30 I/O 72 I/O
31 I/O 73 I/O
32 I/O 74 I/O
33 I/O 75 I/O
34 I/O 76 I/O
35 I/O 77 I/O
36 I/O 78 I/O
37 I/O 79 I/O
38 I/O 80 I/O
39 I/O 81 I/O
40 PRB, I/O 82 I/O
41 VCCA 83 CLKA
42 GND 84 CLKB
54SX Family FPGAs
v3.1 37
Package Pin Assignments (continued)
208-Pin PQFP (Top View)
208-Pin PQFP
1208
54SX Family FPGAs
38 v3.1
208-Pin PQFP
Pin Number A54SX08
Function
A54SX16,
A54SX16P
Function A54SX32
Function Pin Number A54SX08
Function
A54SX16,
A54SX16P
Function A54SX32
Function
1 GND GND GND 54 I/O I/O I/O
2 TDI, I/O TDI , I/O TDI, I/O 5 5 I/O I/O I/O
3 I/O I/O I/O 56 I/O I/O I/O
4 NC I/O I/O 57 I/O I/O I/O
5 I/O I/O I/O 58 I/O I/O I/O
6 NC I/O I/O 59 I/O I/O I/O
7 I/O I/O I/O 60 VCCI VCCI VCCI
8 I/O I/O I/O 61 NC I/O I/O
9 I/O I/O I/O 62 I/O I/O I/O
10 I/O I/O I/O 63 I/O I/O I/O
11 TMS TMS TMS 64 NC I/O I/O
12 VCCI VCCI VCCI 65* I/O I/O NC*
13 I/O I/O I/O 66 I/O I/O I/O
14 NC I/O I/O 67 NC I/O I/O
15 I/O I/O I/O 68 I/O I/O I/O
16 I/O I/O I/O 69 I/O I/O I/O
17 NC I/O I/O 70 NC I/O I/O
18 I/O I/O I/O 71 I/O I/O I/O
19 I/O I/O I/O 72 I/O I/O I/O
20 NC I/O I/O 73 NC I/O I/O
21 I/O I/O I/O 74 I/O I/O I/O
22 I/O I/O I/O 75 NC I/O I/O
23 NC I/O I/O 76 PRB, I/O PRB, I/O PRB, I/O
24 I/O I/O I/O 77 GND GND GND
25 VCCR VCCR VCCR 78 VCCA VCCA VCCA
26 GND GND GND 79 GND GND GND
27 VCCA VCCA VCCA 80 VCCR VCCR VCCR
28 GND GND GND 81 I/O I/O I/O
29 I/O I/O I/O 82 HCLK HCLK HCLK
30 I/O I/O I/O 83 I/O I/O I/O
31 NC I/O I/O 84 I/O I/O I/O
32 I/O I/O I/O 85 NC I/O I/O
33 I/O I/O I/O 86 I/O I/O I/O
34 I/O I/O I/O 87 I/O I/O I/O
35 NC I/O I/O 88 NC I/O I/O
36 I/O I/O I/O 89 I/O I/O I/O
37 I/O I/O I/O 90 I/O I/O I/O
38 I/O I/O I/O 91 NC I/O I/O
39 NC I/O I/O 92 I/O I/O I/O
40 VCCI VCCI VCCI 93 I/O I/O I/O
41 VCCA VCCA VCCA 94 NC I/O I/O
42 I/O I/O I/O 95 I/O I/O I/O
43 I/O I/O I/O 96 I/O I/O I/O
44 I/O I/O I/O 97 NC I/O I/O
45 I/O I/O I/O 98 VCCI VCCI VCCI
46 I/O I/O I/O 99 I/O I/O I/O
47 I/O I/O I/O 100 I/O I/O I/O
48 NC I/O I/O 101 I/O I/O I/O
49 I/O I/O I/O 102 I/O I/O I/O
50 NC I/O I/O 103 TDO, I/O TDO, I/O TDO, I/O
51 I/O I/O I/O 104 I/O I/O I/O
52 GND GND GND 105 GND GND GND
53 I/O I/O I/O 106 NC I/O I/O
* Please note that Pin 65 in the A54SX32—PQ208 is a no connect (NC).
54SX Family FPGAs
v3.1 39
107 I/O I/O I/O 158 I/O I/O I/O
108 NC I/O I/O 159 I/O I/O I/O
109 I/O I/O I/O 160 I/O I/O I/O
110 I/O I/O I/O 161 I/O I/O I/O
111 I/O I/O I/O 162 I/O I/O I/O
112 I/O I/O I/O 163 I/O I/O I/O
113 I/O I/O I/O 164 VCCI VCCI VCCI
114 VCCA VCCA VCCA 165 I/O I/O I/O
115 VCCI VCCI VCCI 166 I/O I/O I/O
116 NC I/O I/O 167 NC I/O I/O
117 I/O I/O I/O 168 I/O I/O I/O
118 I/O I/O I/O 169 I/O I/O I/O
119 NC I/O I/O 170 NC I/O I/O
120 I/O I/O I/O 171 I/O I/O I/O
121 I/O I/O I/O 172 I/O I/O I/O
122 NC I/O I/O 173 NC I/O I/O
123 I/O I/O I/O 174 I/O I/O I/O
124 I/O I/O I/O 175 I/O I/O I/O
125 NC I/O I/O 176 NC I/O I/O
126 I/O I/O I/O 177 I/O I/O I/O
127 I/O I/O I/O 178 I/O I/O I/O
128 I/O I/O I/O 179 I/O I/O I/O
129 GND GND GND 180 CLKA CLKA CLKA
130 VCCA VCCA VCCA 181 CLKB CLKB CLKB
131 GND GND GND 182 VCCR VCCR VCCR
132 VCCR VCCR VCCR 183 GND GND GND
133 I/O I/O I/O 184 VCCA VCCA VCCA
134 I/O I/O I/O 185 GND GND GND
135 NC I/O I/O 186 PRA, I/O PRA, I/O PRA, I/O
136 I/O I/O I/O 187 I/O I/O I/O
137 I/O I/O I/O 188 I/O I/O I/O
138 NC I/O I/O 189 NC I/O I/O
139 I/O I/O I/O 190 I/O I/O I/O
140 I/O I/O I/O 191 I/O I/O I/O
141 NC I/O I/O 192 NC I/O I/O
142 I/O I/O I/O 193 I/O I/O I/O
143 NC I/O I/O 194 I/O I/O I/O
144 I/O I/O I/O 195 NC I/O I/O
145 VCCA VCCA VCCA 196 I/O I/O I/O
146 GND GND GND 197 I/O I/O I/O
147 I/O I/O I/O 198 NC I/O I/O
148 VCCI VCCI VCCI 199 I/O I/O I/O
149 I/O I/O I/O 200 I/O I/O I/O
150 I/O I/O I/O 201 VCCI VCCI VCCI
151 I/O I/O I/O 202 NC I/O I/O
152 I/O I/O I/O 203 NC I/O I/O
153 I/O I/O I/O 204 I/O I/O I/O
154 I/O I/O I/O 205 NC I/O I/O
155 NC I/O I/O 206 I/O I/O I/O
156 NC I/O I/O 207 I/O I/O I/O
157 GND GN D GND 208 TCK, I/O TCK, I/ O TC K, I/O
208-Pin PQFP (Continued)
Pin Number A54SX08
Function
A54SX16,
A54SX16P
Function A54SX32
Function Pin Number A54SX08
Function
A54SX16,
A54SX16P
Function A54SX32
Function
* Please note that Pin 65 in the A54SX32—PQ208 is a no connect (NC).
54SX Family FPGAs
40 v3.1
Package Pin Assignments (continued)
144-Pin TQFP (Top View)
1
144
144-Pin
TQFP
54SX Family FPGAs
v3.1 41
144-Pin TQFP
Pin Number A54SX08
Function A54SX16P
Function A54SX32
Function Pin Number A54SX08
Function A54SX16P
Function A54SX32
Function
1 GND GND GND 41 I/O I/O I/O
2 TDI, I/O TDI, I/O TDI, I/O 42 I/O I/O I/O
3 I/O I/O I/O 43 I/O I/O I/O
4 I/O I/O I/O 44 VCCI VCCI VCCI
5 I/O I/O I/O 45 I/O I/O I/O
6 I/O I/O I/O 46 I/O I/O I/O
7 I/O I/O I/O 47 I/O I/O I/O
8 I/O I/O I/O 48 I/O I/O I/O
9 TMS TMS TMS 49 I/O I/O I/O
10 VCCI VCCI VCCI 50 I/O I/O I/O
11 GND GND GND 51 I/O I/O I/O
12 I/O I/O I/O 52 I/O I/O I/O
13 I/O I/O I/O 53 I/O I/O I/O
14 I/O I/O I/O 54 PRB, I/O PRB, I/O PRB, I/O
15 I/O I/O I/O 55 I/O I/O I/O
16 I/O I/O I/O 56 VCCA VCCA VCCA
17 I/O I/O I/O 57 GND GND GND
18 I/O I/O I/O 58 VCCR VCCR VCCR
19 VCCR VCCR VCCR 59 I/O I/O I/O
20 VCCA VCCA VCCA 60 HCLK HCLK HCLK
21 I/O I/O I/O 61 I/O I/O I/O
22 I/O I/O I/O 62 I/O I/O I/O
23 I/O I/O I/O 63 I/O I/O I/O
24 I/O I/O I/O 64 I/O I/O I/O
25 I/O I/O I/O 65 I/O I/O I/O
26 I/O I/O I/O 66 I/O I/O I/O
27 I/O I/O I/O 67 I/O I/O I/O
28 GND GND GND 68 VCCI VCCI VCCI
29 VCCI VCCI VCCI 69 I/O I/O I/O
30 VCCA VCCA VCCA 70 I/O I/O I/O
31 I/O I/O I /O 71 TDO, I/O TDO, I/O TDO, I/O
32 I/O I/O I/O 72 I/O I/O I/O
33 I/O I/O I/O 73 GND GND GND
34 I/O I/O I/O 74 I/O I/O I/O
35 I/O I/O I/O 75 I/O I/O I/O
36 GND GND GND 76 I/O I/O I/O
37 I/O I/O I/O 77 I/O I/O I/O
38 I/O I/O I/O 78 I/O I/O I/O
39 I/O I/O I/O 79 VCCA VCCA VCCA
40 I/O I/O I/O 80 VCCI VCCI VCCI
54SX Family FPGAs
42 v3.1
81 GND GND GND 113 I/O I/O I/O
82 I/O I/O I/O 114 I/O I/O I/O
83 I/O I/O I/O 115 VCCI VCCI VCCI
84 I/O I/O I/O 116 I/O I/O I/O
85 I/O I/O I/O 117 I/O I/O I/O
86 I/O I/O I/O 118 I/O I/O I/O
87 I/O I/O I/O 119 I/O I/O I/O
88 I/O I/O I/O 120 I/O I/O I/O
89 VCCA VCCA VCCA 121 I/O I/O I/O
90 VCCR VCCR VCCR 122 I/O I/O I/O
91 I/O I/O I/O 123 I/O I/O I/O
92 I/O I/O I/O 124 I/O I/O I/O
93 I/O I/O I/O 125 CLKA CLKA CLKA
94 I/O I/O I/O 126 CLKB CLKB CLKB
95 I/O I/O I/O 127 VCCR VCCR VCCR
96 I/O I/O I/O 128 GND GND GND
97 I/O I/O I/O 129 VCCA VCCA VCCA
98 VCCA VCCA VCCA 130 I/O I/O I/O
99 GND GND GND 131 PRA, I/O PRA, I/O PRA, I/O
100 I/O I/O I/O 132 I/O I/O I/O
101 GND GND GND 133 I/O I/O I/O
102 VCCI VCCI VCCI 134 I/O I/O I/O
103 I/O I/O I/O 135 I/O I/O I/O
104 I/O I/O I/O 136 I/O I/O I/O
105 I/O I/O I/O 137 I/O I/O I/O
106 I/O I/O I/O 138 I/O I/O I/O
107 I/O I/O I/O 139 I/O I/O I/O
108 I/O I/O I/O 140 VCCI VCCI VCCI
109 GND GND GND 141 I/O I/O I/O
110 I/O I/O I/O 142 I/O I/O I/O
111 I/O I/O I/O 143 I/O I/O I/O
112 I/O I/O I/O 144 TCK, I/O TCK, I/O TCK, I/O
113 I/O I/O I/O
144-Pin TQFP (Continued)
Pin Number A54SX08
Function A54SX16P
Function A54SX32
Function Pin Number A54SX08
Function A54SX16P
Function A54SX32
Function
54SX Family FPGAs
v3.1 43
Package Pin Assignments (continued)
176-Pin TQFP (Top View)
176-Pin
TQFP
176
1
54SX Family FPGAs
44 v3.1
176-Pin TQFP
Pin Number A54SX08
Function
A54SX16,
A54SX16P
Function A54SX32
Function Pin Number A54SX08
Function
A54SX16,
A54SX16P
Function A54SX32
Function
1 GND GND GND 45 I/O I/O I/O
2 TDI, I/O TDI, I/O TDI, I/O 46 I/O I/O I/O
3 NC I/O I/O 47 I/O I/O I/O
4 I/O I/O I/O 48 I/O I/O I/O
5 I/O I/O I/O 49 I/O I/O I/O
6 I/O I/O I/O 50 I/O I/O I/O
7 I/O I/O I/O 51 I/O I/O I/O
8 I/O I/O I/O 52 VCCI VCCI VCCI
9 I/O I/O I/O 53 I/O I/O I/O
10 TMS TMS TMS 54 NC I/O I/O
11 VCCI VCCI VCCI 55 I/O I/O I/O
12 NC I/O I/O 56 I/O I/O I/O
13 I/O I/O I/O 57 NC I/O I/O
14 I/O I/O I/O 58 I/O I/O I/O
15 I/O I/O I/O 59 I/O I/O I/O
16 I/O I/O I/O 60 I/O I/O I/O
17 I/O I/O I/O 61 I/O I/O I/O
18 I/O I/O I/O 62 I/O I/O I/O
19 I/O I/O I/O 63 I/O I/O I/O
20 I/O I/O I/O 64 PRB, I/O PRB, I/O PRB, I/O
21 GND GND GND 65 GND GND GND
22 VCCA VCCA VCCA 66 VCCA VCCA VCCA
23 GND GND GND 67 VCCR VCCR VCCR
24 I/O I/O I/O 68 I/O I/O I/O
25 I/O I/O I/O 69 HCLK HCLK HCLK
26 I/O I/O I/O 70 I/O I/O I/O
27 I/O I/O I/O 71 I/O I/O I/O
28 I/O I/O I/O 72 I/O I/O I/O
29 I/O I/O I/O 73 I/O I/O I/O
30 I/O I/O I/O 74 I/O I/O I/O
31 I/O I/O I/O 75 I/O I/O I/O
32 VCCI VCCI VCCI 76 I/O I/O I/O
33 VCCA VCCA VCCA 77 I/O I/O I/O
34 I/O I/O I/O 78 I/O I/O I/O
35 I/O I/O I/O 79 NC I/O I/O
36 I/O I/O I/O 80 I/O I/O I/O
37 I/O I/O I/O 81 NC I/O I/O
38 I/O I/O I/O 82 VCCI VCCI VCCI
39 I/O I/O I/O 83 I/O I/O I/O
40 NC I/O I/O 84 I/O I/O I/O
41 I/O I/O I/O 85 I/O I/O I/O
42 NC I/O I/O 86 I/O I/O I/O
43 I/O I/O I /O 87 TDO, I/O TDO, I/O TDO, I/O
44 GND GND GND 88 I/O I/O I/O
54SX Family FPGAs
v3.1 45
89 GND GND GND 133 GND GND GND
90 NC I/O I/O 134 I/O I/O I/O
91 NC I/O I/O 135 I/O I/O I/O
92 I/O I/O I/O 136 I/O I/O I/O
93 I/O I/O I/O 137 I/O I/O I/O
94 I/O I/O I/O 138 I/O I/O I/O
95 I/O I/O I/O 139 I/O I/O I/O
96 I/O I/O I/O 140 VCCI VCCI VCCI
97 I/O I/O I/O 141 I/O I/O I/O
98 VCCA VCCA VCCA 142 I/O I/O I/O
99 VCCI VCCI VCCI 143 I/O I/O I/O
100 I/O I/O I/O 144 I/O I/O I/O
101 I/O I/O I/O 145 I/O I/O I/O
102 I/O I/O I/O 146 I/O I/O I/O
103 I/O I/O I/O 147 I/O I/O I/O
104 I/O I/O I/O 148 I/O I/O I/O
105 I/O I/O I/O 149 I/O I/O I/O
106 I/O I/O I/O 150 I/O I/O I/O
107 I/O I/O I/O 151 I/O I/O I/O
108 GND GND GND 152 CLKA CLKA CLKA
109 VCCA VCCA VCCA 153 CLKB CLKB CLKB
110 GND GND GND 154 VCCR VCCR VCCR
111 I/O I/O I/O 155 GND GND GND
112 I/O I/O I/O 156 VCCA VCCA VCCA
113 I/O I/O I/O 157 PRA, I/O PRA, I/O PRA, I/O
114 I/O I/O I/O 158 I/O I/O I/O
115 I/O I/O I/O 159 I/O I/O I/O
116 I/O I/O I/O 160 I/O I/O I/O
117 I/O I/O I/O 161 I/O I/O I/O
118 NC I/O I/O 162 I/O I/O I/O
119 I/O I/O I/O 163 I/O I/O I/O
120 NC I/O I/O 164 I/O I/O I/O
121 NC I/O I/O 165 I/O I/O I/O
122 VCCA VCCA VCCA 166 I/O I/O I/O
123 GND GND GND 167 I/O I/O I/O
124 VCCI VCCI VCCI 168 NC I/O I/O
125 I/O I/O I/O 169 VCCI VCCI VCCI
126 I/O I/O I/O 170 I/O I/O I/O
127 I/O I/O I/O 171 NC I/O I/O
128 I/O I/O I/O 172 NC I/O I/O
129 I/O I/O I/O 173 NC I/O I/O
130 I/O I/O I/O 174 I/O I/O I/O
131 NC I/O I/O 175 I/O I/O I/O
132 NC I/O I/O 176 TCK, I/O TCK, I/O TCK, I/O
176-Pin TQFP (Continued)
Pin Number A54SX08
Function
A54SX16,
A54SX16P
Function A54SX32
Function Pi n Number A54SX08
Function
A54SX16,
A54SX16P
Function A54SX32
Function
54SX Family FPGAs
46 v3.1
Package Pin Assignments (continued)
100-Pin VQFP (Top View)
1
100-Pin
VQFP
100
54SX Family FPGAs
v3.1 47
100-VQFP
Pin Number A54SX08
Function
A54SX16,
A54SX16P
Function Pin Numbe r A54SX08
Function
A54SX16
A54SX16P
Function
1 GND GND 51 GND GND
2 TDI, I/O TDI, I/O 52 I/O I/O
3 I/O I/O 53 I/O I/O
4 I/O I/O 54 I/O I/O
5 I/O I/O 55 I/O I/O
6 I/O I/O 56 I/O I/O
7TMSTMS 57V
CCA VCCA
8V
CCI VCCI 58 VCCI VCCI
9 GND GND 59 I/O I/O
10 I/O I/O 60 I/O I/O
11 I/O I/O 61 I/O I/O
12 I/O I/O 62 I/O I/O
13 I/O I/O 63 I/O I/O
14 I/O I/O 64 I/O I/O
15 I/O I/O 65 I/O I/O
16 I/O I/O 66 I/O I/O
17 I/O I/O 67 VCCA VCCA
18 I/O I/O 68 GND GND
19 I/O I/O 69 GND GND
20 VCCI VCCI 70 I/O I/O
21 I/O I/O 71 I/O I/O
22 I/O I/O 72 I/O I/O
23 I/O I/O 73 I/O I/O
24 I/O I/O 74 I/O I/O
25 I/O I/O 75 I/O I/O
26 I/O I/O 76 I/O I/O
27 I/O I/O 77 I/O I/O
28 I/O I/O 78 I/O I/O
29 I/O I/O 79 I/O I/O
30 I/O I/O 80 I/O I/O
31 I/O I/O 81 I/O I/O
32 I/O I/O 82 VCCI VCCI
33 I/O I/O 83 I/O I/O
34 PRB, I/O PRB, I/O 84 I/O I/O
35 VCCA VCCA 85 I/O I/O
36 GND GND 86 I/O I/O
37 VCCR VCCR 87 CLKA CLKA
38 I/O I/O 88 CLKB CLKB
39 HCLK HCLK 89 VCCR VCCR
40 I/O I/O 90 VCCA VCCA
41 I/O I/O 91 GND GND
42 I/O I/O 92 PRA, I/O PRA, I/O
43 I/O I/O 93 I/O I/O
44 VCCI VCCI 94 I/O I/O
45 I/O I/O 95 I/O I/O
46 I/O I/O 96 I/O I/O
47 I/O I/O 97 I/O I/O
48 I/O I/O 98 I/O I/O
49 TDO, I/O TDO, I/O 99 I/O I/O
50 I/O I/O 100 TCK, I/O TCK, I/O
54SX Family FPGAs
48 v3.1
Package Pin Assignments (continued)
313-Pin PBGA (Top View)
123456789101112131415
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
16 17 18 19 20 21 22 23 24 25
12345678910111213141516171819202122232425
54SX Family FPGAs
v3.1 49
313-Pin PBGA
Pin Number A54SX32
Function Pin Number A54SX32
Function Pin Number A54SX32
Function Pin Number A54SX32
Function
A1 GND AC15 I/O C5 NC F20 I/O
A3 NC AC17 I/O C7 I/O F22 I/O
A5 I/O AC19 I/O C9 I/O F24 I/O
A7 I/O AC21 I/O C11 I/O G1 I/O
A9 I/O AC23 I/O C13 VCCI G3 TMS
A11 I/O AC25 NC C15 I/O G5 I/O
A13 VCCR AD2 GND C17 I/O G7 I/O
A15 I/O AD4 I/O C19 VCCI G9 VCCI
A17 I/O AD6 VCCI C21 I/O G11 I/O
A19 I/O AD8 I/O C23 I/O G13 CLKB
A21 I/O AD10 I/O C25 NC G15 I/O
A23 NC AD12 PRB, I/O D2 I/O G17 I/O
A25 GND AD14 I/O D4 NC G19 I/O
AA1 I/O AD16 I/O D6 I/O G21 I/O
AA3 I/O AD18 I/O D8 I/O G23 I/O
AA5 NC AD20 I/O D10 I/O G25 I/O
AA7 I/O AD22 NC D12 I/O H2 I/O
AA9 NC AD24 I/O D14 I/O H4 I/O
AA11 I/O AE1 NC D16 I/O H6 I/O
AA13 I/O AE3 I/O D18 I/O H8 I/O
AA15 I/O AE5 I/O D20 I/O H10 I/O
AA17 I/O AE7 I/O D22 I/O H12 PRA, I/O
AA19 I/O AE9 I/O D24 NC H14 I/O
AA21 I/O AE11 I/O E1 I/O H16 I/O
AA23 NC AE13 VCCA E3 NC H18 NC
AA25 I/O AE15 I/O E5 I/O H20 I/O
AB2 NC AE17 I/O E7 I/O H22 VCCI
AB4 NC AE19 I/O E9 I/O H24 I/O
AB6 I/O AE21 I/O E11 I/O J1 I/O
AB8 I/O AE23 TDO, I/O E13 VCCA J3 I/O
AB10 I/O AE25 GND E15 I/O J5 I/O
AB12 I/O B2 TCK, I/O E17 I/O J7 NC
AB14 I/O B4 I/O E19 I/O J9 I/O
AB16 I/O B6 I/O E21 I/O J11 I/O
AB18 VCCI B8 I/O E23 I/O J13 CLKA
AB20 NC B10 I/O E25 I/O J15 I/O
AB22 I/O B12 I/O F2 I/O J17 I/O
AB24 I/O B14 I/O F4 I/O J19 I/O
AC1 I/O B16 I/O F6 NC J21 GND
AC3 I/O B18 I/O F8 I/O J23 I/O
AC5 I/O B20 I/O F10 NC J25 I/O
AC7 I/O B22 I/O F12 I/O K2 I/O
AC9 I/O B24 I/O F14 I/O K4 I/O
AC11 I/O C1 TDI, I/O F16 NC K6 I/O
AC13 VCCR C3 I/O F18 I/O K8 VCCI
54SX Family FPGAs
50 v3.1
K10 I/O N3 VCCA R21 I/O V18 I/O
K12 I/O N5 VCCR R23 I/O V20 I/O
K14 I/O N7 I/O R25 I/O V22 VCCA
K16 I/O N9 VCCI T2 I/O V24 VCCI
K18 I/O N11 GND T4 I/O W1 I/O
K20 VCCA N13 GND T6 I/O W3 I/O
K22 I/O N15 GND T8 I/O W5 I/O
K24 I/O N17 I/O T10 I/O W7 NC
L1 I/O N19 I/O T12 I/O W9 I/O
L3 I/O N21 I/O T14 HCLK W11 I/O
L5 I/O N23 VCCR T16 I/O W13 VCCI
L7 I/O N25 VCCA T18 I/O W15 I/O
L9 I/O P2 I/O T20 I/O W17 I/O
L11 I/O P4 I/O T22 I/O W19 I/O
L13 GND P6 I/O T24 I/O W21 I/O
L15 I/O P8 I/O U1 I/O W23 I/O
L17 I/O P10 I/O U3 I/O W25 I/O
L19 I/O P12 GND U5 VCCI Y2 I/O
L21 I/O P14 GND U7 I/O Y4 I/O
L23 I/O P16 I/O U9 I/O Y6 I/O
L25 I/O P18 I/O U15 I/O Y8 I/O
M2 I/O P20 NC U17 I/O Y10 I/O
M4 I/O P22 I/O U19 I/O Y12 I/O
M6 I/O P24 I/O U21 I/O Y14 I/O
M8 I/O R1 I/O U23 I/O Y16 I/O
M10 I/O R3 I/O U25 I/O Y18 I/O
M12 GND R5 I/O V2 VCCA Y20 NC
M14 GND R7 I/O V4 I/O Y22 I/O
M16 VCCI R9 I/O V6 I/O Y24 NC
M18 I/O R11 I/O V8 I/O
M20 I/O R13 GND V10 I/O
M22 I/O R15 I/O V12 I/O
M24 I/O R17 I/O V14 I/O
N1 I/O R19 I/O V16 NC
313-Pin PBGA (Continued)
Pin Number A54SX32
Function Pin Number A54SX32
Function Pin Number A54SX32
Function Pin Number A54SX32
Function
54SX Family FPGAs
v3.1 51
Package Pin Assignments (continued)
329-Pin PBGA (Top View)
2322212019181716151410 11 12 13987654321
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
54SX Family FPGAs
52 v3.1
329-Pin PBGA
Pin Number A54SX32
Function Pin Number A54SX32
Function Pin Number A54SX32
Function Pin Number A54SX32
Function
A1 GND AA23 VCCI AC22 VCCI C21 VCCI
A2 GND AB1 I/O AC23 GND C22 GND
A3 VCCI AB2 GND B1 VCCI C23 NC
A4 NC AB3 I/O B2 GND D1 I/O
A5 I/O AB4 I/O B3 I/O D2 I/O
A6 I/O AB5 I/O B4 I/O D3 I/O
A7 VCCI AB6 I/O B5 I/O D4 TCK, I/O
A8 NC AB7 I/O B6 I/O D5 I/O
A9 I/O AB8 I/O B7 I/O D6 I/O
A10 I/O AB9 I/O B8 I/O D7 I/O
A11 I/O AB10 I/O B9 I/O D8 I/O
A12 I/O AB11 PRB, I/O B10 I/O D9 I/O
A13 CLKB AB12 I/O B11 I/O D10 I/O
A14 I/O AB13 HCLK B12 PRA, I/O D11 VCCA
A15 I/O AB14 I/O B13 CLKA D12 VCCR
A16 I/O AB15 I/O B14 I/O D13 I/O
A17 I/O AB16 I/O B15 I/O D14 I/O
A18 I/O AB17 I/O B16 I/O D15 I/O
A19 I/O AB18 I/O B17 I/O D16 I/O
A20 I/O AB19 I/O B18 I/O D17 I/O
A21 NC AB20 I/O B19 I/O D18 I/O
A22 VCCI AB21 I/O B20 I/O D19 I/O
A23 GND AB22 GND B21 I/O D20 I/O
AA1 VCCI AB23 I/O B22 GND D21 I/O
AA2 I/O AC1 GND B23 VCCI D22 I/O
AA3 GND AC2 VCCI C1 NC D23 I/O
AA4 I/O AC3 NC C2 TDI, I/O E1 VCCI
AA5 I/O AC4 I/O C3 GND E2 I/O
AA6 I/O AC5 I/O C4 I/O E3 I/O
AA7 I/O AC6 I/O C5 I/O E4 I/O
AA8 I/O AC7 I/O C6 I/O E20 I/O
AA9 I/O AC8 I/O C7 I/O E21 I/O
AA10 I/O AC9 VCCI C8 I/O E22 I/O
AA11 I/O AC10 I/O C9 I/O E23 I/O
AA12 I/O AC11 I/O C10 I/O F1 I/O
AA13 I/O AC12 I/O C11 I/O F2 TMS
AA14 I/O AC13 I/O C12 I/O F3 I/O
AA15 I/O AC14 I/O C13 I/O F4 I/O
AA16 I/O AC15 NC C14 I/O F20 I/O
AA17 I/O AC16 I/O C15 I/O F21 I/O
AA18 I/O AC17 I/O C16 I/O F22 I/O
AA19 I/O AC18 I/O C17 I/O F23 I/O
AA20 TDO, I/O AC19 I/O C18 I/O G1 I/O
AA21 VCCI AC20 I/O C19 I/O G2 I/O
AA22 I/O AC21 NC C20 I/O G3 I/O
54SX Family FPGAs
v3.1 53
G4 I/O L22 I/O R20 I/O Y10 I/O
G20 I/O L23 NC R21 I/O Y11 I/O
G21 I/O M1 I/O R22 I/O Y12 VCCA
G22 I/O M2 I/O R23 I/O Y13 VCCR
G23 GND M3 I/O T1 I/O Y14 I/O
H1 I/O M4 VCCA T2 I/O Y15 I/O
H2 I/O M10 GND T3 I/O Y16 I/O
H3 I/O M11 GND T4 I/O Y17 I/O
H4 I/O M12 GND T20 I/O Y18 I/O
H20 VCCA M13 GND T21 I/O Y19 I/O
H21 I/O M14 GND T22 I/O Y20 GND
H22 I/O M20 VCCA T23 I/O Y21 I/O
H23 I/O M21 I/O U1 I/O Y22 I/O
J1 NC M22 I/O U2 I/O Y23 I/O
J2 I/O M23 VCCI U3 VCCA
J3 I/O N1 I/O U4 I/O
J4 I/O N2 I/O U20 I/O
J20 I/O N3 I/O U21 VCCA
J21 I/O N4 I/O U22 I/O
J22 I/O N10 GND U23 I/O
J23 I/O N11 GND V1 VCCI
K1 I/O N12 GND V2 I/O
K2 I/O N13 GND V3 I/O
K3 I/O N14 GND V4 I/O
K4 I/O N20 NC V20 I/O
K10 GND N21 I/O V21 I/O
K11 GND N22 I/O V22 I/O
K12 GND N23 I/O V23 I/O
K13 GND P1 I/O W1 I/O
K14 GND P2 I/O W2 I/O
K20 I/O P3 I/O W3 I/O
K21 I/O P4 I/O W4 I/O
K22 I/O P10 GND W20 I/O
K23 I/O P11 GND W21 I/O
L1 I/O P12 GND W22 I/O
L2 I/O P13 GND W23 NC
L3 I/O P14 GND Y1 NC
L4 VCCR P20 I/O Y2 I/O
L10 GND P21 I/O Y3 I/O
L11 GND P22 I/O Y4 GND
L12 GND P23 I/O Y5 I/O
L13 GND R1 I/O Y6 I/O
L14 GND R2 I/O Y7 I/O
L20 VCCR R3 I/O Y8 I/O
L21 I/O R4 I/O Y9 I/O
329-Pin PBGA
Pin Number A54SX32
Function Pin Number A54SX32
Function Pin Number A54SX32
Function Pin Number A54SX32
Function
54SX Family FPGAs
54 v3.1
Package Pin Assignments (Continued)
144-Pin FBGA (Top View)
12345678910 11 12
A
B
C
D
E
F
G
H
J
K
L
M
54SX Family FPGAs
v3.1 55
144-Pin FBGA
Pin Number A54SX08
Function Pin Number A54SX08
Function Pin Number A54SX08
Function
A1 I/O E1 I/O J1 I/O
A2 I/O E2 I/O J2 I/O
A3 I/O E3 I/O J3 I/O
A4 I/O E4 I/O J4 I/O
A5 VCCA E5 TMS J5 I/O
A6 GND E6 VCCI J6 PRB, I/O
A7 CLKA E7 VCCI J7 I/O
A8 I/O E8 VCCI J8 I/O
A9 I/O E9 VCCA J9 I/O
A10 I/O E10 I/O J10 I/O
A11 I/O E11 GND J11 I/O
A12 I/O E12 I/O J12 VCCA
B1 I/O F1 I/O K1 I/O
B2 GND F2 I/O K2 I/O
B3 I/O F3 VCCR K3 I/O
B4 I/O F4 I/O K4 I/O
B5 I/O F5 GND K5 I/O
B6 I/O F6 GND K6 I/O
B7 CLKB F7 GND K7 GND
B8 I/O F8 VCCI K8 I/O
B9 I/O F9 I/O K9 I/O
B10 I/O F10 GND K10 GND
B11 GND F11 I/O K11 I/O
B12 I/O F12 I/O K12 I/O
C1 I/O G1 I/O L1 GND
C2 I/O G2 GND L2 I/O
C3 TCK, I/O G3 I/O L3 I/O
C4 I/O G4 I/O L4 I/O
C5 I/O G5 GND L5 I/O
C6 PRA, I/O G6 GND L6 I/O
C7 I/O G7 GND L7 HCLK
C8 I/O G8 VCCI L8 I/O
C9 I/O G9 I/O L9 I/O
C10 I/O G10 I/O L10 I/O
C11 I/O G11 I/O L11 I/O
C12 I/O G12 I/O L12 I/O
D1 I/O H1 I/O M1 I/O
D2 VCCI H2 I/O M2 I/O
D3 TDI, I/O H3 I/O M3 I/O
D4 I/O H4 I/O M4 I/O
D5 I/O H5 VCCA M5 I/O
D6 I/O H6 VCCA M6 I/O
D7 I/O H7 VCCI M7 VCCA
D8 I/O H8 VCCI M8 I/O
D9 I/O H9 VCCA M9 I/O
D10 I/O H10 I/O M10 I/O
D11 I/O H11 I/O M11 TDO, I/O
D12 I/O H12 VCCR M12 I/O
54SX Family FPGAs
56 v3.1
List of Changes
The following table lists critical changes that were made in the current version of the document.
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production.” The definition of these categories
are as follows:
Product Brief
The product brief is a modified version of an advanced datasheet containing general product information. This brief
summarizes specific device and family information for unreleased products.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades.
This information can be used as estimates but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be fi nal.
Previous version Changes in current version (v3.1) Page
v3.0.1 The storage temperature in the “Absolute Maximum Ratings1” table on page 10 was
updated. page 10
Table 1 on page 8 was updated. page 8
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