Rev. 0321K–EPROM–4/2004
Features
Fast Read Access Time - 45 ns
Low-Power CMOS Operation
100 µA max. Standby
25 mA max. Active at 5 MHz
JEDEC Standard Packages
32-Lead 600-mil PDIP
32-Lead PLCC
32-Lead TSOP
5V ± 10% Supply
High Reliability CMOS Technology
2000V ESD Protection
200 mA Latchup Immunity
Rapid Programming Algorithm - 100 µs/byte (typical)
CMOS and TTL Compatible Inputs and Outputs
Integrated Product Identification Code
Commercial, Industrial and Automotive Temperature Ranges
Description
The AT27C010 is a low-power, high-performance 1,048,576-bit one-time programma-
ble read only memory (OTP EPROM) organized as 128K by 8 bits. They require only
one 5V power supply in normal read mode operation. Any byte can be accessed in
less than 45 ns, eliminating the need for speed reducing WAIT states on high-perfor-
mance microprocessor systems.
In read mode, the AT27C010 typically consumes only 8 mA. Standby mode supply
current is typically less than 10 µA.
1-Megabit
(128K x 8)
OTP EPROM
AT27C010
1M bit EPROM
Pin Configurations
Pin Name Function
A0 - A16 Addresses
O0 - O7 Outputs
CE Chip Enable
OE Output Enable
PGM Program Strobe
NC No Connect
TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
PGM
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
A1
A2
A3
PLCC Top View
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
O0
A14
A13
A8
A9
A11
OE
A10
CE
O7
4
3
2
1
32
31
30
14
15
16
17
18
19
20
O1
O2
GND
O3
O4
O5
O6
A12
A15
A16
VPP
VCC
PGM
NC
(continued)
PDIP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
PGM
NC
A14
A13
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
2AT27C010
0321K–EPROM–4/2004
The AT27C010 is available in a choice of industry standard JEDEC-approved one-time
programmable (OTP) plastic PDIP, PLCC, and TSOP packages. All devices feature two
line control (CE, OE) to give designers the flexibility to prevent bus contention.
With 128K byte storage capability, the AT27C010 allows firmware to be stored reliably
and to be accessed by the system without the delays of mass storage media.
Atmel’s 27C010 has additional features to ensure high quality and efficient production
use. The Rapid™ Programming Algorithm reduces the time required to program the part
and guarantees reliable programming. Programming time is typically only 100 µs/byte.
The Integrated Product Identification Code electronically identifies the device and manu-
facturer. This feature is used by industry standard programming equipment to select the
proper programming algorithms and voltages.
System
Considerations
Switching between active and standby conditions via the Chip Enable pin may produce
transient voltage excursions. Unless accommodated by the system design, these tran-
sients may exceed data sheet limits, resulting in device non-conformance. At a
minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should
be utilized for each device. This capacitor should be connected between the V CC and
Ground terminals of the device, as close to the device as possible. Additionally, to stabi-
lize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF
bulk electrolytic capacitor should be utilized, again connected between the VCC and
Ground terminals. This capacitor should be positioned as close as possible to the point
where the power supply is connected to the array.
Block Diagram
3
AT27C010
0321K–EPROM–4/2004
Note: 1. Minimum voltage is -0.6V dc which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V dc which may overshoot to +7.0 volts for pulses of less than 20 ns.
Note: 1. X can be VIL or VIH.
2. Refer to Programming Characteristics.
3. VH = 12.0 ± 0.5V.
4. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
Absolute Maximum Ratings*
Temperature Under Bias................................ -5C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device at these or any other
conditions beyond those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V(1)
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Operating Modes
Mode\Pin CE OE PGM Ai VPP Outputs
Read VIL VIL X(1) Ai X DOUT
Output Disable X VIH XXXHigh Z
Standby VIH XXXXHigh Z
Rapid Program(2) VIL VIH VIL Ai VPP DIN
PGM Verify VIL VIL VIH Ai VPP DOUT
PGM Inhibit VIH XX X V
PP High Z
Product Identification(4) VIL VIL X
A9 = VH(3)
A0 = VIH or VIL
A1 - A16 = VIL
X Identification Code
4AT27C010
0321K–EPROM–4/2004
Note: 1. VCC must be applied simultaneously or before VPP
, and removed simultaneously or after VPP
..
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of I
CC and IPP
..
Note: 1. 2,3,4,5. - see AC Waveforms for Read Operation.
DC and AC Operating Conditions for Read Operation
AT27C010
-45 -70 -90
Operating
Te mp . ( C a s e)
Com. 0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C
Auto. -40°C - 125°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10%
DC and Operating Characteristics for Read Operation
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC
Com., Ind. ± A
Auto. ± A
ILO Output Leakage Current VOUT = 0V to VCC
Com., Ind. ± A
Auto. ±10 µA
IPP1(2) VPP(1)) Read/Standby Current VPP = VCC 10 µA
ISB VCC(1) Standby Current
ISB1 (CMOS), CE = VCC ± 0.3V 100 µA
ISB2 (TTL), CE = 2.0 to VCC + 0.5V 1mA
ICC VCC Active Current f = 5 MHz, IOUT = 0 mA,
CE = VIL
25 mA
VIL Input Low Voltage -0.6 0.8 V
VIH Input High Voltage 2.0 VCC + 0.5 V
VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Output High Voltage IOH = -400 µA2.4 V
AC Characteristics for Read Operation
Symbol Parameter Condition
AT27C010
Units
-45 -70 -90
MinMaxMinMaxMinMax
tACC(3) Address to Output Delay CE =OE=V
IL 45 70 90 ns
tCE(2) CE to Output Delay OE = VIL 45 70 90 ns
tOE(2)(3) OE to Output Delay CE = VIL 20 30 35 ns
tDF(4)(5) OE or CE High to Output Float, whichever occurred first 20 25 25 ns
tOH Output Hold from Address, CE or OE, whichever occurred first 7 7 0 ns
5
AT27C010
0321K–EPROM–4/2004
AC Waveforms for Read
Operation(1)
Note: 1. Timing measurement reference level is 1.5V for -45 devices. Input AC drive levels are
VIL = 0.0V and VIH = 3.0V. Timing measurement reference levels for all other speed
grades are VOL = 0.8V and VOH = 2.0V. Input AC drive levels are VIL = 0.45V and VIH =
2.4V.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on t
CE.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
Input Test Waveforms
and Measurement Levels
tR, tF < 5 ns (10% to 90%)
For -45 devices only:
tR, tF < 20 ns (10% to 90%)
For -70 and -90 devices:
6AT27C010
0321K–EPROM–4/2004
Output Test Load
Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Note: CL = 100 pF including jig
capacitance, except for
the -45 devices, where
CL=30pF.
Pin Capacitance
f = 1 MHz, T = 25°C(Note:)
Symbol Typ Max Units Conditions
CIN 48pFV
IN = 0V
COUT 812pFV
OUT = 0V
7
AT27C010
0321K–EPROM–4/2004
Programming
Waveforms(1)
Note: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the
programmer.
3. When programming the AT27C010 at 0.1 µF capacitor is required across VPP and
ground to suppress spurious voltage transients.
DC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Symbol Parameter Test Conditions
Limits
UnitsMin Max
ILI Input Load Current VIN = VIL, VIH ±10 µA
VIL Input Low Level -0.6 0.8 V
VIH Input High Level 2.0 VCC + 1 V
VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Output High Voltage IOH = -400 µA2.4 V
8AT27C010
0321K–EPROM–4/2004
Note: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP
..
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven—
see timing diagram.
3. Program Pulse width tolerance is 100 µsec ± 5%.
ICC2 VCC Supply Current (Program and Verify) 40 mA
IPP2 VPP Supply Current CE = PGM = VIL 20 mA
VID A9 Product Identification Voltage 11.5 12.5 V
DC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Symbol Parameter Test Conditions
Limits
UnitsMin Max
AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25 V, VPP = 13.0 ± 0.25V
Symbol Parameter Test Conditions(1)
Limits
UnitsMin Max
tAS Address Setup Time
Input Rise and Fall Times
(10% to 90%) 20ns
Input Pulse Levels
0.45V to 2.4V
Input Timing Reference Level
0.8V to 2.0V
Output Timing Reference Level
0.8V to 2.0V
2µs
tCES CE Setup Time 2 µs
tOES OE Setup Time 2 µs
tDS Data Setup Time 2 µs
tAH Address Hold Time 0 µs
tDH Data Hold Time 2 µs
tDFP OE High to Output Float Delay (2) 0 130 ns
tVPS VPP Setup Time 2 µs
tVCS VCC Setup Time 2 µs
tPW PGM Program Pulse Width(3) 95 105 µs
tOE Data Valid from OE 150 ns
tPRT
VPP Pulse Rise TIme
During Programming 50 ns
Atmel’s 27C010 Integrated Product Identification Code
Codes
Pins Hex
DataA0 O7 O6 O5 O4 O3 O2 O1 O0
Manufacturer 000011110 1E
Device Type 100000101 05
9
AT27C010
0321K–EPROM–4/2004
Rapid Programming
Algorithm
A 100 µs PGM pulse width is used to program. The address is set to the first location.
VCC is raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with
one 100 µs PGM pulse without verification. Then a verification / reprogramming loop is
executed for each address. In the event a byte fails to pass verification, up to 10 succes-
sive 100 µs pulses are applied with a verification after each pulse. If the byte fails to
verify after 10 pulses have been applied, the part is considered failed. After the byte ver-
ifies properly, the next address is selected until all have been checked. V
PP is then
lowered to 5.0V and VCC to 5.0V. All bytes are read again and compared with the origi-
nal data to determine if the device passes or fails.
10 AT27C010
0321K–EPROM–4/2004
AT27C010 Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
45 25 0.1 AT27C010-45JC
AT27C010-45PC
AT27C010-45TC
32J
32P6
32T
Commercial
(0°C to 70°C)
25 0.1 AT27C010-45JI
AT27C010-45PI
AT27C010-45TI
32J
32P6
32T
Industrial
(-40°C to 85°C)
70 25 0.1 AT27C010-70JC
AT27C010-70PC
AT27C010-70TC
32J
32P6
32T
Commercial
(0°C to 70°C)
25 0.1 AT27C010-70JI
AT27C010-70PI
AT27C010-70TI
32J
32P6
32T
Industrial
(-40°C to 85°C)
90 25 0.1 AT27C010-90JC
AT27C010-90PC
AT27C010-90TC
32J
32P6
32T
Commercial
(0°C to 70°C)
25 0.1 AT27C010-90JI
AT27C010-90PI
AT27C010-90TI
32J
32P6
32T
Industrial
(-40°C to 85°C)
25 0.1 AT27C010-90JA
AT27C010-90PA
32J
32P6
Automotive
(-40°C to 125°C)
Package Type
32J 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
32P6 32-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T 32-Lead, Plastic Thin Small Outline Package (TSOP)
11
AT27C010
0321K–EPROM–4/2004
Package Information
32J – PLCC
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B
32J
10/04/01
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 E2
B
e
E1 E
D1
D
D2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 3.175 3.556
A1 1.524 2.413
A2 0.381
D 12.319 12.573
D1 11.354 11.506 Note 2
D2 9.906 10.922
E 14.859 15.113
E1 13.894 14.046 Note 2
E2 12.471 13.487
B 0.660 0.813
B1 0.330 0.533
e 1.270 TYP
12 AT27C010
0321K–EPROM–4/2004
32P6PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP) B
32P6
09/28/01
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 4.826
A1 0.381
D 41.783 42.291 Note 1
E 15.240 15.875
E1 13.462 13.970 Note 1
B 0.356 0.559
B1 1.041 1.651
L 3.048 3.556
C 0.203 0.381
eB 15.494 17.526
e 2.540 TYP
Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
13
AT27C010
0321K–EPROM–4/2004
32T – TSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP) B
32T
10/18/01
PIN 1
D1 D
Pin 1 Identifier
b
e
EA
A1
A2
0º ~ 8º c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A 1.20
A1 0.05 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 0.21
e 0.50 BASIC
Printed on recycled paper.
0321K–EPROM–4/2004
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