f u l l y t e s t e d a n d i n t e r o p e r a b l e Lattice Ethernet Solutions Ready-to-Use Ethernet Portfolio Lattice provides customers with low cost and low power programmable solutions that are ready-to-use right out of the box. A full suite of tested and interoperable solutions is available for Ethernet applications, including: FPGAs with Embedded Ethernet-compliant SERDES A Complete Portfolio of Soft and Hard IP Cores for 10GbE, 2.5GbE, 1GbE, and 10/100 Ethernet Stacks Application Specific Development Boards, Systems and Reference Designs Test and Interoperability Reports for PMA, PCS and MACs Silicon: Industry Leading Programmable Ethernet Platforms LatticeECP3TM Low Cost FPGA SERDES SERDES SERDES SERDES LatticeSCTM Extreme Performance FPGA Embedded 3.2Gbps SERDES support PCI Express, Ethernet (XAUI, 1GbE, SGMII), CPRI, OBSAI & 3G/HD/SD-SDI. SERDES SERDES SERDES Programmable Function Unit (PFU) perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. Programmable Function Unit (PFU) perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. Pre-Engineered Source Synchronous Support implements DDR3 at 800Mbps, SPI4.2 at 750Mbps and generic interfaces up to 1Gbps. Programmable I/O Cells (PICs) include PURESPEEDTM buffers that support over 20 I/O standards. sysDSPTM Blocks implement multipliers, adders, subtractors, accumulators. Structured ASIC Block (MACOTM) provides 50,000 usable gates for increased performance, density and lower power. sysMEM Embedded Block RAM (EBR) provides 18kbit dual port RAM. sysMEMTM Embedded Block RAM (EBR) provides 18kbit dual port RAM. sysCLOCK PLLs & DLLs for clock management. LatticeECP3 Features SERDES Quad SERDES + Embedded PCS - each channel runs from 600Mbps to 3.8Gbps with 105mW power dissipation. Low Cost Digital SERDES * Ideal for low cost chip-to-chip and small factor backplane applications * Exceeds XAUI Tx and Rx requirements * 1000BaseX Jitter Compliant Up to 16 Channels per Device * Useful for multi-port switching Complete End-to-End Solution * Soft XAUI PCS and 10GbE MAC implementations available * Soft SGMII and TS-MAC implementations available Very Low SERDES Power (~110mW Per Channel Typical @ 3.2Gbps) Low Cost FPGA Fabric * High end features at low cost sysCLOCKTM PLLs & DLLs for clock management. LatticeSC Features High Performance Analog SERDES * Exceeds XAUI TX and RX requirements * Ideal for long Ethernet-based backplanes Up to 32 Channels per Device * Useful for multi-port switching Data Rates Up to 3.8 Gbps * Exceeds XAUI baud rate specifications Complete End-to-End Solution * Rich PCS functionality * flexiMACTM supports both GbE and 10GbE MACs, saves cost and power * Soft SGMII and TS-MAC implementation available Very Low SERDES Power (105mW Per Channel Typical @ 3.125Gbps) Extreme Performance FPGA Fabric * 500MHz block level performance Media Access Controllers Physical Coding Sub-Layer Intellectual Property: Rich Portfolio of Hard & Soft IP XAUI PCS GbE & SGMII PCS flexiPCSTM Platform: Soft IP Compliant to IEEE802.3ae for XAUI Implements TX and RX State Machines XGMII Interface to FGPA Fabric Platform: Soft IP Compliant to IEEE802.3z MAC or PHY Modes (Pin Selectable) RX and TX State Machines and Autonegotiation Rate Adaptation for 10/100 MII Frames 8-bit GMII MAC Interface Platform: Hard PCS Block Supports IEEE802.3ae XAUI and IEEE GbE PCS M u l t i p ro t o c o l GMII (GbE) and XGMII Interfaces to FPGA Fabric Tri-Speed MAC 10GbE MAC flexiMAC Platform: Soft IP 10/100/1000 Mbps Operation Compliant to IEEE 802.3z Generic FIFO Interface Programmable IPG TX and RX Statistics Vectors Multicast Address Filtering MII/GMII Interface Management Interface FCS on TX and RX Supports: Platform: Soft IP Compliant to IEEE802.3ae-2002 Optional HiGig/+ Capability for Broadcom StrataXGS I/II Switches (LatticeSC only) XAUI or XGMII Interface System Aide FIFO Interface Programmable IPG TX and RX Statistics Vectors Multicast Address Filtering MDIO Interface Supports: Platform: Implemented on MACO Structured ASIC Technology Multiprotocol Engine Can be Configured as a 10G or 1G MAC Saves Up to 5K LUTs in FPGA Real Estate Low Power Implementation (100mW max) No IP Licensing Fees * * * * * * * * * * * Full Duplex control with PAUSE frames VLAN tagged frames Automatic padding of short frames Automatic re-transmission on collision Broadcast and multicast frames Jumbo packets (up to 8192 bytes) Full duplex control with PAUSE frames VLAN tagged frames Automatic padding of short frames FCS on TX and RX Jumbo packets Tri-Speed MAC Block Diagram G/MII Receive and Transmit MAC flexiPCS Platform: Soft IP Bundle 10/100/1000 Mbps Operation Compliant to IEEE 802.3z Generic FIFO interface Programmable IPG TX and RX Statistics Vectors Multicast Address Filtering MII/GMII Interface Management Interface FCS on TX and RX Supports: System Interfaces Management Interface Soft SPI4.2 Platform: Industry Best Performance MACO SPI4.2 Block Diagram LatticeSCMTM Device SPI4.2 MACO IP Core ASIC Gates PHY Layer Device FPGA Array S4TX Data Path Status Path S4RX Data Path Status Path Control Regs User Logic Link Layer Function or SPI4 Loop SMI SYSBUS * High performance FPGAs: LatticeSC/M at 1Gbps with dynamic alignment * Industry best perfromance for low-cost FPGAs: LatticeECP3, ECP2/M (750Mbps with static alignment) Support for 256 Logic Channels Highly Configurable * Selectable 64/128b bus width * Run-time user controls for TX idles, packing and training patterns * Programmable internal FIFO thresholds * Variable minimum burst sizes * Variable packet sizes * Selectable status reporting (RAM or Transparent) TM 2.5GbE MAC * * * * * * Platform: Implemented on MACO Structured ASIC Technology Very Low Power (0.85W) Saves 4K LUTs in FPGA LUTs Maximum 1Gbps Bandwidth No IP Licensing Fee PCS flexiMAC Host Interface MACO SPI4.2 TM Full Duplex control with PAUSE frame VLAN tagged frames Automatic padding of short frames Automatic re-transmission on collision Broadcast and multicast frames Jumbo packets XAUI to SPI4.2 Fabric Interface Platform: Hard and Soft IP Bundle Bundle Includes: * No-charge Bridge Reference design with source code * SPI4.2 MACO (No IP licensing fee) * 10GbE MAC IP Optional HiGig+(R) Capability for Broadcom(R) StrataXGS(R) I/II Switches Single Instance Fits into LatticeSC15 Device * 17x17 256fpBGA - industry's smallest footprint (by 40%) * Lowest power SERDES at 3.125Gbps (105mW) * Lowest power SPI4.2 implementation (0.85W) Maximum Bandwidth of 12.5Gbps Tested with Broadcom StrataXGS Switches Lattice Developed and Supported Development & Evaluation Systems Lattice Ethernet Evaluation Platforms Board Name LatticeECP3 Evaluation Platforms LatticeECP2MTM Evaluation Platforms LatticeSC Evaluation Platforms Ethernet Interfaces Other Interfaces Memory Interfaces Serial Protocol Board * SMAs for SERDES (4 channels) * RJ-45 * PCIe x4 Edge Finger * SMAs for LVDS I/O * DDR3 Component (8 bit) * DDR2 Component (18 bit) I/O Protocol Board * SMAs for SERDES (4 channels) * RJ-45 * SPI4.2 Connector * SMAs for LVDS I/O * DDR3 Memory Dual DIMM (64 bit) * DDR2 Component (18 bit) PCI Express x4 * SMAs for SERDES (3 channels) * Breakout Card for RJ-45 * PCIe x4 Edge Finger * SMAs for LVDS I/O * BNC for SMPTE * DDR2 Component (18 bit) SERDES Evaluation * SMAs for SERDES (4 channels) * RJ-45 * SFP Optical Cage (SGMII) * PCIe x1 Edge Finger * DDR2 Component (18 bit) Communications LFSC25-900 * SMAs for SERDES (8 channels) * SFI for MSA300 * Breakout Card for RJ-45 * SPI4.2 * SMAs for LVDS I/O * DDR2 SODIMM (64 bit) PCI Express x4 LFSC80-1152 * SMAs for SERDES (4 channels) * Breakout Card for RJ-45 * PCIe x4 Edge Finger * SMAs for LVDS I/O * DDR2 Component (18 bit) PCI Express x1 LFSC25-900 * SFP Optical Cage (SGMII) * RJ-45 * PCIe x1 Edge Finger * SMAs for LVDS I/O * SATA * RLDRAM and QDR2 (18 bit) LatticeECP3 Serial Protocol Board LatticeECP2M PCI Express x4 Evaluation Board LatticeSC PCI Express x1 Evaluation Board LatticeECP2M SERDES Evaluation Board LatticeSC Communications Evaluation Board LatticeECP3 I/O Protocol Board LatticeSC PCI Express x4 Evaluation Board Lattice Tri-Speed Ethernet MAC Development System The LatticeMico32 Tri-Speed Ethernet Media Access Controller (TSMAC) demo shows the capability of the TSMAC IP core to function in a real network environment. * Uses Lattice open source LatticeMico32 soft RISC processor * Web server application * Includes MAC device drivers and open source lightweight IP (lwIP) stack LatticeMico32 Tri-Speed MAC Demo Board Lattice FPGA Tri-Speed MAC Tri-Speed MAC Device Driver (Soft IP Core) TX FIFO Intel PHY RX FIFO LatticeMico32TM (Soft P) Lightweight IP TCP/IP Network Stack Web Server Tri-Speed MAC Demo Page Tri-Speed MAC Core Page RJ-45 The LatticeMico32 Tri-Speed Ethernet Media Access Controller (TSMAC) demo requires no test equipment, lengthy setup or complex explanation. The demo uses a Web server to demonstrate the Tri-Speed MAC IP core, using the open-source lightweight IP (lwIP) network stack. Web Browser Demonstration PC Testing and Usability Hardware Testing Lattice IPexpressTM Tool Lattice tests all critical components of the Ethernet stack rigorously, and puts a great deal of emphasis on interoperability with proven 3rd party silicon platforms. The following test documentation is available for customer review. The IPexpress tool revolutionizes the way users design with Lattice IP cores and greatly simplifies IP design. The IPexpress design flow enables users to fully parameterize IP in real-time. The designer can then instantiate the user-configured IP and complete the design process, including full timing simulation and bitstream generation. PMA Electrical Characterization See Lattice technical note TN1084 and supplements (available under NDA) for ANSI11.2 and IEEE802.3-2002 Electrical Tests for LatticeECP3, LatticeECP2M and LatticeSC SERDES. Interoperability The following test and interoperability documentation is available for customer review: Lattice Device Marvell Alaska Family Ethernet Protocol 88E1111/881112 1GbE PMA/PCS LatticeECP3 SGMII PMA/PCS Broadcom StrataXGS 1GbE PMA/PCS SGMII PMA/PCS 2.5GbE PMA/PCS XAUI PMA/PCS LatticeSC HiGig+ PMA/PCS PMC Sierra PM3388 View IP Cores Available for Download From the Lattice IP Server Tab within IPexpress, you can view available ispLeverCORETM user-configurable IP cores for download. Install or Download IP Cores You can download and install ispLeverCORE user-configurable IP cores on your computer, or you can simply download them and install them later. 1GbE flexiMAC 2.5GbE Soft MAC 10GbE flexiMAC HiGig+ MAC SPI4.2 Lattice's IPexpress tool can be used to easily configure both MACO hard IP and Lattice's growing selection of soft IP cores. Lattice Ethernet Portfolio Guide LatticeECP3 PMA Serial PCS MACs SPI4.2 Reference Designs Development Platforms * XAUI * GbE (1000BaseX) * XGMII * GMII/RGMII * MII/RMII LatticeECP2TM * XGMII * GMII/RGMII * MII/RMII LatticeXP2TM * GMII/RGMII * MII/RMII * Soft XAUI * Soft GbE * Soft SGMII * Soft 10GbE MAC * Soft Tri-Speed MAC (10/100/1000) * Hard flexiMAC (1GbE & 10GbE) * Soft Tri-Speed MAC (10/100/1000) * Soft 2.5GbE MAC * Soft 10GbE MAC * Soft HiGig+ MAC * Hard SPI4.2 on MACO & Soft SPI4.2 * Soft SPI4.2 * RGMII to GMII Bridge * Boards with SMA Connectors, SGMII Cage & RJ-45 Connectors * Interoperability Platforms * Processor based Demo with TCP/IP Stack * Reference Drivers LatticeSC * XAUI * HiGig+ * GbE (1000BaseX) * XGMII * GMII/RGMII * MII/RMII * Hard flexiPCS (GbE, 2.5GbE & XAUI) * Soft SGMII * Boards with RJ-45 Connectors * Processor based Demonstration with TCP/IP Stack * Reference Drivers * XAUI to SPI4.2 Bridge * HiGig+ to SPI4.2 Bridge * RGMII to GMII Bridge * Boards with SMA Connectors, SGMII Cage & RJ-45 Connectors * Interoperability Platforms * Processor based Demo with TCP/IP Stack * Reference Drivers Applications Support 1-800-LATTICE (528-8423) (503) 268-8001 techsupport@latticesemi.com www.latticesemi.com Copyright (c) 2009 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), flexiMAC, flexiPCS, IPexpress, ispLeverCORE, LatticeECP3, LatticeECP2, LatticeECP2M, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP2, MACO, sysCLOCK, sysDSP, and sysMEM are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. December 2009 Order #: I0194B Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Lattice: 2PT5-MAC-SC-U1