DAC161P997 DAC161P997 Single-Wire 16-bit DAC for 4-20mA Loops Literature Number: SNAS515C DAC161P997 Single-Wire 16-bit DAC for 4-20mA Loops 1.0 General Description 2.0 Applications The DAC161P997 is a 16- bit digital-to-analog converter (DAC) for transmitting an analog output current over an industry standard 4-20 mA current loop. It offers 16-bit accuracy with a low output current temperature coefficient (29ppm/C) and excellent long-term output current drift (90 ppmFS) while consuming less than 190A. The data link to the DAC161P997 is a Single Wire Interface (SWIF) which allows sensor data to be transferred in digital format over an isolation boundary using a single isolation component. The DAC161P997's digital input is compatible with standard isolation transformers and optocouplers. Error detection and handshaking features within the SWIF protocol ensure error free communication across the isolation boundary. For applications where isolation is not required, the DAC161P997 interfaces directly to a microcontroller. The loop drive of the DAC161P997 interfaces to a HART (Highway Addressable Remote Transducer) modulator, allowing injection of FSK modulated digital data into the 4-20mA current loop. This combination of specifications and features makes the DAC161P997 ideal for 2- and 4-wire industrial transmitters. The DAC161P997 is available in a 16-lead LLP package and is specified over the extended industrial temperature range of -40C to 105C. * * * * * * * * Two-wire, 4-20 mA current loop transmitter Industrial Process Control Actuator control Factory Automation Building Automation Precision Instruments Data Acquisition Systems Test Systems 3.0 Features 16-bit linearity Single-Wire Interface (SWIF), with handshake Digital Data transmission (no loss of fidelity) Pin Programmable Power-Up Condition Self adjusting to input data rate Loop error detection and reporting Programmable output current error level No external precision components Simple interface to HART modulator Small package: LLP-16 (4x4 mm, 0.5 mm pitch) 4.0 Key Specifications Output Current TempCo Long-Term Output Current Drift INL Total Supply Current 29 ppmFS/C(max) 90 ppmFS(typ) +3.3/-2.1 A(max) 190 A(max) 5.0 Typical Application - Conceptual Schematic 30154401 National Semiconductor(R) is a registered trademark of National Semiconductor Corporation. (c) 2011 National Semiconductor Corporation 301544 www.national.com DAC161P997 Single-Wire 16-bit DAC for 4-20mA Loops August 2, 2011 DAC161P997 6.0 Block Diagram 30154402 www.national.com 2 7.1 4-20 mA CURRENT LOOP TRANSMITTER The DAC161P997 is a 16-bit DAC realized as a modulator. The DAC's output is a current pulse train that is filtered by the on-board low pass RC filter. The final output current is a multiplied copy of the filtered modulator output. This architecture guarantees an excellent linearity performance, while minimizing power consumption of the device. The DAC161P997 eases the design of robust, precise, longterm stable industrial systems by integrating all precision elements on-chip. Only a few external components are needed to realize a low-power, high-precision industrial 4 - 20 mA transmitter. In case of a fault, or during initial power-up the DAC161P997 will output current in either upper or lower error current band. The choice of band is user selectable via a device pin. The error current value is user programmable via the SWIF link by the Master. 7.2 SINGLE-WIRE INTERFACE (SWIF) SWIF is a versatile and robust solution for transmitting digital data over the galvanic isolation boundary using just one isolation element: a pulse transformer. Digital data format achieves the information transmission without the loss of fidelity which usually afflicts transmissions employing PWM (Pulse Width Modulation) schemes. Digital transmission format also makes possible data differentiation: user can specify whether given data word is a DAC input to be converted to loop current, or it is a device configuration word. 8.0 Connection Diagram 30154403 LLP-16 (SQ16A) Top View 3 www.national.com DAC161P997 SWIF was designed to use in conjunction with pulse transformer as an isolation element. The use of the transformers to cross the isolation boundary is typical in the legacy systems due to their robustness, low-power consumption, and low cost. However, system implementation is not limited to the transformer as a link since SWIF easily interfaces with optocouplers, or it can be directly driven by a CMOS gate. SWIF incorporates a number of features that address robustness aspect of the data link design: 1. Bidirectional signal flow: the DAC161P997 can issue an ACKNOWLEDGE pulse back to the master transmitter, via the same physical channel, to confirm the reception of the valid data; 2. Error Detection: SWIF protocol incorporates frame length detection and parity checks as a method of verifying the integrity of the received data; 3. Channel Activity Detection: SWIF can monitor the data channel and raise an error flag should the expected activity drop below programmable threshold, due to , for example, damage to the physical channel. In the typical system the Master is a micro controller. SWIF has been implemented on a number of popular micro controllers where it places minimum demands on the hardware or software resources even of the simple 8-bit devices. SWIF gives the system designer flexibility is balancing the trade-offs between the data rate, activity monitoring functionality and the power consumption in the transformer coupled data channel. At lowest data rates, with long inactive interframe periods, the power consumed by SWIF is negligible. See Section 17.2.2 Inter-Frame Period 7.0 Functional Overview DAC161P997 9.0 Pin Descriptions Name Pin Function VA 15 Analog block positive supply rail COMA 1 Analog block negative supply rail (local COMMMON) COMD 2 Digital block negative supply rail (local COMMON) VD 3 Digital block positive supply rail DIN 4 SWIF input DBACK 5 SWIF input loop back ACKB 6 SWIF acknowledge output - open drain, active LOW ERRLVL 8 Sets the output current level at power-up LOW 10 Must be tied to COMA, COMD potential C1 14 External capacitor C2 13 External capacitor, HART Input C3 12 External capacitor BASE 16 External NPN base drive N.C. 11 User must not connect to this pin ERRB 7 Error flag output open drain, active LOW OUT 9 Loop output current source - Die Attach Pad. For best thermal conductivity and best noise immunity DAP should be soldered to the PCB pad which is connected directly to circuit common node (COMA, COMD) DAP ESD Protection - 10.0 Ordering Information Order Number DAC161P997CISQ DAC161P997CISQX www.national.com NS Package Number Transport Media Tape-and reel: 1000 pieces SQ16A Tape-and reel: 2500 pieces 4 1.0 General Description ......................................................................................................................... 1 2.0 Applications .................................................................................................................................... 1 3.0 Features ........................................................................................................................................ 1 4.0 Key Specifications ........................................................................................................................... 1 5.0 Typical Application - Conceptual Schematic ........................................................................................ 1 6.0 Block Diagram ................................................................................................................................ 2 7.0 Functional Overview ........................................................................................................................ 3 7.1 4-20 mA CURRENT LOOP TRANSMITTER ................................................................................ 3 7.2 SINGLE-WIRE INTERFACE (SWIF) ........................................................................................... 3 8.0 Connection Diagram ........................................................................................................................ 3 9.0 Pin Descriptions .............................................................................................................................. 4 10.0 Ordering Information ...................................................................................................................... 4 11.0 Absolute Maximum Ratings ............................................................................................................. 6 12.0 Operating Conditions (Note 1, Note 2) ............................................................................................... 6 13.0 Electrical Characteristics ................................................................................................................ 6 14.0 Single-Wire Interface (SWIF) Timing Diagram .................................................................................... 8 15.0 Typical Performance Characteristics ................................................................................................ 9 16.0 Register Set ................................................................................................................................ 11 16.1 LCK: Address=0x00; Default=0x00 ......................................................................................... 11 16.2 CONFIG1: Address=0x01; Default=0x08 ................................................................................. 11 16.3 CONFIG2: Address=0x02; Default=0x1F ................................................................................ 11 16.4 CONFIG3: Address=0x03; Default=0x08 ................................................................................. 11 16.5 ERR_LOW: Address=0x04; Default=0x24 ............................................................................... 12 16.6 ERR_HIGH: Address=0x05; Default=0xE8 ............................................................................... 12 17.0 Application Information ................................................................................................................. 13 17.1 16-BIT DAC AND LOOP DRIVE ............................................................................................. 13 17.1.1 DC Characteristics ...................................................................................................... 13 17.1.1.1 DC Input-Output Transfer Function ...................................................................... 14 17.1.1.2 Loop Interface .................................................................................................. 14 17.1.1.3 Loop Compliance .............................................................................................. 14 17.1.2 AC Characteristics ...................................................................................................... 15 17.1.2.1 Step Response ................................................................................................. 16 17.1.2.2 Output impedance ............................................................................................ 16 17.1.2.3 PSRR ............................................................................................................. 16 17.1.2.4 Stability ........................................................................................................... 16 17.1.2.5 Noise and Ripple .............................................................................................. 17 17.1.2.6 Digital Feedthrough ........................................................................................... 17 17.1.2.7 HART Signal Injection ....................................................................................... 17 17.1.2.8 RC Filter Limitation ........................................................................................... 17 17.1.3 Alarm Current ............................................................................................................ 17 17.2 SINGLE-WIRE INTERFACE (SWIF) ....................................................................................... 17 17.2.1 Frame Format ............................................................................................................ 18 17.2.2 Inter-Frame Period ...................................................................................................... 18 17.2.3 Symbol Set ................................................................................................................ 18 17.2.4 Interface Circuit .......................................................................................................... 20 17.2.4.1 Transformer Coupled Interface - Data Flow to the DAC .......................................... 20 17.2.4.2 Transformer Coupled Interface - Acknowledge Pulse ............................................. 21 17.2.4.3 DC-Coupled Interface ........................................................................................ 21 17.2.4.4 SWIF Implementation Examples ......................................................................... 22 17.2.4.5 Transformer Selection and SWIF Data Link Circuit Design ..................................... 25 17.3 ERROR DETECTION AND REPORTING ................................................................................ 28 18.0 Application Circuit Examples ......................................................................................................... 29 19.0 Physical Dimensions .................................................................................................................... 30 5 www.national.com DAC161P997 Table of Contents DAC161P997 11.0 Absolute Maximum Ratings (Note 12.0 Operating Conditions 1, Note 2) 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Temperature (TA) Supply Voltage Range (VA - VD) (COMA - COMD) BASE load to COMA OUT load to COMA Supply relative to common (VA, VD to COMA, COMD) Voltage between any 2 pins(Note 3) Current IN or OUT of any pin - except OUT (Note 3) Output current at OUT Junction Temperature Storage Temperature Range ESD Susceptibility (Note 4) Human Body Model Machine Model Charged Device Model -0.3V to 6.0V 6.0V 5 mA 50 mA +150C -65C to +150C (Note 1, Note -40C to 105C 2.7V to 3.6V 0V 0V 0 to 15 pF none Package JA LLP16 35C/W For Soldering specifications: See product folder at www.national.com www.national.com/ms/MS-SOLDERING.pdf. 5500V 500V 1250V and 13.0 Electrical Characteristics Unless otherwise noted, these specifications apply for VA = VD = 2.7V to 3.6V, TA=25C, external bipolar transitor: 2N3904, RE=22, C1=C2=C3=2.2nF. Boldface limits are over the temperature range of -40C TA 105C unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units POWER SUPPLY VA, VD Supply Voltage VA = VD 2.7 VA Supply Current VD Supply Current DACCODE=0x0200 (Note 5) Total Supply Current VPOR Power On Reset supply rail potential threshold 1.3 3.6 V 75 A 115 A 190 A 1.9 V DC ACCURACY N Resolution INL Integral Non-Linearity DNL Differential Non-Linearity TUE Total Unadjusted Error OE Offset Error 16 0x2AAA<DACCODE<0xD555 (4mA<ILOOP<20 mA) -2.1 +3.3 (Note 10) -0.2 +0.2 0x2AAA<DACCODE<0xD555 -0.23 +0.23 (Note 6) -9.16 +9.16 A 138 nA/C Offset Error Temp. Coefficient GE Gain Error Bits (Note 7) -0.22 Gain Error Temp. Coefficient 5 %FS 29 ppmFS/C DACCODE = 0x2AAA -18 20 mA Loop Current Error DACCODE = 0xD555 -55 IERRL LOW ERROR Current ERR_LOW = default 3361 3375 3391 IERRH HIGH ERROR Current ERR_HIGH = default 21702 21750 21817 LTD %FS 0.22 4mA Loop Current Error Long Term Drift -- mean shift of 12 mA output current after 1000 hrs at 150C A +18 +55 90 A ppmFS LOOP CURRENT OUTPUT (OUT) Output Current Minimum tested at DACCODE = 0x01C2 (Note 8) Output Impedance COMA to OUT voltage drop 0.18 24 100 IOUT = 24 mA mA M 960 mV 10 mA BASE OUTPUT BASE short circuit output current www.national.com BASE forced to COMA potential 6 Parameter Conditions Min Typ Max Units DYNAMIC CHARACTERISTICS 1kHz 20 nA/Hz 1Hz to 1kHz band 300 nARMS Output Noise Density Integrated Output Noise SWIF I/O CHARACTERISTICS VIH DIN VIL DIN CDIN DIN input capacitance VOH DBACK VOL DBACK TD 0.7*VD 0.3*VD 10 I = 3mA 2216 I = 5mA 1783 pF I = 3mA 547 I = 5mA 1260 DIN to DBACK delay V 8 mV ns OPEN DRAIN OUTPUTS VOL ACKB VOL ERRB I = 3mA 550 I = 5mA 1370 I = 300 A 66 I = 3mA 602 ACKB Leakage current when output device is off 1 ERRB Leakage current when output device is off 1 IOZ mV mV A SWIF TIMING Symbol rate: 1/TP 0.3 "D" symbol duty cycle: THD/TP 7/16 1/2 9/16 "0" symbol duty cycle: TH0/TP 3/16 1/4 5/16 "1" symbol duty cycle: TH1/TP 11/16 3/4 13/16 ACKB assert: TA/TP 1/16 1/4 4/8 ACKB deassert: TB/TP 12/8 7/4 31/16 90 100 110 19.2 kHz Internal Timer TM Timeout Period ms Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: All voltages are measured with respect to COMA = COMD = 0V, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds power supplies (VIN < COMA or VIN > VA), the current at that pin must not exceed 5 mA, and the voltage (VIN) at that pin relative to any other pin must not exceed 6.0V. See Section 9.0 Pin Descriptions for additional details of input structures. Note 4: The Human Body Model (HBM) is a 100 pF capacitor charged to the specified voltage then discharged through a 1.5 k resistor into each pin. The Machine Model (MM) is a 200 pF capacitor charged to specified voltage then discharged directly into each pin. The Charged Device Model (CDM) is a specified circuit characterizing an ESD event that occurs when a device acquires charge through some triboelectric (frictional) or electrostatic induction process and then abruptly touches a grounded object or surface. Note 5: At code 0x0200 the BASE current is minimal, i.e., device current contribution to power consumption is minimized. The SWIF link is inactive, i.e., after transmitting code 0x200 to the DAC161P997, there are no more transitions in the channel during the supply current measurement. Note 6: Here offset is the y-intercept of the straight line defined by 4 mA and 20 mA points of the measured transfer characteristic. Note 7: Here Gain Error is the difference in slope of the straight line defined by measured 4 mA and 20 mA points of transfer characteristic, and that of the ideal characteristic. Note 8: This should be treated as the minimum LOOP current guarantee. Note 9: INL is measured using "best fit" method in the output current range of 4 mA to 20 mA. Note 10: Guaranteed by design. 7 www.national.com DAC161P997 Symbol DAC161P997 14.0 Single-Wire Interface (SWIF) Timing Diagram See section Section 17.2.3 Symbol Set for SWIF waveform description 30154410 www.national.com 8 Unless otherwise noted, data presented here was collected under these conditions VA = VD = 3.3V, TA=25C, external bipolar transistor: 2N3904, RE=22, C1=C2=C3=2.2 nF. Supply Current vs Supply Voltage Gain Error TC distribution Data Rate = 300Baud Data Rate = 19200Baud 190 FREQUENCY OF OCCURRENCE (%) TOTAL SUPPLY CURRENT (A) 200 180 170 160 150 140 130 120 110 100 25 20 15 Tail of the distribution follows Gaussian PDF with: =2.0, =4.8 10 5 0 0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 2 4 6 8 10 12 14 16 18 20 GE TEMPERATURE COEFFICIENT (ppm/C) 30154435 30154436 Linearity vs ILOOP 2.5 Integration BW=1kHz Integration BW=10kHz 2.0 5 1.5 4 INL (A) OUTPUT CURRENT RIPPLE A(rms) Integrated Noise vs ILOOP 6 3 2 1.0 0.5 0.0 -0.5 1 -1.0 0 -1.5 0 4 8 12 16 20 OUTPUT CURRENT (mA) 24 4 6 8 10 12 14 16 18 OUTPUT CURRENT (mA) 30154434 30154437 Modulator Filter Response 0 30 -10 MAGNITUDE RESPONSE (dB) FREQUENCY OF OCCURRENCE (%) Offset Error TC Distribution 35 25 20 Tail of the distribution follows Gaussian PDF with: =3nA, =24nA/C 15 10 5 0 0 20 40 60 80 20 -20 -30 -40 -50 C1=C2=C3=2.2nF HART Adaptation C1=C2=C3=1nF -60 -70 -80 100 1 OE TEMPERATURE COEFFICIENT (nA/C) 30154438 10 100 1k 10k FREQUENCY (Hz) 100k 30154442 9 www.national.com DAC161P997 15.0 Typical Performance Characteristics Supply Current vs ILOOP TOTAL SUPLLY CURRENT (A) 300 SETTLING TIME (s) 100k 10k 1k 100 10 C1=C2=C3=2.2nF HART Adaptation C1=C2=C3=1nF 1 1 10 100 1k 10k INPUT CODE STEP (lsb) 250 200 150 VA=VD=2.7V VA=VD=3.0V VA=VD=3.3V VA=VD=3.6V 100 50 0 100k 0 4 8 12 16 20 OUTPUT CURRENT (mA) 30154444 PSRR: ILOOP=4mA 2.5 120 2.0 PSRR (dB) INL (A) Min INL Max INL 0.5 0.0 -0.5 -1.0 -1.5 80 60 40 20 -2.0 -2.5 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 1 30154469 120 C1=C2=C3=1nF C1=C2=C3=2.2nF C1=C2=C3=10nF C1=C2=C3=100nF 100 80 60 40 20 0 1 10 100 1k 10k 100k FREQUENCY (Hz) 10 100 1k 10k 100k FREQUENCY (Hz) 1M 30154471 PSRR: ILOOP=20mA 1M 30154470 www.national.com C1=C2=C3=1nF C1=C2=C3=2.2nF C1=C2=C3=10nF C1=C2=C3=100nF 100 1.5 1.0 24 30154468 Output Linearity vs Temperature PSRR (dB) DAC161P997 Settling Time vs Input Step Size 1M 10 DAC161P997 16.0 Register Set 16.1 LCK: Address=0x00; Default=0x00 Bit Field Name Description 0x95 - registers unlocked 0x** - any value written locks registers A register lock prevents inadvertent changes to the configuration. The DAC output cannot be updated while software configuration registers are unlocked. 7:0 16.2 CONFIG1: Address=0x01; Default=0x08 Bit Field Name Description 7:5 RESERVED. Always write 0. 4:3 0b00 - NOP 0b01 - set error 0b10 - clear error 0b11 - NOP Sets or clears the error condition. At power-on the error is set. Error is also cleared after reception of valid SWIF frame. These bits are self clearing. This functionality can be used for diagnostic purposes, e.g. Master can use SERR to force ILOOP into an error band, and then return it to previously held output level. SERR 2:1 0 RESERVED. Always write 0. RST 0 - NOP 1- same as power-on reset. Once device is reset to default state the bit clears automatically 16.3 CONFIG2: Address=0x02; Default=0x1F Bit Field Name 7:5 Description RESERVED. Always write 0. 4 ACK_EN Set to enable ACK When enabled, an acknowledgement is indicated on the serial interface upon detection of each valid frame. See Section 17.2.1 Frame Format 3 FRAME Set to enable framing error reporting. See table in Section 17.3 ERROR DETECTION AND REPORTING 2 PARITY Set to enable parity error reporting. See table in Section 17.3 ERROR DETECTION AND REPORTING 1 CHANNEL 0 LOOP Set to enable channel-inactive reporting. See table in Section 17.3 ERROR DETECTION AND REPORTING Set to enable loop error reporting. See table in Section 17.3 ERROR DETECTION AND REPORTING 16.4 CONFIG3: Address=0x03; Default=0x08 Bit Field Name Description 7:4 RESERVED. Always write 0. 3:0 0 <= RX_ERR_CNT 15 Threshold = 1 + RX_ERR_CNT The slave enters the error state once `Threshold' number of consecutive FRAME or PARITY errors are counted. The threshold is programmable to prevent occasional errors from being reported. See table in Section 17.3 ERROR DETECTION AND REPORTING RX_ERR_CNT 11 www.national.com DAC161P997 16.5 ERR_LOW: Address=0x04; Default=0x24 Bit Field Name Description 8-bit value. If ERRLVL = LOW, the DAC will use the value stored in ERR_LOW register to set the output current sourced from OUT pin when reporting an error condition. The ERR_LOW value is used as the upper byte of the DACCODE, while the lower byte is forced to 0x00. At power up the ERR_LOW defaults to a value which forces IERRL output current. SeeSection 13.0 Electrical Characteristics 7:0 16.6 ERR_HIGH: Address=0x05; Default=0xE8 Bit Field 7:0 www.national.com Name Description If ERRLVL = HIGH, the DAC will use the value stored in ERR_HIGH register to set the output current sourced from OUT pin when reporting an error condition. The ERR_HIGH value is used as the upper byte of the DACCODE, while the lower byte is forced to 0x00. At power-up the ERR_HIGH defaults to a value which forces IERRH output current. See Section 13.0 Electrical Characteristics 12 17.1 16-BIT DAC AND LOOP DRIVE 17.1.1 DC Characteristics The DAC converts the 16-bit input code in the DACCODE register to an equivalent current output. The DAC output is a current pulse which is then filtered by a 3rd order RC lowpass filter and boosted to produce the loop current ILOOP at the device OUT pin. Figure 1 shows the principle of operation of the DAC161P997 in the Loop Powered Transmitter - the circuit details were omitted for clarity. In this figure ID and IA represent supply (quiescent) currents of the internal digital and analog blocks. IAUX represents supply (quiescent) current of companion devices present in the system, such as the voltage regulator and the SWIF channel. While ILOOP has a number of component currents, ILOOP = IDAC+ID+IA+IAUX+IE, it is only IE that is regulated by the loop to maintain the relationship shown above. Since it is only IE's magnitude that is controlled, not its direction, there is a lower limit to ILOOP. This limit is dependent on the fixed components IA and ID, and on system implementation through IAUX. 30154430 FIGURE 1. Loop-Powered Transmitter Figure 2 shows the variant of the transmitter where the supply currents to the system blocks are provided by the local supply, and not the 4 - 20 mA loop Self-Powered Transmitter. Same basic relationship between the ILOOP and IDAC holds, but the component currents of ILOOP are only IDAC and IE. 30154445 FIGURE 2. Self-Powered Transmitter 13 www.national.com DAC161P997 By observing that the control loop formed by the amplifier and the bipolar transistor forces the voltage across R1 and R2 to be equal, it can be shown that, under normal conditions, the ILOOP is dependent only on IDAC through the following relationship: 17.0 Application Information DAC161P997 sum of supply currents of the DAC161P997 internal blocks, IA, ID, and companion devices present in the system, IAUX. The last component current IE can theoretically be controlled down to 0 but, due to the stability considerations of the control loop, it is advised not to allow the IE to drop below 200 A. The graph in Figure 3 shows the DC transfer characteristic of the 4 - 20 mA transmitter, including minimum current limits. The minimum current limit for the Loop-Powered Transmitter is typically around 400 A (ID+IA+IAUX+IE). The minimum current limit for the Self-Powered Transmitter is typically around 200 A (IE). Typical values for ID and IA are listed in the Electrical Characteristics table. IE depends on the BJT device used. 17.1.1.1 DC Input-Output Transfer Function The output current sourced by the OUT pin of the device is expressed by: The valid DACCODE range is the full 16-bit code space (0x0000 to 0xFFFF), which results in the IDAC range of 0 to approximately 12 A. This, however, does not result in the ILOOP range of 0 to 24 mA. The maximum output current sourced out of OUT pin, ILOOP, is 24 mA. The minimum output current is dependent on the system implementation. The minimum output current is the 30154429 FIGURE 3. DAC DC Transfer Function The NPN BJT should not be replaced with an N-channel FET (Field Effect Transistor) for the following reasons: discrete FET's typically have high threshold voltages (VT), in the order of 1.5V to 2V, which is beyond the BASE output maximum range; discrete FET's present higher load capacitance which may degrade system stability margins; and BASE output relies on the BJT's base current for biasing. 17.1.1.2 Loop Interface The DAC161P997 cannot directly interface to the typical 4 20 mA loop due to the excessive loop supply voltage. The loop interface has to provide the means of stepping down the LOOP Supply down to 3.6V. This can be accomplished with either a linear regulator (LDO) or switching regulator while keeping in mind that the regulator's quiescent current will have direct effect on the minimum achievable ILOOP (see Section 17.1.1.1 DC Input-Output Transfer Function). The second component of the loop interface is the external NPN transistor (BJT). This device is part of the control circuit that regulates the transmitter's output current (ILOOP). Since the BJT operates over the wide current range, spanning at least 4 - 20 mA, it is necessary to degenerate the emitter in order to stabilize transistor's transconductance (gm). The degeneration resistor of 22 is suggested in typical applications. For circuit details, see Section 18.0 Application Circuit Examples. www.national.com 17.1.1.3 Loop Compliance The maximum V(LOOP+,LOOP-) potential is limited by the choice of step-down regulator, and the external BJT's Collector Emitter breakdown voltage. For minimum V(LOOP+, LOOP-) potential consider Figure 2. Here, observe that V (LOOP+,LOOP-)min(VCE) + ILOOPRE + ILOOPR2=min(VCE) + 0.53V + 0.96V=3.66V, at ILOOP=24mA. The voltage drop accross internal R2 is specified in Section 13.0 Electrical Characteristics 14 DAC161P997 17.1.2 AC Characteristics The approximate frequency dependent characteristics of the loop drive circuit can be analyzed using the circuit in Figure 4: 30154447 FIGURE 4. Capacitances affecting Control Loop Here it is assumed that the internal amplifier dominates the frequency response of the system, and it has a single pole response. The BJT's response, in the bandwidth of the control loop, is assumed to be frequency independent and is characterized by the transconductance gm and the output resistance ro. As in previous sections IDAC and IAUX represent the filtered output of the modulator and the quiescent current of the companion devices. The circuit in Figure 4 can be further simplified by omitting the on-board capacitances, whose effect will be discussed in Section 17.1.2.4 Stability, and by combining the amplifier, the external transistor and resistor RE into one Gm block. The resulting circuit is shown in Figure 5. By assuming that the BJT's output resistance (ro) is large, the loop current ILOOP can be expressed as: 30154449 FIGURE 5. AC Analysis Model of a Transmitter 15 www.national.com DAC161P997 The sum of voltage drops around the path containing R1, R2 and ve is: By considering the circuit in Figure 5, and setting IDAC = IAUX = 0, the following expression can be obtained: an assumption is made on the response of the internal amplifier:: As in Section 17.1.2 AC Characteristics an assumption can be made on the frequency response of the internal amplifier, and the effective transconductance Gm should be stabilized with external RE leading to: By combining the above the final expression for the ILOOP as a function of 2 inputs IDAC and IAUX is: The output impedance of the transmitter is a product of the external BJT's output resistance ro, and the frequency characteristics of the internal amplifier. At low frequencies this results in a large impedance that does not significantly affect the output current accuracy. 17.1.2.3 PSRR Power Supply Rejection Ratio is defined as the ability of the current control loop to reject the variations in the supply current of the companion devices, IAUX. Specifically: The result above reveals that there are 2 distinct paths from the inputs IDAC and IAUX to the output ILOOP. IDAC follows the low-pass, and the IAUX follows the high-pass path. In both cases the corner frequency is dependent on the effective transconductance, Gm, of the external transistor. This implies that control loop dynamics could vary with the output current ILOOP if Gm were allowed to be just native device transconductance gm. This undesirable behavior is mitigated by the degenerating resistor RE which stabilizes Gm as follows: It was shown in Section 17.1.2 AC Characteristics that the IAUX affects ILOOP via the high-pass path whose corner frequency is dependent on the effective Gm of the external BJT. If that dependence were not mitigated with the degenerating resistor RE, the PSRR would be degraded at low output current ILOOP. The typical PSRR performance of the transmitter shown in Section 18.0 Application Circuit Examples is shown in Section 15.0 . This results in the frequency response which is largely independent of the output current ILOOP: 17.1.2.4 Stability The current control loop's stability is affected by the impedances present in the system. Figure 4 shows the simplified diagram of the control loop, formed by the on-board amplifier and an external BJT, and the lumped capacitances CX1 through CX4 that model any other external elements. CX1 typically represents a local step-down regulator, or LDO, and any other companion devices powered from the LOOP+. This capacitance reduces the stability margins of the control loop, and therefore it should be limited. RX1 can be used to isolate CX1 from LOOP+ node and thus remedy the stability margin reduction. If RX1 = 0, CX1 cannot exceed 10 nF. RX1 = 200 is recommended if it can be tolerated. Minimum RX1 = 40 if CX1 exceeds 10 nF. CX3 also adversely affects stability of the loop and it must be limited to 20 pF. CX4 affects the control loop in the same way as CX1, and it should be treated in the same way as CX1. CX2 is the only capacitance that improves stability margins of the control loop. Its maximum size is limited only by the safety requirements. Stability is a function of ILOOP as well. Since ILOOP is approximately equal to the collector current of the external BJT, Gm of the BJT, and thus loop dynamics, depend on ILOOP. This While the bandwidth of the IDAC path may not be of great consequence given the low frequency nature of the 4-20 mA current loop systems, the location of the pole in the IAUX path directly affects PSRR of the transmitter circuit. This is further discussed in Section 17.1.2.3 PSRR. 17.1.2.1 Step Response The transient input-output characteristics of the DAC161P997 are dominated by the response of the RC filter at the output of the DAC. Settling times due to step input are shown in Section 15.0 . 17.1.2.2 Output impedance The output impedance is described as: www.national.com 16 noise performance of the device throughout the entire code range of the DAC. This results in the "U" shaped noise characteristic as a function of output current. At narrow bandwidths, and particularly at mid-scale output currents, it is the amplifier driving the external BJT that starts to dominate as a noise source. 17.1.2.5 Noise and Ripple The output of the DAC is a current pulse train. The transition density varies throughout the DAC input code range (ILOOP range). At the extremes of the code range, the transition density is the lowest which results in low frequency components of the DAC output passing through the RC filter. Hence, the magnitude of the ripple present in ILOOP is the highest at the ends of the transfer characteristic of the device (see Section 15.0 ). It should be noted that at wide noise measurement bandwidth, it is the ripple due to the modulator that dominates the 17.1.2.6 Digital Feedthrough Digital feedthrough is indiscernible from the ripple induced by the modulator. 17.1.2.7 HART Signal Injection The HART specification requires minimum suppression of the sensor signal in the HART signal band (1-2 kHz) of about 60 dB. The filter in Figure 6 below meets that requirement. 30154431 FIGURE 6. HART Signal Injection 17.1.2.8 RC Filter Limitation In an effort to speed up the transient response of the device the user can reduce the capacitances associated with the lowpass filter at the output of the modulator. However, to maintain stability margins of the current control loop it is necessary to have at least C1=C2=C3=1nF. 17.2 SINGLE-WIRE INTERFACE (SWIF) SWIF provides flexible and easy to implement digital data link between the Master (transmitter) and the Slave (receiver). The Master encodes the digital data into a square (NRZ) CMOS level waveform which can be generated using common microcontroller resources. The Slave (DAC161P997) translates the waveform back into a bit stream which is then interpreted as the output current update or configuration data. SWIF can operate in both Simplex (unidirectional) and HalfDuplex (bidirectional) modes. In the DAC161P997's implementation of SWIF, an Acknowledge pulse constitutes the reverse data flowing from the Slave back to the Master. In its simplest implementation, the waveform can be directly coupled to the DAC161P997 input. In typical systems, however, SWIF data is transmitted via the galvanic isolation element such as pulse transformer or an opto-coupler. The details of the circuit implementations are discussed in Section 17.2.4 Interface Circuit. 17.1.3 Alarm Current The DAC161P997 reports faults to the plant controller by forcing the OUT current into one of the error bands. The error current bands are defined as either above 20 mA, or below 4mA. The error band selection is done via the ERRLVL pin. The exact value of the output current used to indicate fault is dictated by the contents of ERR_HIGH and ERR_LOW registers. See Section 16.5 ERR_LOW: Address=0x04; Default=0x24 and Section 16.6 ERR_HIGH: Address=0x05; Default=0xE8. The default settings for LOW ERROR CURRENT and HIGH ERROR CURRENT are specified in Section 13.0 Electrical Characteristics 17 www.national.com DAC161P997 dependence can be reduced by degenerating the emitter of the BJT with a small resistance as discussed in Section 17.1.1.2 Loop Interface. Inductance in series with the LOOP+ and LOOP- do not significantly affect the control loop. DAC161P997 Section 17.2.1 Frame Format through Section 17.2.3 Symbol Set describe the data encoding and the SWIF protocol. of payload (HIGH Slice) - a total of nine symbols. The second parity symbol corresponds to bit parity of the second byte of payload only (LOW Slice) - a total of 8 symbols. P0 = [ ( Number of ones in LOW Slice ) mod 2 == 0 ] P1 = [ ( Number of ones in HIGH Slice ) mod 2 == 0 ] Symbol `D' after the parity bits completes a valid frame. The symbol "A" is optional, but if present it has to immediately follow the last "D" symbol of the frame. The duration of acknowledge symbol "A" is always twice the duration of P0 symbol preceding it. See Figure 7. SWIF does not require that all symbols in valid frames are sent by the Master at a fixed Baud rate. Each symbol is evaluated individually and is recognized as valid as long as it conforms to the duration requirement (Tp) and its duty cycle falls outside of noise margins. (See Table 1 below.) 17.2.1 Frame Format A frame begins with a minimum of one idle symbol. There can be more than one and each has the effect of resetting the frame buffer of the DAC161P997. After idle symbol "D" a Tag Bit specifies the destination of the frame. If the tag is symbol `0' then frame's destination is the DACCODE register. If tag is a `1' the destination is one of the configuration registers. The following 16 symbols constitute the data payload. If current frame is a DAC frame, the entire payload is a single DACCODE word. If it is a configuration frame, the first byte is the register address and the second byte is the register data. Words are transmitted MSB first. Two parity symbols follow the payload. The first parity symbol is determined by the bit parity of the tag bit and the first byte 30154427 FIGURE 7. Data Frame Format CONFIG2: Address=0x02; Default=0x1F and Section 17.3 ERROR DETECTION AND REPORTING. 17.2.2 Inter-Frame Period The fastest DAC update rate is achieved when Master sends the valid frames back to back, Continuous Mode, at the fastest Baud rate. This, however, results in the least power efficient implementation. 30154467 30154465 Sending the `L' in the inter-frame period results in the transmission line being inactive (transition-free) except when the data frames are being transmitted. This is the most power efficient implementation of SWIF link, but it does not facilitate link integrity reporting. To avoid ERRB being asserted due to the channel inactivity, CONFIG2.CHANNEL should be cleared. SWIF is designed to operate in the Burst Mode as well, where the valid frames are separated by the inter-frame periods that do not carry any data. The inter-frame period can be occupied by a stream of idle `D' or `L' symbols. 17.2.3 Symbol Set The digital data encoding scheme is outlined in the table below. The signal names in the table correspond to the nodes shown in Figure 13. The signal waveforms due to a random symbol stream are shown in Figure 8 30154466 Sending the `D' symbol in the inter-frame period provides continuous verification of integrity of the data link. The device by default monitors the activity of the SWIF link, and if the activity ceases the ERRB flag is asserted. See Section 16.3 www.national.com 18 DAC161P997 TABLE 1. Symbol Set Table Character Mnemonic SWIF Symbol Comments Occupies one symbol period -- -- Transmit from Master only -- 25% duty-cycle square waveform -- Terminates LOW "0" -- Occupies one symbol period -- Transmit from Master only -- 75% duty-cycle square waveform -- Terminates LOW "1" -- Occupies one symbol period -- Transmit from Master only -- 50% duty-cycle square waveform -- Terminates LOW "D" -- Occupies two symbol periods -- Master stops driving the SWIF and "listens" for acknowledge pulse from the Slave -- Slave pulls ACKB LOW to reverse the direction of data flow through the transformer -- Slave's DBACK will drive the SWIF pri_rx line between 50% points of the adjacent periods - in this interval Master must de-assert pri_tx_en_n -- Terminates with pri_tx=LOW and pri_tx_en_n=LOW -- Occupies one symbol period, but can be repeated indefinitely -- Transmit from Master only "A" -- Always LOW -- Does not carry any meaningful information "L" -- Used as an inter-frame symbol, i.e., sent by the Master between valid data frames 19 www.national.com DAC161P997 30154464 FIGURE 8. Symbol stream example 17.2.4 Interface Circuit SWIF interface components are shown in Figure 9. The buffers A and B comprise a square waveform recovery circuit in applications where a pulse transformer is used to cross the galvanic isolation boundary, see Section 17.2.4.1 Transformer Coupled Interface - Data Flow to the DAC. The ACKB output and its internal NMOS switch provide the means of reversing the direction of data flow through the coupling transformer see Section 17.2.4.2 Transformer Coupled Interface Acknowledge Pulse. In simple cases where the data link is DC coupled buffer A alone acts as a data receiver. The buffer C is provided for cases where improved noise immunity is required, see Section 17.2.4.3 DC-Coupled Interface. 17.2.4.1 Transformer Coupled Interface - Data Flow to the DAC In systems requiring galvanic isolation between the transmitter (micro-controller) and the receiver, the commonly used coupling element is a pulse transformer. Transformer passes only the AC components of the square input waveform resulting in an impulse train across the secondary winding. Buffers A and B form a latch circuit around the secondary winding that recovers the square waveform from the impulse train. Figure 10 shows the details of the square waveform transmission from the primary side and recovery of the signal on the secondary side. Transmitter's DC component is blocked by the capacitor CP. The transmitter's output waveform VO results in the impulse train VP across the primary winding. Similar impulse train then appears across the secondary winding. If the magnitude of the impulse exceeds the threshold on the A buffer, the latch formed by A and B buffers will change state. The new latch state will persist until an opposite polarity impulse appears across the secondary winding. Note that in Figure 10 the capacitor CS bottom plate floats, and thus does not affect the operation of this circuit. 30154411 FIGURE 9. SWIF Front End www.national.com 20 DAC161P997 30154413 FIGURE 10. Transformer coupled SWIF link with the DAC161P997 as Receiver On the secondary side buffer B drives the square waveform across the transformer. Capacitor CS, whose bottom plate is now grounded via the ACKB pin, blocks the DC component of the square waveform. Buffer A is inactive. On the primary side a square waveform recovery is performed by the now familiar latch. 17.2.4.2 Transformer Coupled Interface - Acknowledge Pulse Since the transformer is a symmetrical device (particularly one with 1:1 winding ratio), it is simple to reverse the data flow through it. Figure 11 shows the SWIF interface circuit during the transmission of the Acknowledge pulse from the DAC161P997 on the secondary side back to the micro-controller on the primary side. 30154414 FIGURE 11. Transformer coupled SWIF link with the DAC161P997 as transmitter nity of the input circuit. Presence of the buffer C and its output resistor facilitate this. The Hysteresis can be easily realized by inserting RIN between the transmitter and DIN input. Note that when RIN=0 the presence of the buffer C can be ignored. 17.2.4.3 DC-Coupled Interface DC coupled signal path between the transmitter and the receiver is shown in Figure 12. Such circuit as the internal buffer A is sufficient for the signal recovery as the signal presented at the DIN input is a square CMOS level waveform. In noisy environments it may be necessary to implement a Hysteresis loop around the DIN input to improve noise immu- 21 www.national.com DAC161P997 30154412 FIGURE 12. DC-Coupled SWIF Input While transmitting, Master drives the pri_tx_en_n LOW and sources data stream onto the pri_tx. The circuit path is through buffer `a', transformer primary winding, DC blocking capacitor to GND. While receiving, Master drives the pri_tx_en_n HIGH and `listens' for acknowledge signal pri_rx. In this mode the buffers `a' and `b' form the latch around the transformer winding, and buffer `c' floats the DC blocking capacitor. 17.2.4.4 SWIF Implementation Examples An example of implementation of the SWIF data link is shown in the figure below. This implementation uses the components already present in the systems employing the standard methods for PWM signal transmission over an isolation boundary. In this example Master uses 2 digital I/Os: * One bidirectional port for transmitting encoded data to, and receiving the acknowledge signal from the slave - pri_tx/pri_rx. * One output sourcing the pri_tx_en_n signal that governs the direction of the data flow over the SWIF link. 30154417 FIGURE 13. Typical SWIF implementation The interface implementation shown in Figure 13 can be expanded or simplified depending on the requirements of the system and capabilities of the Master controller. A number of other possible implementations are shown in the figures below. www.national.com Figure 14 shows the circuit analogous in its functionality to the circuit in Figure 13 but with fewer active components. Here instead of disabling `b' buffer during data transmission, its output impedance is increased to the point where its drive is significant only during the data reception form the Slave. 22 DAC161P997 30154418 FIGURE 14. SWIF Link with Simplified Control Figure 15 shows the SWIF link circuit when the Master does not have a bidirectional I/O available. The Master output driv- ing pri_tx is split away from the Master receiving pri_rx input by using a buffer `d', until now unused, on 74LVC125. 30154419 FIGURE 15. Master without Bidirectional I/O 23 www.national.com DAC161P997 Figure 16 shows the trivial circuit realization of the SWIF link in simplex mode, unidirectional data flow. 30154420 FIGURE 16. SWIF without Acknowledge Capability Figure 17 shows the DC coupled SWIF link realization. In this example ACKB output is used to generate the Acknowledge pulse. This is equivalent to the Acknowledge pulse generated at DBACK, since in transformer coupled application both ACKB and DBACK have to be pulsed to transmit back to the Master. Note that the pulse generated by ACKB is active LOW. 30154421 FIGURE 17. DC-Coupled SWIF Link www.national.com 24 creased power consumption due to the relatively large currents required to turn on the internal diodes and standing current in the pull-up resistors. 30154433 FIGURE 18. SWIF Link Realized with Octo-couplers ter. The application circuit schematic utilizing T1/E1 transformer as the isolation element is shown in Section 18.0 Application Circuit Examples. A number of suggested off the shelf transformers are listed in Table 2. 17.2.4.5 Transformer Selection and SWIF Data Link Circuit Design In general, the transformers developed for T1/E1 telecom applications are well suited as the interface element for the DAC161P997 in the galvanically isolated industrial transmit- TABLE 2. Examples of Transformers Suitable in the DAC161P997 Applications Manuf P/N LM (mH) LLP/S (H) RP/S (O) CWW (pF) Isolation Voltage (Vrms) Pulse TX1491 1.2 1.2 2.7 35 1500 Coilcraft S5394-CLB 0.4 Not Specified 0.95 0.92 1500 Halo TG02-1205 1.2 Not Specified 0.7 30 1500 XFMRS XF7856-GD11 0.785 0.5 0.52 Not Specified 1500 25 www.national.com DAC161P997 The SWIF link realization using opto-couplers (opto-isolators) is shown in Figure 18. Points of note here are: the opto-couplers invert the SWIF symbol waveform, and there is in- DAC161P997 Model suitable for simulating the behavior of the pulse transformer is shown in Figure 19. The model parameters are readily available in the datasheets provided by the transformer manufacturers, see Table 2 for examples. 30154415 FIGURE 19. Pulse Transformer Model - Winding Ratio 1:1 TABLE 3. Transformer Model Parameters' Legend Parameter LM Description Magnetizing inductance, in Data Sheets shown as OCL (open circuit inductance) LLP/S Leakage inductance of the primary (secondary) winding CWP/S Winding capacitance. Dominated by the CWW (winding to winding) component. Here it is assumed that CWS=CWP=1/2CWW RP/S Winding resistance The circuit behavior will be dominated by the DC blocking capacitance CP and the magnetizing inductance LM. In the example circuit shown in Figure 20 the rising edge of VO ultimately results in an impulse at the input DIN, see Figure 21. Once voltage at DIN is above VIH of the A buffer, the A buffer will change its state. However, the latch will acquire a new state only if the voltage at DIN persists above VIH for TPEAK > TD. The parasitic elements in the transformer model: LLS, LSP, CWS, CWP may result in the oscillating component superim- posed on the dominant impulse response waveform shown in Figure 21. The oscillation should be controlled so that the condition TPEAK> TD is maintained. The typical method for controlling this parasitic oscillation is to insert a damping element into the signal path. A small resistance in series with transformer winding is such damping element. The typical application example in Section 18.0 Application Circuit Examples illustrates this. The delay around the SWIF input latch, from DIN to DBACK, TD is specified inSection 13.0 Electrical Characteristics . 30154416 FIGURE 20. NRZ Waveform Transmission and Recovery Circuit Model www.national.com 26 DAC161P997 30154432 FIGURE 21. SWIF Link Circuit Response to Step Input 27 www.national.com DAC161P997 ERR_LOW registers. Once the condition causing the fault is removed the OUT will return to the last valid output level prior to the occurrence of the fault. Table below summarizes the detectable faults, and means of reporting. The interval TM is governed by the internal timer and is specified in Section 13.0 Electrical Characteristics . 17.3 ERROR DETECTION AND REPORTING The user can modify the CONFIG2:(LOOP | CHANNEL | PARITY | FRAME) bits to mask or enable the reporting of any of the detectable fault conditions. The DAC161P997 reports errors by asserting the ERRB signal, and by setting the current sourced by OUT to a value dictated by the state at ERRLVL pin and the contents of the ERR_HIGH and REPORTING ERROR CAUSE ERRB Value used by the DAC to set OUT pin current LOW ERR_LOW The device cannot sustain the required output current at OUT pin, typically caused by drop in loop supply, or increased load impedance. LOOP The DAC161P997 automatically clears this fault after interval of TM and attempts to establish output current dictated by the value in the DACCODE register CHANNEL no valid symbols have been received on DIN in last interval of TM LOW ERRLVL=1: ERR_HIGH ERRLVL=0: ERR_LOW PARITY SWIF received a valid data frame, but a bit error has been detected by parity check LOW ERRLVL=1: ERR_HIGH ERRLVL=0: ERR_LOW FRAME invalid symbol received, or an incorrect number of valid symbols were detected in the frame LOW ERRLVL=1: ERR_HIGH ERRLVL=0: ERR_LOW www.national.com 28 DAC161P997 30154443 18.0 Application Circuit Examples 29 www.national.com DAC161P997 19.0 Physical Dimensions inches (millimeters) unless otherwise noted LLP-16 Package NS Package Number SQA16A www.national.com 30 DAC161P997 Notes 31 www.national.com DAC161P997 Single-Wire 16-bit DAC for 4-20mA Loops Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH(R) Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise(R) Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagicTM www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise(R) Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PRODUCTS. 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