25 NXP Semiconductors
MM912_637
ELECTRICAL CHARACTERISTICS
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred
to the receive data register and the receive data register full (RDRF) status flag is set. If RDRF was already set indicating the receive data
register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered,
the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver
overrun.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCID.
The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles
receive data. Refer to Section 4.13.3.4, “Interrupts and status flags" for more details about flag clearing.
4.13.3.3.1 Data sampling technique
The SCI receiver uses a 16× baud rate clock for sampling. The receiver starts by taking logic level samples at 16 times the baud rate to
search for a falling edge on the RxD serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1
samples. The 16× baud rate clock is used to divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is
located, three more samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of
these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determine the logic level for that bit.
The logic level is interpreted to be that of the majority of the samples taken during the bit time. In the case of the start bit, the bit is assumed
to be 0 if at least two of the samples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s.
If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise
flag (NF) will be set when the received character is transferred to the receive data buffer.
The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit
times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case
analysis because some characters do not have any extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling
edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. The receiver is inhibited from receiving
any new characters until the framing error flag is cleared. The receive shift register continues to function, but a complete character cannot
transfer to the receive data buffer if FE is still set.
4.13.3.3.2 Receiver wake-up operation
Receiver wake-up is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a
different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the
message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIC2. When RWU bit is set,
the status flags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is set) are inhibited from setting,
thus eliminating the software overhead for handling the unimportant message characters. At the end of a message, or at the beginning of
the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next
message.
4.13.3.3.2.1 Idle-line wake-up
When WAKE = 0, the receiver is configured for idle-line wake-up. In this mode, RWU is cleared automatically when the receiver detects
a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are
needed to constitute a full character time (10 or 11 bit times because of the start and stop bits).
When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE flag. The receiver wakes up
and waits for the first data character of the next message which will set the RDRF flag and generate an interrupt if enabled. When RWUID
is one, any idle condition sets the IDLE flag and generates an interrupt if enabled, regardless of whether RWU is zero or one.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit
so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When ILT = 1, the idle bit counter
does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message.
4.13.3.3.2.2 Address-mark wake-up
When WAKE = 1, the receiver is configured for address-mark wake-up. In this mode, RWU is cleared automatically when the receiver
detects a logic 1 in the most significant bit of a received character (eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark
wake-up allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. The logic 1 MSB
of an address frame clears the RWU bit before the stop bit is received and sets the RDRF flag. In this case, the character with the MSB
set is received even though the receiver was sleeping during most of this character time.