INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCHR16601
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
1JANUARY 2004INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2004 Integrated Device Technology, Inc. DSC-4491/5
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
•VCC = 2.5V ± 0.2V
• CMOS power levels (0.4μμ
μμ
μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
IDT74ALVCHR16601
3.3V CMOS 18-BIT UNIVERSAL
BUS TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low Switching Noise
B1
A1
LEAB
CLKBA
OEBA
LEBA
CLKAB
TO 17 OTHER CHANNELS
CE
1D
C1
CE
1D
C1
CLK
CLKENAB
OEAB
CLKENBA
27
29
30
2
28
55
56
1
354
CLK
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The transceiver combines D-type latches and D-type
flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and
OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is
latched if CLKAB is held at a high or low logic level. If LEAB is low, the data
is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output
enable OEAB is active low. When OEAB is low, the outputs are active. When
OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA
and CLKENBA.
The ALVCHR16601 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold levels.
The ALVCHR16601 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVCHR16601
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
OEAB
A1
GND
A2
A3
VCC
A4
A5
GND
A6
A7
A8
A9
A11
A12
GND
A13
A14
A15
VCC
A16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1CLKENAB
B1
GND
B2
B3
VCC
B4
B5
B6
B7
B8
B9
GND
B11
B12
B13
B14
GND
B15
B16
B17
GND
A18
OEBA
LEBA
25
26
27
28
32
31
30
29
GND
B18
CLKBA
CLKENBA
A10
A17
VCC
B10
LEAB CLKAB
TSSOP
TOP VIEW
PIN CONFIGURATION
NOTE:
1. As applicable to the device type.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 5 7 pF
COUT Output Capacitance VOUT = 0V 7 9 pF
CI/O I/O Port Capacitance VIN = 0V 7 9 pF
Symbol Description Max Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –50 to +50 mA
IIK Continuous Clamp Current, ±50 mA
VI < 0 or VI > VCC
IOK Continuous Clamp Current, VO < 0 –50 mA
ICC Continuous Current through each ±100 mA
ISS VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA,
CLKBA, and CLKENBA.
2 . H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
3. Output level before the indicated steady-state input conditions were established.
FUNCTION TABLE(1,2)
Inputs Outputs
CLKENAB OEAB LEAB CLKAB Ax Bx
XH X X X Z
XLHX LL
XLHX HH
HLLX XB
(3)
LLL↑LL
LLL↑HH
L L L L or H X B(3)
PIN DESCRIPTION
Pin Names Description
OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
Ax A-to-B Data Inputs or B-to-A 3-State Outputs(1)
Bx B-to-A Data Inputs or A-to-B 3-State Outputs(1)
CLKENAB A-to-B Clock Enable Input (Active LOW)
CLKENBA B-to-A Clock Enable Input (Active LOW)
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCHR16601
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
3
Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH Input HIGH Current VCC = 3.6V VI = VCC ——±5µA
IIL Input LOW Current VCC = 3.6V VI = GND — — ±5µA
IOZH High Impedance Output Current VCC = 3.6V VO = VCC ——±10 µA
IOZL (3-State Output pins) VO = GND — — ±10
VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V
VHInput Hysteresis VCC = 3.3V — 100 — mV
ICCL Quiescent Power Supply Current VCC = 3.6V — 0.1 40 µA
ICCH VIN = GND or VCC
ICCZ
ΔICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol Parameter(1) Test Conditions Min. Typ.(2) Max. Unit
IBHH Bus-Hold Input Sustain Current VCC = 3V VI = 2V – 75 — — µA
IBHL VI = 0.8V 75 — —
IBHH Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V – 45 — — µA
IBHL VI = 0.7V 45 — —
IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V — — ±500 µA
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCHR16601
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Symbol Parameter Test Conditions Typical Typical Unit
CPD Power Dissipation Capacitance Outputs enabled CL = 0pF, f = 10Mhz 56 63 pF
CPD Power Dissipation Capacitance Outputs disabled 12 13
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 2.3V IOH = – 4mA 1.9 —
IOH = – 6mA 1.7 —
VCC = 2.7V IOH = – 4mA 2.2 —
IOH = – 8mA 2 —
VCC = 3V IOH = – 6mA 2.4 —
IOH = – 12mA 2 —
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 2.3V IOL = 4mA — 0.4
IOL = 6mA — 0.55
VCC = 2.7V IOL = 4mA — 0.4
IOL = 8mA — 0.6
VCC = 3V IOL = 6mA — 0.55
IOL = 12mA — 0 .8
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCHR16601
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
5
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fMAX 150 —150 —150 —MHz
tPLH Propagation Delay 1 4.8 —5.1 1 4.4 ns
tPHL Ax to Bx or Bx to Ax
tPLH Propagation Delay 1 5.5 —5.8 1 5.1 ns
tPHL LEAB to Bx or LEBA to Ax
tPLH Propagation Delay 1.2 5.9 —6.3 1.4 5.4 ns
tPHL CLKAB to Bx or CLKBA to Ax
tPZH Output Enable Time 1.1 6.3 —6.6 1.1 5.6 ns
tPZL OEAB to Bx or OEBA to Ax
tPZH Output Disable Time 1 4.2 —5.1 1.6 4.7 ns
tPZL OEAB to Bx or OEBA to Ax
tSU Set-up Time, data before CLK↑2.3 —2.4 —2.1 —ns
tSU Set-up Time, data before LE↓, CLK HIGH 2 —1.6 —1.6 —ns
tSU Set-up Time, data before LE↓, CLK LOW 1.3 —1.2 —1.1 —ns
tSU Set-up Time, CLKEN before CLK↑2—2—1.7 —ns
tHHold Time, data after CLK↑0.7 —0.7 —0.8 —ns
tHHold Time, data after LE↓, CLK HIGH 1 . 3 —1.6 —1.4 —ns
tHHold Time, data after LE↓, CLK LOW 1.7 —2—1.7 —ns
tHHold Time, CLKEN after CLK↑0.3 —0.5 —0.6 —ns
tWPulse Width, LE HIGH 3.3 —3.3 —3.3 —ns
tWPulse Width, CLK HIGH or LOW 3.3 —3.3 —3.3 —ns
tSK(O) Output Skew(2) —————500 ps
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCHR16601
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Open
VLOAD
GND
VCC
Pulse
Generator D.U.T.
500Ω
500Ω
CL
RT
VIN VOUT
(1, 2)
ALVC Link
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK (x)
OUTPUT 1
OUTPUT 2
tPHL1
tSK (x)
tPLH2 tPHL2
VT
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
VOH
VOL
tPLH tPHL
tPHL
tPLH
OUTPUT
VIH
VT
VT
VIH
VT
ALVC Link
DATA
INPUT 0V
0V
0V
0V
tREM
TIMING
INPUT
SYNCHRONOUS
CONTROL
tSU tH
tSU tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
VT
ALVC Link
CONTROL
INPUT
tPLZ 0V
OUTPUT
NORMALLY
LOW tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VLZ
VOH
VT
VT
tPZL
VLOAD/2 VLOAD/2
VIH
VT
VOL
VHZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
Output Skew - tSK(X)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
VLOAD 6 6 2 x Vcc V
VIH 2.7 2.7 Vcc V
VT1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
CL50 50 30 pF
TEST CONDITIONS
SWITCH POSITION
Test Switch
Open Drain
Disable Low VLOAD
Enable Low
Disable High GND
Enable High
All Other Tests Open
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCHR16601
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
7
ORDERING INFORMATION
IDT XX ALVC XXX XX
PackageDevice Type
Temp. Range
PA
PAG
R16
74
Thin Shrink Small Outline Package
TSSOP - Green
18-Bit Universal Bus Transceiver with 3-State Outputs
-40°C to +85°C
XXX
FamilyBus-Hold
601
Bus-Hold
Double-Density, ±12mA
H
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 logichelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
