TC4027BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4027BP, TC4027BF TC4027B Dual J-K Master-Slave Flip Flop TC4027B is J-K master-slave flip-flop having RESET and SET functions. In the case of J-K made, when the clock input is given with both RESET and SET at "L", the output changes at rising edge of the clock according to the states of J and K. When SET input is placed at "H", and RESET input is placed at "L", outputs become Q = "H", and Q = "L". When RESET input is placed at "H", and SET input is placed at "L", outputs become Q = "L", and Q = "H". When both of RESET input and SET input are at "H", outputs become Q = "H" and Q = "H". TC4027BP TC4027BF Pin Assignment Weight DIP16-P-300-2.54A SOP16-P-300-1.27A : 1.00 g (typ.) : 0.18 g (typ.) Block Diagram Start of commercial production 1985-02 1 2014-03-01 TC4027BP/BF Truth Table Inputs Outputs RESET SET J K CLOCK Qn + 1 Qn + 1 L H * * * H L H L * * * L H H H * * * H H L L L L Qn* Qn* L L L H L H L L H L H L L L H H Qn ** Qn** L L * * Qn* Qn * *: Don't care : Level change *: No change **: Change Logic Diagram 1/2 TC4027B Absolute Maximum Ratings (Note) Characteristics DC supply voltage Symbol Rating Unit VDD VSS - 0.5 to VSS + 20 V V VIN VSS - 0.5 to VDD + 0.5 VOUT VSS - 0.5 to VDD + 0.5 V IIN 10 mA Power dissipation PD 300 (DIP)/180 (SOP) mW Operating temperature range Topr -40 to 85 C Storage temperature range Tstg -65 to 150 C Input voltage Output voltage DC input current Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 2 2014-03-01 TC4027BP/BF Operating Ranges (VSS = 0 V) (Note) Characteristics Symbol Test Condition Min Typ. Max Unit DC supply voltage VDD 3 18 V Input voltage VIN 0 VDD V Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VDD or VSS. Static Electrical Characteristics (VSS = 0 V) Characteristics High-level output voltage Low-level output voltage Symbol VOH VOL IOH 25C 85C VDD (V) Min Max Min Typ. Max Min Max 5 4.95 4.95 5.00 4.95 10 9.95 9.95 10.00 9.95 15 14.95 14.95 15.00 14.95 5 0.05 0.00 0.05 0.05 10 0.05 0.00 0.05 0.05 15 0.05 0.00 0.05 0.05 5 -0.61 -0.51 -1.0 -0.42 VOH = 2.5 V 5 -2.50 -2.10 -4.0 -1.70 VOH = 9.5 V 10 -1.50 -1.30 -2.2 -1.10 VOH = 13.5 V 15 -4.00 -3.40 -9.0 -2.80 VOL = 0.4 V 5 0.61 0.51 1.2 0.42 VOL = 0.5 V 10 1.50 1.30 3.2 1.10 VOL = 1.5 V 15 4.00 3.40 12.0 2.80 VOUT = 0.5 V, 4.5 V 5 3.5 3.5 2.75 3.5 VOUT = 1.0 V, 9.0 V 10 7.0 7.0 5.50 7.0 VOUT = 1.5 V, 13.5 V 15 11.0 11.0 8.25 11.0 VOUT = 0.5 V, 4.5 V 5 1.5 2.25 1.5 1.5 VOUT = 1.0 V, 9.0 V 10 3.0 4.50 3.0 3.0 VOUT = 1.5 V, 13.5 V 15 4.0 6.75 4.0 4.0 18 0.1 10 -5 0.1 1.0 -0.1 -1.0 30 IOUT < 1 A VIN = VSS, VDD IOUT < 1 A VIN = VSS, VDD VOH = 4.6 V Output high current -40C Test Condition Unit V V mA VIN = VSS, VDD Output low current IOL mA VIN = VSS, VDD Input high voltage VIH V IOUT < 1 A Input low voltage VIL V IOUT < 1 A Input current "H" level "L" level Quiescent supply current IIH IIL IDD VIH = 18 V VIL = 0 V VIN = VSS, VDD (Note) -5 18 -0.1 -10 5 1 0.002 1 10 2 0.004 2 60 15 4 0.008 4 120 A A Note: All valid input combinations. 3 2014-03-01 TC4027BP/BF Dynamic Electrical Characteristics (Ta = 25C, VSS = 0 V, CL = 50 pF) Characteristics Output transition time (low to high) Output transition time (high to low) (CLOCK-Q, Q ) tpHL Propagation delay time tpLH (SET, RESET-Q, Q ) tpHL trCL Max clock input fall time tfCL Min clock pulse width Min set-up time (J, K-CLOCK) Min hold time (J, K-CLOCK) Min removal time (SET, RESET-CLOCK) Input capacitance fCL Max clock input rise time (SET, RESET) tTHL tpLH Min pulse width VDD (V) tTLH Propagation delay time Max clock frequency Test Condition Symbol Min Typ. Max 5 70 200 10 35 100 15 30 80 5 70 200 10 35 100 15 30 80 5 150 300 10 75 130 15 60 90 5 120 300 10 60 130 15 45 90 5 3.5 8 10 8.0 16 15 12.0 20 Unit ns ns ns ns MHz 5 10 s No limit 15 tW tW tSU tH trem CIN 4 5 60 180 10 35 80 15 25 50 5 60 140 10 35 60 15 25 40 5 30 140 10 10 50 15 5 35 5 140 10 50 15 35 5 40 10 20 15 15 5 7.5 ns ns ns ns ns pF 2014-03-01 TC4027BP/BF Waveforms for Measurement of Dynamic Characteristics Waveform 1 Waveform 2 Waveform 3 5 2014-03-01 TC4027BP/BF Package Dimensions Weight: 1.00 g (typ.) 6 2014-03-01 TC4027BP/BF Package Dimensions Weight: 0.18 g (typ.) 7 2014-03-01 TC4027BP/BF RESTRICTIONS ON PRODUCT USE * Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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