1
®
FN8131.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5323, X5325
(Replaces X25323, X25325)
CPU Supervisor with 32kBit SPI EEPROM
These devices combine four popular functions, Power-on
Reset Control, Watchdog T imer , Supply V oltage Supervision,
and Block Lock Protect Serial EEPROM Memo ry in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device acti vates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point.
RESET/RESET is asserted until VCC returns to proper
operating level and stabilizes. Five industry standard VTRIP
thresholds are available, how ever, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher preci s ion.
Features
• Selectable watchdog timer
•Low V
CC detection and reset assertion
- Five standard reset threshold voltages
- Re-program low VCC reset threshold voltage using
special programming sequence
- Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a volatile
flag bit
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 32kbits of EEPROM
• Built-in inadverte nt write protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock™ protection
- In ci rcuit programmable ROM mode
• 2MHz SPI interface modes (0,0 and 1,1)
• Minimize EEPROM programming time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free (RoHS compliant)
Block Diagram
WATCHDOG
TIMER RESET
DATA
REGISTER
COMMAND
DECODE AND
CONTROL
LOGIC
SI
SO
SCK
CS/WDI
VCC
RESET AND
WATCHDOG
TIMEBASE
POWER-ON AND
GENERATION
VTRIP
+
-
RESET/RESET
RESET
LOW VOLTAGE
STATUS
REGISTER
PROTECT LOGIC
8kBITS
8kBITS
16kBITS
EEPROM ARRAY
WATCHDOG TRANSITION
DETECTOR
WP
X5323 = RESET
X5325 = RESET
V
CC
THRESHOLD
RESET LOGIC
Data Sheet June 30, 2008
2FN8131.2
June 30, 2008
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW) PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH) PART
MARKING VCC RANGE
(V) VTRIP RANGE TEMP
RANGE (°C) PACKAGE
X5323P-4.5A X5323P AL X5325P-4.5A X5325P AL 4.5 to 5.5 4.5 to 4.75 0 to +70 8 Ld PDIP
X5323PZ-4.5A (Note) X5323P ZAL X5325PZ-4.5A X5325P ZAL 0 to +70 8 Ld PDIP** (Pb-free)
X5323PI-4.5A X5323P AM X5325PI-4.5A X5325P AM -40 to +85 8 Ld PDIP
X5323PIZ-4.5A (Note) X5323P ZAM X5325PIZ-4.5A X5325P ZAM -40 to +85 8 Ld PDIP** (Pb-free)
X5323S8-4.5A X5323 AL X5325S8-4.5A X5325 AL 0 to +70 8 Ld SOIC
X5323S8Z-4.5A (Note) X5323 ZAL X5325S8Z-4.5A (Note) X5325 ZAL 0 to +70 8 Ld SOIC (Pb-free)
X5323S8I-4.5A* X5323 AM X5325S8I-4.5A X5325 AM -40 to +85 8 Ld SOIC
X5323S8IZ-4.5A*
(Note) X5323 ZAM X5325S8IZ-4.5A
(Note) X5325 ZAM -40 to +85 8 Ld SOIC (Pb-free)
X5323V14-4.5A X5323 VAL X5325V14-4.5A X5325 VAL 0 to +70 14 Ld TSSOP
X5323V14Z-4.5A
(Note) X5323 VZAL X5325V14Z-4.5A
(Note) X5325 VZAL 0 to +70 14 Ld TSSOP
(Pb-free)
X5323V14I-4.5A X5323 VAM X5325V14I-4.5A X5325 VAM -40 to +85 14 Ld TSSOP
X5323V14IZ-4.5A
(Note) X5323 VZAM X5325V14IZ-4.5A
(Note) X5325 VZAM -40 to +85 14 Ld TSSOP
(Pb-free)
X5323P X5323P X5325P X5325P 4.5 to 5.5 4.25 to 4.5 0 to +70 8 Ld PDIP
X5323PZ (Note) X5323P Z X5325PZ X5325P Z 0 to +70 8 Ld PDIP** (Pb-free)
X5323PI X5323P I X5325PI X5325P I -40 to +85 8 Ld PDIP
X5323PIZ (Note) X5323P ZI X5325PIZ X5325P ZI -40 to +85 8 Ld PDIP** (Pb-free)
X5323S8* X5323 X5325S8* X5325 0 to +70 8 Ld SOIC
X5323S8Z* (Note) X5323 Z X5325S8Z* (Note) X5325 Z 0 to +70 8 Ld SOIC (Pb-free)
X5323S8I* X5323 I X5325S8I* X5325 I -40 to +85 8 Ld SOIC
X5323S8IZ* (Note) X5323 ZI X5325S8IZ* (Note) X5325 ZI -40 to +85 8 Ld SOIC (Pb-free)
X5323V14* X5323 V X5325V14* X5325 V 0 to +70 14 Ld TSSOP
X5323V14Z* (Note) X5323 VZ X5325V14Z* (Note) X5325 VZ 0 to +70 14 Ld TSSOP
(Pb-free)
X5323V14I* X5323 VI X5325V14I* X5325 VI -40 to +85 14 Ld TSSOP
X5323V14IZ* (Note) X5323 VZI X5325V14IZ* (Note) X5325 VZI -40 to +85 14 Ld TSSOP
(Pb-free)
X5323P-2.7A X5323P AN X5325P-2.7A X5325P AN 2.7 to 5.5 2.85 to 3.0 0 to +70 8 Ld PDIP
X5323PZ-2.7A (Note) X5323P ZAN X5325PZ-2.7A X5325P ZAN 0 to +70 8 Ld PDIP** (Pb-free)
X5323PI-2.7A X5323P AP X5325PI-2.7A X5325P AP -40 to +85 8 Ld PDIP
X5323PIZ-2.7A (Note) X5323P ZAP X5325PIZ-2.7A X5325P ZAP -40 to +85 8 Ld PDIP** (Pb-free)
X5323S8-2.7A* X5323 AN X5325S8-2.7A X5325 AN 0 to +70 8 Ld SOIC
X5323S8Z-2.7A*
(Note) X5323 ZAN X5325S8Z-2.7A (Note) X5325 ZAN 0 to +70 8 Ld SOIC (Pb-free)
X5323S8I-2.7A* X5323 AP X5325S8I-2.7A X5325 AP -40 to +85 8 Ld SOIC
X5323S8IZ-2.7A*
(Note) X5323 ZAP X5325S8IZ-2.7A
(Note) X5325 ZAP -40 to +85 8 Ld SOIC (Pb-free)
X5323, X5325
3FN8131.2
June 30, 2008
X5323V14-2.7A X5323 VAN X5325V14-2.7A X5325 VAN 2.7 to 5.5 2.85 to 3.0 0 to +70 14 Ld TSSOP
X5323V14Z-2.7A
(Note) X5323 VZAN X5325V14Z-2.7A
(Note) X5325 VZAN 0 to +70 14 Ld TSSOP
(Pb-free)
X5323V14I-2.7A X5323 VAP X5325V14I-2.7A X5325 VAP -40 to +85 14 Ld TSSOP
X5323V14IZ-2.7A
(Note) X5323 VZAP X5325V14IZ-2.7A
(Note) X5325 VZAP -40 to +85 14 Ld TSSOP
(Pb-free)
X5323P-2.7 X5323P F X5325P-2.7 X5325P F 2.7 to 5.5 2.55 to 2.7 0 to +70 8 Ld PDIP
X5323PZ-2.7 (Note) X5323P ZF X5325PZ-2.7 X5325P ZF 0 to +70 8 Ld PDIP** (Pb-free)
X5323PI-2.7 X5323P G X5325PI-2.7 X5325P G -40 to +85 8 Ld PDIP
X5323PIZ-2.7 (Note) X5323P ZG X5325PIZ-2.7 X5325P ZG -40 to +85 8 Ld PDIP** (Pb-free)
X5323S8-2.7* X5323 F X5325S8-2.7* X5325 F 0 to +70 8 Ld SOIC
X5323S8Z-2.7* (Note) X5323 ZF X5325S8Z-2.7* (Note) X5325 ZF 0 to +70 8 Ld SOIC (Pb-free)
X5323S8I-2.7* X5323 G X5325S8I-2.7* X5325 G -40 to +85 8 Ld SOIC
X5323S8IZ-2.7* (Note) X5323 ZG X5325S8IZ-2.7* (Note) X5325 ZG -40 to +85 8 Ld SOIC (Pb-free)
X5323V14-2.7* X5323 VF X5325V14-2.7* X5325 VF 0 to +70 14 Ld TSSOP
X5323V14Z-2.7*
(Note) X5323 VZF X5325V14Z-2.7*
(Note) X5325 VZF 0 to +70 14 Ld TSSOP
(Pb-free)
X5323V14I-2.7* X5323 VG X5325V14I-2.7* X5325 VG -40 to +85 14 Ld T SSOP
X5323V14IZ-2.7*
(Note) X5323 VZG X5325V14IZ-2.7*
(Note) X5325 VZG -40 to +85 14 Ld T SSOP
(Pb-free)
*Add “-T1” for tape and reel. Please refer to TB347 for details on reel specifications.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW) PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH) PART
MARKING VCC RANGE
(V) VTRIP RANGE TEMP
RANGE (°C) PACKAGE
Pinouts X5323, X5325
(8 LD SOIC, PDIP)
TOP VIEW
X5323, X5325
(14 LD TSSOP)
TOP VIEW
CS/WDI
WP
SO
1
2
3
4
RESET/RESET
8
7
6
5
VCC
VSS
SCK
SI
SO
WP
VSS
1
2
3
4
5
6
7
SCK
SI
14
13
12
11
10
9
8
NC
VCC
NC
CS/WDI
NC
NC
NC
NC
RESET/RESET
X5323, X5325
4FN8131.2
June 30, 2008
Pin Descriptions
PIN NUMBER
(SOIC/PDIP) PIN NUMBER
TSSOP PIN NAME PIN FUNCTION
11CS
/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway , the device will be in the stand-by power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation
after power-up, a HIGH to LOW transition on CS is required.
Watchdog Inpu t. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET/RESET going active.
22SOSerial Output. SO is a push/pull serial data output pin. A read cycle shifts dat a out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
58SISerial Input. SI is a serial data input pin. In put all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and da ta MS B first.
69SCKSerial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
36WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
47V
SS Ground
814V
CC Supply Voltage
7 13 RESET/
RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdo g timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
3 to 5,10 to 12 NC No internal connections
X5323, X5325
5FN8131.2
June 30, 2008
Principles of Operation
Power-on Reset
Application of power to the X5323/X5325 activates a
power-on reset circuit. This circuit goes active at ab out 1V
and pulls the RESET/RESET pin active. This signal prevents
the system microprocessor from starting to operate with
insuf ficient volt ag e or prio r to st abili zati on of the oscillator. As
long as RESET/RESET pin is active, the device w ill no t
respond to any Read/W rite instruction. Whe n VCC exceeds
the device VTRIP value for 200ms (nominal) the circuit
releases RESET/RESET, allowing the processor to begin
executing code.
Low Voltage Monitoring
During operation, the X5323/X5325 monitors th e VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brown-out condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor must
toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be tog g l ed
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the status register determine the watchdog timer period. The
microprocessor can change these watchdog bits, or they
may be “locked” by tying the WP pin LOW and setting the
WPEN bit HIGH.
VCC Threshold Reset Procedure
The X5323/X53 25 has a standard VCC threshold (VTRIP)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard VTRIP is not exactly right, or for higher precision in
the VTRIP value, the X5323/X5325 threshold may be
adjusted.
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage value. For
example, if the current VTRIP is 4.4V and the new VTRIP is
4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessa ry
to reset the trip point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the VCC pin and tie the CS/WDI pin and the WP
pin HIGH. RESET/RESET and SO pins are left
unconnected. Then apply the programming voltage VP to
both SCK and SI and pulse CS/WDI LOW then HIGH.
Remove VP and the sequence is complete.
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a “native” voltage level. For
example, if the current VTRIP is 4.4V and the VTRIP is reset,
the new VTRIP is something le ss than 1.7V. This procedure
must be used to set the voltage to a lower value.
To reset the VTRIP voltage, apply a voltage between 2.7V
and 5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin,
and the SCK pin HIGH. RESET/RESET and SO pins are left
unconnected. Then apply the programming volt age VP to the
SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove
VP and the sequence is complete.
SCK
SI
VP
VP
CS
FIGURE 1. SET VTRIP VOLTAGE
SCK
SI
VCC
VP
CS
FIGURE 2. RESET VTRIP VOLTAGE
X5323, X5325
6FN8131.2
June 30, 2008
VTRIP PROGRAMMING
APPLY 5V TO VCC
DECREMENT VCC
RESET PIN
GOES ACTIVE?
MEASURED VTRIP -
DESIRED VTRIP
DONE
EXECUTE
SEQUENCE
RESET VTRIP
SET VCC = VCC APPLIED =
DESIRED VTRIP
EXECUTE
SEQUENCE
SET VTRIP
NEW VCC APPLIED =
OLD VCC APPLIED + ERROR
(VCC = VCC - 10mV)
EXECUTE
SEQUENCE
RESET VTRIP
NEW VCC APPLIED =
OLD VCC APPLIED - ERROR
ERROR ≤ EMAX
ERROR < EMAX
YES
NO
ERROR ≥ EMAX
EMAX = MAXIMUM DESIRED ERROR
FIGURE 3. VTRIP PROGRAMMING SEQUENCE FLOW CHART
X5323,
1
2
3
4
8
7
6
5
VTRIP
ADJ.
PROGRAM
NC
NC
VP
RESET VTRIP
TEST VTRIP
SET VTRIP
NC
RESET
4.7kΩ
4.7kΩ
10kΩ10kΩ
+
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
X5325
X5323, X5325
7FN8131.2
June 30, 2008
SPI Serial Memory
The memory portion of the device is a CMOS serial EEPRO M
array with Intersil’s block lock protection. The array is
internally organized as x8. The device features a Serial
Peripheral Interface (SPI) and sof tw are proto col allow ing
operation on a simple fo ur-wire b us.
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directl y wi th the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller fami lies. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW . Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
Write Enable Latch
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latc h (Fi g ure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid write cycle.
Status Register
The RDSR instruction provides access to the status register.
The status registe r may be read at any time , e ven duri ng a
write cycle. The status register is formatted as foll ows:
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
The Write Enable Latch (WEL) bit indicates the status of
the write enable latch. When WEL = 1, the latch is set
HIGH and when WEL = 0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of the
array that is block lock protected can be read but not written. It
will remain protected until the BL bits are altered to disable
block lock protection of that portion of memory .
NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
7 6543210
WPEN FLB WD1 WD0 BL1 BL0 WEL WIP
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME INSTRUCTION FORMAT* OPERATION
WREN 0000 0110 Set the write enable latch (enable write operations)
SFLB 0000 0000 Set flag bit
WRDI/RFLB 0000 0100 Reset the write enable latch/reset flag bit
RSDR 0000 0101 Read status register
WRSR 0000 0001 Write status register (watchdog, block lock, WPEN and flag bits)
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
TABLE 2. BLOCK PROTECT MATRIX
WREN CMD STATUS REGISTER DEVICE PIN BLOCK BLOCK STATUS REGISTER
WEL WPEN WP Protected Block Unprote cted Block WPEN, BL0, BL1 WD0, WD1
0 X X Protected Protected Protected
1 1 0 Protected Writable Protected
1 0 X Protected Writable Writable
1 X 1 Protected Writable Writable
X5323, X5325
8FN8131.2
June 30, 2008
.
The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction.
The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instruction s . Th e fl ag bi t is automatically reset upon
power-up. This flag can be used by the system to determine
whether a reset occurs as a result of a watchdog time out or
power failure.
Note: The W atch Dog Timer is shipped disabled. (WD1 = 1,
WD0 = 1. The factory default for Memory Block Protection is
‘None’. (BL1 = 0, BL0 = 0).
The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in co njunc tion with the WP pin to
provide an in-circuit programmable ROM function (Table 2). WP
is LOW and WPEN bit programmed HIGH disables all status
register write operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog bits
from inadvertent corruption.
In the locked state (programmable ROM mode) the WP pin is
LOW and the nonvolatile bit WPEN is “1”. This mode disables
nonvolatile writes to the device’s status register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the status register is in progress will
not stop this write operation, but the operation disables
subsequent write attempts to the status register.
When WP is HIGH, all functions, including nonvolatile writes
to the status register operate normally. Setting the WPEN bit
in the status register to “0” blocks the WP pin function,
allowing writes to the status register when WP is HIGH or
LOW. Setting the WPEN bit to “1” while the WP pin is LOW
activates the programmable ROM mode, thus requiring a
change in the WP pin prior to subsequent status register
changes. This allows manufacturing to install the device in a
system with WP pin grounded and still be able to program
the status register. Manufacturing can then load
configuration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to be
protected by setting the block lock bits, and finally set the
“OTP mode” by setting the WPEN bit. Data changes now
require a hardware change.
Read Sequence
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address.
After the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted out
on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted out.
STATUS
REGISTER BITS ARRAY ADDRESSES PROTECTED
BL1 BL0 X5323/X5325
0 0 None (factory default)
0 1 $0C00 to $0FFF
1 0 $0800 to $0FFF
1 1 $0000 to $0FFF
STATUS REGISTER BITS WATCHDOG TIME-OUT
(TYPICAL)WD1 WD0
0 0 1.4s
0 1 600ms
1 0 200ms
1 1 disabled (factory default)
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
7 654321 0
DATA OUT
CS
SCK
SI
SO
MSB
HIGH IMPEDANCE
INSTRUCTION 16-BIT ADDRESS
15 14 13 3 2 1 0
FIGURE 5. READ EEPROM ARRAY SEQUENCE
X5323, X5325
9FN8131.2
June 30, 2008
When the highest address is reached, the address counter
rolls over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is terminated by
taking CS high. Refer to the read EEPROM Array Sequence
(Figure 1).
To read the status register, the CS line is first pulled low to
select the device followed by the 8-bit RDSR instruction.
After the RDSR opcode is sent, the contents of the status
register are shifted out on the SO line. Refer to the read
status register sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 3). CS is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS must then be taken HIGH. If
the user continues the write operation without taking CS
HIGH after issuing the WREN instruction, the write operation
will be ignored.
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16-bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the page and overwrite any data that may
have been previously written.
Note: When writing more than one page, you must wait one
write cycle (10ms typical) when going from one page to
another. This is required for the internal nonvolatile memory
to be programmed correctly.
For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought HIGH
at any other time, the write operati on will not be completed
(Figure 4).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0 and
1 must be “0”.
While the write is in progress following a status register or
EEPROM Sequence, the status register may be read to
check the WIP bit. During this time the WIP bit will be high.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• The flag bit is reset.
• Reset signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the write enable
latch.
•CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
01234567891011121314
76543210
DATA OUT
CS
SCK
SI
SO
MSB
HIGH IMPEDANCE
INSTRUCTION
FIGURE 6. READ STATUS REGISTER SEQUENCE
X5323, X5325
10 FN8131.2
June 30, 2008
Symbol Table
01234567
CS
SI
SCK
HIGH IMPEDANCE
SO
FIGURE 7. WRITE ENABLE LATCH SEQUENCE
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
32 33 34 35 36 37 38 39
SCK
SI
CS
012345678910
SCK
SI
INSTRUCTION 16-BIT ADDRESS DATA BYTE 1
76543210
CS
40 41 42 43 44 45 46 47
DATA BYTE 2
76543210
DATA BYTE 3
76543210
DATA BYTE N
15 14 13 3 2 1 0
20 21 22 23 24 25 26 27 28 29 30 31
654 321 0
FIGURE 8. WRITE SEQUENCE
0123456789
CS
SCK
SI
SO HIGH IMPEDANCE
INSTRUCTION DATA BYTE
76543210
10 11 12 13 14 15
FIGURE 9. STAT US REGISTER WRITE SEQUENCE
X5323, X5325
11 FN8131.2
June 30, 2008
Absolute Maximum Ratings Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to VSS . . . . . . . . . . . .-1.0V to +7V
DC Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Operating Conditions
Temperature Range (Industrial). . . . . . . . . . . . . . . . .-40°C to +85°C
Temperature Range (Commercial). . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
DC Electrical Specifications Over the recommended operating conditions, unless otherwise specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VCC Write Current (active) ICC1 SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open 5 mA
VCC Read Current (active) ICC2 SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open 0.4 mA
VCC Standby Current WDT = OFF ISB1 CS = VCC, VIN = VSS or VCC, VCC =5.5V 1 µA
VCC Standby Current WDT = ON ISB2 CS = VCC, VIN = VSS or VCC, VCC = 5.5V 50 µA
VCC Standby Current WDT = ON ISB3 CS = VCC, VIN = VSS or VCC, VCC =3.6V 20 µA
Input Leakage Current ILI VIN = VSS to VCC 0.1 10 µA
Output Leakage Current ILO VOUT = VSS to VCC 0.1 10 µA
Input LOW Voltage VIL
(Note 1) -0.5 VCC x 0.3 V
Input HIGH Voltage VIH
(Note 1) VCC x 0.7 VCC + 0.5 V
Output LOW Voltage VOL1 VCC > 3.3V, IOL = 2.1mA 0.4 V
Output LOW Voltage VOL2 2V < VCC ≤ 3.3V, IOL = 1mA 0.4 V
Output LOW Voltage VOL3 VCC ≤ 2V, IOL = 0.5mA 0.4 V
Output HIGH Voltage VOH1 VCC > 3.3V, IOH = -1.0mA VCC - 0.8 V
Output HIGH Voltage VOH2 2V < VCC ≤ 3.3V, IOH = -0.4 mA VCC - 0.4 V
Output HIGH Voltage VOH3 VCC ≤ 2V, IOH = -0.25mA VCC - 0.2 V
Reset Output LOW Voltage VOLS IOL = 1mA 0.4 V
Capacitance TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL TEST CONDITIONS MAX UNIT
COUT (Note 2) Output Capacitance (SO, RESET/RESET) VOUT = 0V 8 pF
CIN (Note 2) Input Capacitance (SCK, SI, CS, WP)V
IN = 0V 6 pF
NOTES:
1. VIL min and VIH max are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
X5323, X5325
12 FN8131.2
June 30, 2008
Equivalent AC Load Circuit at 5V VCC
Serial Input Timing
5V
OUTPUT
100pF
5V
4.6kΩ
RESET/RESET
30pF
2.06kΩ
3.03kΩ
AC Test Conditions
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
AC Electrical Specifications Input pulse levels = VCC x 0.1 to VCC x 0.9; input rise and fall times = 10ns; input and ouput timing
level = VCC x 0.5. Over recommended operating conditions, unless otherwise specified.
PARAMETER SYMBOL
2.7 TO 5.5V
UNITMIN MAX
SERIAL INPUT TIMING
Clock Frequency fSCK 02MHz
Cycle Time tCYC 500 ns
CS Lead Time tLEAD 250 ns
CS Lag Time tLAG 250 ns
Clock HIGH Time tWH 200 ns
Clock LOW Time tWL 250 ns
Data Set-up Time tSU 50 ns
Data Hold Time tH50 ns
Input Rise Time tRI (Note 3) 100 ns
Input Fall Time tFI (Note 3) 100 ns
CS Deselect Time tCS 500 ns
Write Cycle Time tWC (Note 4) 10 ms
SCK
CS
SI
SO
MSB IN
tSU tRI
tLAG
tLEAD
tH
LSB IN
tCS
tFI
HIGH IMPEDANCE
X5323, X5325
13 FN8131.2
June 30, 2008
Serial Output Timing
Power-Up and Power-Down Timing
Serial Output Timing
PARAMETER SYMBOL
2.7 TO 5.5V
UNITMIN MAX
Clock Frequency fSCK 02MHz
Output Disable Time tDIS 250 ns
Output Valid From Clock Low tV250 ns
Output Hold Time tHO 0ns
Output Rise Time tRO (Note 3) 100 ns
Output Fall Time tFO (Note 3) 100 ns
NOTES:
3. This parameter is periodically sampled and not 100% tested.
4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
SCK
CS
SO
SI
MSB OUT MSB–1 OUT LSB OUT
ADDR
LSB IN
tCYC
tVtHO tWL
tWH
tDIS
tLAG
RESET (X5323)
RESET (X5323)
VCC
tPURST
tPURST
tR
tF
tRPD
0V
VTRIP VTRIP
X5323, X5325
14 FN8131.2
June 30, 2008
CS/WDI vs RESET/RESET Timing
RESET Output T iming
SYMBOL PARAMETER MIN TYP MAX UNIT
VTRIP Reset Trip Point Voltage, X5323-4.5A, X5323-4.5A 4.5 4.63 4.75 V
Reset Trip Point Voltage, X5323, X5325 4.25 4.38 4.5 V
Reset Trip Point Voltage, X5323-2.7A, X5325-2.7A 2.85 2.92 3.0 V
Reset Trip Point Voltage, X5323-2.7, X5325-2.7 2.55 2.63 2.7 V
VTH VTRIP Hysteresis (HIGH to LOW vs LOW to HIGH VTRIP Voltage) 20 mV
tPURST Power-up Reset Time-Out 100 200 280 ms
tRPD (Note 5) VCC Detect To Reset/Output 500 ns
tF (Note 5) VCC Fall Time 100 µs
tR (Note 5) VCC Rise Time 100 µs
VRVALID Reset Valid VCC 1V
NOTE:
5. This parameter is periodically sampled and not 100% tested.
CS/WDI
tCST
RESET
tWDO tRST tWDO tRST
RESET
RESET/RESET Output Timing
SYMBOL PARAMETER MIN TYP MAX UNIT
tWDO Watchdog Time-Out Period
WD1 = 1, WD0 = 0 100 200 300 ms
WD1 = 0, WD0 = 1 450 600 800 ms
WD1 = 0, WD0 = 0 1 1.4 2 s
tCST CS Pulse Width to Reset the Watchdog 400 ns
tRST Reset Time-Out 100 200 300 ms
X5323, X5325
15 FN8131.2
June 30, 2008
VTRIP Set Conditions
VTRIP Reset Conditions
SCK
SI
VP
VP
CS tVPS tVPH
tP
tVPS tVPH
tRP
tVPO
tVPO
tTSU
tTHD
VTRIP
VCC
SCK
SI
VCC
VP
CS tVPS tVPH
tP
tVPS tVP1
tRP
tVPO
tVPO
VCC*
*VCC > PROGRAMMED VTRIP
VTRIP Programming Specifications VCC = 1.7 to 5.5V; Temperature = 0°C to +70°C.
PARAMETER DESCRIPTION MIN MAX UNIT
tVPS SCK VTRIP Program Voltage Set-up Time 1 µs
tVPH SCK VTRIP Program Voltage Hold Time 1 µs
tPVTRIP Program Pulse Width 1µs
tTSU VTRIP Level Set-up Time 10 µs
tTHD VTRIP Level Hold (Stable) Time 10 ms
X5323, X5325
16 FN8131.2
June 30, 2008
tWC VTRIP Write Cycle Time 10 ms
tRP VTRIP Program Cycle Recovery Period (Between Successive Programming Cycles) 10 ms
tVPO SCK VTRIP Program Voltage Off-Time Before Next Cycle 0 ms
VPProgramming Voltage 15 18 V
VTRAN VTRIP Programed Voltage Range 1.7 5.0 V
Vta1 Initial VTRIP Program Voltage Accuracy (VCC Applied-VTRIP) (Programmed at +25°C) -0.1 +0.4 V
Vta2 Subsequent VTRIP Program Voltage Accuracy [(VCC Applied-Vta1)-VTRIP] (Programmed at +25°C) -25 +25 mV
Vtr VTRIP Program Voltage Repea tability (Successive Program Operat io ns; P rogram med at +25°C) -25 +25 mV
Vtv VTRIP Program Variation After Programming (0°C to +75°C; Programmed at +25°C) -25 +25 mV
NOTE:
6. VTRIP programming parameters are periodically sampled and are not 100% tested.
VTRIP Programming Specifications VCC = 1.7 to 5.5V; Temperature = 0°C to +70°C. (Continued)
PARAMETER DESCRIPTION MIN MAX UNIT
Typical Performance Curves
FIGURE 10. VCC SUPPLY CURRENT vs TEMPERATURE (ISB)FIGURE 11. TWDO vs VOLTAGE/TEMPERATURE (WD1, 0 = 1, 1)
FIGURE 12. VTRIP vs TEMPERATURE (PROGRAMMED AT +25°C) FIGURE 13. TWDO vs VOLTAGE/TEMPERATURE (WD1, 0 = 1, 0)
18
16
14
12
10
8
6
4
2
0
-40 25 90
TEMPERATURE (°C)
ISB (µA)
WATCHDOG TIMER OFF (VCC = 3V, 5V)WATCHDOG TIMER OFF (VCC = 3V, 5V)
WATCHDOG TIMER ON (VCC = 5V)
WATCHDOG TIMER ON (VCC = 5V)
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1.7 2.4 3.1 3.8 4.5 5.2
+90°C
+25°C
-40°C
RESET (s)
VOLTAGE (V)
5.025
5.000
4.975
3.525
3.500
3.475
2.525
2.500
2.475
025 85
VOLTAGE (V)
TEMPERATURE (°C)
VTRIP = 5V
VTRIP = 3.5V
VTRIP = 2.5V
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
1.7 5.2
RESET (s)
VOLTAGE (V)
2.4 3.1 3.8 4.5
+90°C
+25°C
-40°C
X5323, X5325
17 FN8131.2
June 30, 2008
FIGURE 14. TPURST vs TEMPERATURE FIGURE 15. TWDO vs VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1)
Typical Performance Curves
200
195
190
185
180
175
170
165
160
-40 25 90
TEMPERATURE (°C)
205
TIME (ms)
+90°C
+25°C
-40°C
200
195
190
185
180
175
170
165
160
205
RESET (s)
VOLTAGE (V)
1.7 5.22.4 3.1 3.8 4.5
X5323, X5325
18 FN8131.2
June 30, 2008
X5323, X5325
Plastic Dual-In-Line Packages (PDIP)
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
INCHES
TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20
A 0.210 0.210 0.210 0.210 0.210 MAX
A1 0.015 0.015 0.015 0.015 0.015 MIN
A2 0.130 0.130 0.130 0.130 0.130 ±0.005
b 0.018 0.018 0.018 0.018 0.018 ±0.002
b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015
c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002
D 0.375 0.750 0.750 0.890 1.020 ±0.010 1
E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010
E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2
e 0.100 0.100 0.100 0.100 0.100 Basic
eA 0.300 0.300 0.300 0.300 0.300 Basic
eB 0.345 0.345 0.345 0.345 0.345 ±0.025
L 0.125 0.125 0.125 0.125 0.125 ±0.010
N 8 14 16 18 20 Reference
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
D
L
A
eb
A1
NOTE 5
A2
SEATING
PLANE
L
N
PIN #1
INDEX
E1
12 N/2
b2
E
eB
eA
c
19 FN8131.2
June 30, 2008
X5323, X5325
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1 L
L1
DETAIL X 4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
INCHES
TOLERANCE NOTESSO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8131.2
June 30, 2008
X5323, X5325
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
α0o8o0o8o-
Rev. 2 4/06
