IDT79R4700133GHG - Integrated Device Technology

1 of 25 April 10, 2001

64-Bit RISC Microprocessor

Features

◆True 64-bit microprocessor

– 64-bit integer operations

– 64-bit floating-point operations

– 64-bit registers

– 64-bit virtual address space

◆High-performance microprocessor

– 260 Dhrystone MIPS at 200MHz

– 100 peak MFLOP/s at 200MHz

– Two-way set associative caches

– Simple 5-stage pipeline

◆High level of integration

– 64-bit, 200 MHz integer CPU

– 64-bit floating-point unit

– 16KB instruction cache

– 16KB data cache

– Flexible MMU with large, fully associative TLB

◆Low-power operation

– 3.3V power supply, for the “RV” part

– 5V power supply, for the “R” part

– Dynamic power management

– Standby mode reduces internal power

◆Fully software & pin-compatible with 40XX Processor Family

◆Available in 179-pin PGA or 208-pin QFP

◆Available at 80-200MHz, with mode bit dependent output

clock frequencies

◆64GB physical address space

◆Processor family for a wide variety of embedded

applications

– LAN switches

– Routers

– Color printers

Description

The IDT79R4700 64-bit RISC Microprocessor is both software and

pin-compatible with the R4XXX processor family. With 64-bit processing

capabilities, the R4700 provides more computational power and data

movement bandwidth than is delivered to typical embedded systems by

32-bit processors.

The R4700 is upwardly software compatible with the IDT79R3000™

microprocessor family, including the IDTRISController™ 79R3051™,

R3052™, R3041™, R3081™ as well as the R4640™, R4650™, RC64474/

475™ and R5000™. An array of development tools facilitates rapid

development of R4700-based systems, allowing a variety of customers

access to the MIPS Open Architecture philosophy.

Block Diagram

The IDT logo is a trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Inte-

grated Device Technology, Inc.

Read Buffer

Integer Register File

Integer/Address Adder

Data TLB Virtual

Shifter/Store Aligner

Logic Unit

Program Counter

PC Incrementer

Branch Adder

Load Aligner

Floating-point

Unpacker/Packer

Floating-point

Add/Sub/Cvt/Div/Sqrt

Integer Divide

Floating-point/Integer

Phase Lock Loop, Clocks

Instruction TLB Virtual

Joint TLB

Data Set A

Data Set B

Data Tag A

DTLB Physical

Address Buffer

Data Tag B

Instruction Tag A

Instruction Tag B

ITLB Physical

Store Buffer

Write Buffer

DVA

IVA

Instruction Set A

Instruction Set B

Multiply

Floating-point Control

Integer Control

SysAD

IBus

DBus

Coprocessor 0

System/Memory

Control

Tag AuxTag

Instruction Select

Control

Instruction Register

IDT79R4700

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IDT79R4700

This data sheet provides an overview of the R4700’s CPU features

and architecture. A more detailed description of this processor is

provided in the IDT79R4700 RISC Processor Hardware User’s Manual,

available from Integrated Device Technology (IDT). Information on

development support, applications notes and complementary products

is available on the IDT Web site www.idt.com or through your local IDT

sales representative.

Note: Throughout this data sheet and any other IDT materials for this

device, the R4700 indicates a 5V part; RV4700 designates a reduced

voltage (3V) part; and the RC4700 reflects either.

Figure 1 The RC4700 CPO Registers

Hardware Overview

The RC4700 processor family brings a high-level of integration

designed for high-performance computing. The R4700’s key elements

are briefly described below. A more detailed explanation of each

subsystem is available in the user’s manual.

Pipeline

The RC4700 uses a simple 5-stage pipeline, similar to the pipeline

structure implemented in the IDT79R32364. This pipeline’s simplicity

allows the RC4700 to be lower cost and lower power than super-scalar

or super-pipelined processors. The pipeline stages are shown in Figure

3 on page 3.

Integer Execution Engine

The R4700 implements the MIPS-III Instruction Set architecture and

is upwardly compatible with applications that run on earlier generation

parts.

Implementation of the MIPS-III architecture results in 64-bit opera-

tions, better code density, greater multi-processing support, improved

performance for commonly used code sequences in operating system

kernels and faster execution of floating-point intensive applications. All

TLB

(entries protected

from TLBWR)

EntryHi

10*

EntryLo0

EntryLo1

PageMask

Wired

Random

Index

Status

12* Cause

13*

EPC

14* ErrorEPC

30*

Count

Compare

11*

Context

XContext

20*

PRId

15* Config

16*

TagHi

29*

TagLo

28*

ECC

26* CacheErr

27*

BadVAddr

8* LLAddr

17*

* Register number

resource dependencies are made transparent to the programmer,

insuring transportability among implementations of the MIPS instruction

set architecture.

The MIPS integer unit implements a load/store architecture with

single cycle ALU operations (logical, shift, add, sub) and an autono-

mous multiply/divide unit. Register resources include:

◆32 general-purpose orthogonal integer registers

◆HI/LO result registers, for the integer multiply/divide unit

◆Program counter

Also, the on-chip floating-point co-processor adds 32 floating-point

registers and a floating-point control/status register.

The R4700 has 32 general-purpose registers (shown in Figure 2).

These registers are used for scalar integer operations and address

calculation. The register file consists of two read ports and one write

port and is fully bypassed to minimize operation latency in the pipeline.

ALU

The RC4700 ALU consists of the integer adder and logic unit. The

adder performs address calculations in addition to arithmetic operations,

and the logic unit performs all logical and shift operations. Each of these

units is highly optimized and can perform an operation in a single pipe-

line cycle.

Integer Multiply/Divide

To perform integer multiply and divide operations, the RC4700 uses

the floating-point unit. The results of the operation are placed in the HI

and LO registers. The values can then be transferred to the general

purpose register file using the MFHI/MFLO instructions. To prevent the

General Purpose Registers Multiply/Divide Registers

63 0

0630

r1 HI

r2 63 0

•LO

•

•Program Counter

•630

r29 PC

r30

r31

Figure 2 R4700 CPU Registers

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IDT79R4700

Figure 3 RC4700 Pipeline Stages

I01I 2I 1R 2R 1A 2A 1D 2D 1W 2W

I11I 2I 1R 2R 1A 2A 1D 2D 1W 2W

I21I 2I 1R 2R 1A 2A 1D 2D 1W •••

I31I 2I 1R 2R 1A 2A 1D •••

I41I 2I 1R 2R 1A •••

one cycle

Key to Figure

1I-1R Instruction cache access

2I Instruction virtual-to-physical address translation in ITLB

2A-2D Data cache access and load align

1D Data virtual-to-physical address translation in DTLB

1D-2D Virtual-to-physical address translation in JTLB

2R Register file read

2R Bypass calculation

2R Instruction decode

2R Branch address calculation

1A Issue or slip decision

1A-2A Integer add, logical, shift

1A Data virtual address calculation

2A Store align

1A Branch decision

2W Register file write

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IDT79R4700

occurrence of an interlock or stall, a required number of processor

internal cycles must occur between an integer multiply or divide and a

subsequent MFHI or MFLO operation.

Floating-Point Co-Processor

The RC4700 incorporates a complete floating-point co-processor on

chip and includes a floating-point register file and execution units. The

floating-point co-processor forms a “seamless” interface with the integer

unit, decoding and executing instructions in parallel with the integer unit.

Floating-Point Units

The RC4700 floating-point execution units support single and double

precision arithmetic, as specified in the IEEE Standard 754. The execu-

tion unit is separated into a multiply unit and a combined add/convert/

divide/square root unit. Overlap of multiplies and add/subtract is

supported. The multiplier is partially pipelined, allowing a new multiply to

begin every four cycles.

The RC4700 maintains fully precise floating-point exceptions while

allowing both overlapped and pipelined operations. Precise exceptions

are extremely important in mission-critical environments and highly

desirable for debugging in any environment.

The floating-point unit operation’s set includes floating-point add,

subtract, multiply, divide, square root, conversion between fixed-point

and floating-point format, conversion among floating-point formats and

floating-point compare. These operations comply with the IEEE Stan-

dard 754.

Table 1 lists the latencies of some of the floating-point instructions in

internal processor cycles. Note that multiplies are pipelined so that a

new multiply can be initiated every four pipeline cycles

Floating-Point General Register File

The floating-point register file is made up of thirty-two 64-bit regis-

ters. With the LDC1 and SDC1 instructions the floating-point unit can

take advantage of the 64-bit wide data cache and issue a co-processor

load or store doubleword instruction in every cycle.

The floating-point control register space contains two registers: one

for determining configuration and revision information for the copro-

cessor and one for control and status information. These are primarily

involved with diagnostic software, exception handling, state saving and

restoring, and control of rounding modes.

Operation 32-bit 64-bit

MULT 6 - 9 7 - 10

DIV 42 74

System Control Co-processor (CP0)

The system control co-processor in the MIPS architecture is respon-

sible for the virtual memory sub-system, the exception control system

and the diagnostics capability of the processor. In the MIPS architec-

ture, the system control co-processor (and thus the kernel software) is

implementation dependent.

System Control Co-Processor Registers

The RC4700 incorporates all system control co-processor (CP0)

registers, on-chip. These registers (shown in Figure 1 on page 2)

provide the path through which the virtual memory system’s page

mapping is examined and changed, exceptions are handled and oper-

ating modes are controlled (kernel vs. user mode, interrupts enabled or

disabled, cache features). In addition, to aid in cache diagnostic testing

and assist in data error detection, the RC4700 includes registers to

implement a real-time cycle counting facility.

Virtual-to-Physical Address Mapping

To establish a secure environment for user processing, the RC4700

provides the user, supervisor, and kernel modes of virtual addressing,

available to system software. Bits in a status register determine which

virtual addressing mode is used.

While in user mode, the RC4700 provides a single, uniform virtual

address space of 256GB (2GB for 32-bit address mode). When oper-

ating in the kernel mode, four distinct virtual address spaces—totalling

1024GB (4GB in 32-bit address mode)—are simultaneously available

and are differentiated by the high-order bits of the virtual address.

Operation Single

Precision

Double

Precision

ADD 4 4

SUB 4 4

MUL 4 5

DIV 32 61

SQRT 31 60

CMP 3 3

FIX 4 4

FLOAT 6 6

ABS 1 1

MOV 1 1

NEG 1 1

LWC1, LDC1 2 2

SWC1, SDC1 1 1

Table 1 RC4700 Instruction Latencies

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IDT79R4700

The RC4700 processor also supports a supervisor mode in which the

virtual address space is 256.5GB (2.5GB in 32-bit address mode),

divided into three regions that are based on the high-order bits of the

virtual address. If the RC4700 is configured for 64-bit virtual addressing,

the virtual address space layout is an upwardly compatible extension of

the 32-bit virtual address space layout. Figure 4 on page 5 shows the

address space layout for the 32-bit virtual address operation.

Memory Management Unit (MMU)

The Memory management unit controls the virtual memory system

page mapping. It consists of an instruction address translation buffer

(the ITLB), a data address translation buffer (the DTLB), a Joint TLB (the

JTLB), and co-processor registers used for the virtual memory mapping

sub-system.

Instruction TLB (ITLB)

The RC4700 also incorporates a two-entry instruction TLB. Each

entry maps a 4KB page. The instruction TLB improves performance by

allowing instruction address translation to occur in parallel with data

address translation. When a miss occurs on an instruction address

translation, the least-recently used ITLB entry is filled from the JTLB.

The operation of the ITLB is invisible to the user.

Data TLB (DTLB)

The RC4700 also incorporates a four-entry data TLB. Each entry

maps a 4KB page. The data TLB improves performance by allowing

data address translation to occur in parallel with instruction address

translation. When a miss occurs on a data address translation, the DTLB

is filled from the JTLB. The DTLB refill is pseudo-LRU: the least recently

used entry of the least recently used half is filled. The operation of the

DTLB is invisible to the user.

Joint TLB (JTLB)

For fast virtual-to-physical address decoding, the RC4700 uses a

large, fully associative TLB that maps 96 virtual pages to their corre-

sponding physical addresses. The TLB is organized as 48 pairs of even-

odd entries and maps a virtual address and address space identifier into

the large, 64GB physical address space.

Two mechanisms are provided to assist in controlling the amount of

mapped space and the replacement characteristics of various memory

regions. First, the page size can be configured, on a per-entry basis, to

map a page size of 4KB to 16MB (in multiples of 4). A CP0 register is

loaded with the page size of a mapping, and that size is entered into the

TLB when a new entry is written. Thus, operating systems can provide

special purpose maps; for example, a typical frame buffer can be

memory mapped using only one TLB entry.

The second mechanism controls the replacement algorithm, when a

TLB miss occurs. The RC4700 provides a random replacement algo-

rithm to select a TLB entry to be written with a new mapping; however,

the processor provides a mechanism whereby a system specific number

of mappings can be locked into the TLB and avoid being randomly

replaced. This facilitates the design of real-time systems, by allowing

deterministic access to critical software.

The joint TLB also contains information to control the cache coher-

ency protocol for each page. Specifically, each page has attribute bits to

determine whether the coherency algorithm is uncached, non-coherent

write-back, non-coherent write-through write-allocate or non-coherent

write-through no write-allocate. Non-coherent write-back is typically

used for both code and data on the RC4700; however, hardware-based

cache coherency is not supported.

Cache Memory

To keep the RC4700’s high-performance pipeline full and operating

efficiently, the RC4700 incorporates on-chip instruction and data caches

that can be accessed in a single processor cycle. Each cache has its

own 64-bit data path and can be accessed in parallel.

Instruction Cache

The RC4700 incorporates a two-way set associative on-chip instruc-

tion cache. This virtually indexed, physically tagged cache is 16KB in

size and is protected with word parity.

0xFFFFFFFF

0xE0000000

Kernel virtual address space

(kseg3)

Mapped, 0.5GB

0xDFFFFFFF Supervisor virtual address space

(sseg)

Mapped, 0.5GB

0xC0000000

0xBFFFFFFF

0xA0000000

Uncached kernel physical address space

(kseg1)

Unmapped, 0.5GB

0x9FFFFFFF

0x80000000

Cached kernel physical address space

(kseg0)

Unmapped, 0.5GB

0x7FFFFFF

0x00000000

User virtual address space

(useg)

Mapped, 2.0GB

Figure 4 Kernel Mode Virtual Addressing (32-bit Mode)

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IDT79R4700

Because the cache is virtually indexed, the virtual-to-physical

address translation occurs in parallel with the cache access, further

increasing performance by allowing these two operations to occur simul-

taneously. The tag holds a 24-bit physical address and valid bit and is

parity protected.

The instruction cache is 64-bits wide and can be refilled or accessed

in a single processor cycle. For a peak instruction bandwidth of 800MB/

sec at 200MHz, instruction fetches require only 32 bits per cycle. To

reduce power dissipation, sequential accesses take advantage of the

64-bit fetch. To minimize the cache miss penalty, cache miss refill writes

use 64 bits-per-cycle, and to maximize cache performance, the line size

is eight instructions (32 bytes).

Data Cache

For fast, single cycle data access, the RC4700 includes a 16KB on-

chip data cache that is two-way set associative with a fixed 32-byte

(eight words) line size.

The data cache is protected with byte parity and its tag is protected

with a single parity bit. It is virtually indexed and physically tagged to

allow simultaneous address translation and data cache access

The normal write policy is writeback, which means that a store to a

cache line does not immediately cause memory to be updated. This

increases system performance by reducing bus traffic and eliminating

the bottleneck of waiting for each store operation to finish before issuing

a subsequent memory operation. Software can however select write-

through on a per-page basis when it is appropriate, such as for frame

buffers.

Associated with the data cache is the store buffer. When the RC4700

executes a Store instruction, this single-entry buffer gets written with the

store data while the tag comparison is performed. If the tag matches,

then the data is written into the data cache in the next cycle that the data

cache is not accessed (the next non-load cycle). The store buffer allows

the R4700 to execute a store instruction every processor cycle and to

perform back-to-back stores without penalty.

The data cache can provide 8 bytes each clock cycle, for a peak

bandwidth of 1.6 GB/sec.

Write Buffer

Writes to external memory—whether they are cache miss write-

backs, stores to uncached or write-through addresses—use the on-chip

write buffer. The write buffer holds a maximum of four 64-bit address and

64-bit data pairs. The entire buffer is used for a data cache writeback

and allows the processor to proceed in parallel with memory updates.

System Interface

The RC4700 supports a 64-bit system interface. This interface oper-

ates from two clocks—TClock[1:0] and RClock[1:0]—provided by the

RC4700, at some division of the internal clock.

The system interface consists of a 64-bit Address/Data bus with

eight check bits and a 9-bit command bus protected with parity. In addi-

tion, there are eight handshake signals and six interrupt inputs. The

interface has a simple timing specification and is capable of transferring

data between the processor and memory at a peak rate of 500MB/sec

with a 67MHz bus.

System Address/Data Bus

The 64-bit System Address Data (SysAD) bus is used to transfer

addresses and data between the RC4700 and the rest of the system. It

is protected with an 8-bit parity check bus, SysADC.

The system interface is configurable to allow easier interfacing to

memory and I/O systems of varying frequencies. The data rate and the

bus frequency at which the RC4700 transmits data to the system inter-

face are programmable via boot time mode control bits. Also, the rate at

which the processor receives data is fully controlled by the external

device. Therefore, either a low cost interface requiring no read or write

buffering or a faster, high performance interface can be designed to

communicate with the RC4700. Again, the system designer has the flex-

ibility to make these price/performance trade-offs.

System Command Bus

The RC4700 interface has a 9-bit System Command (SysCmd) bus.

The command bus indicates whether the SysAD bus carries an address

or data. If the SysAD carries an address, then the SysCmd bus also

indicates what type of transaction is to take place (for example, a read

or write). If the SysAD carries data, then the SysCmd bus also gives

information about the data (for example, this is the last data word trans-

mitted, or the cache state of this data line is clean exclusive). The

SysCmd bus is bidirectional to support both processor requests and

external requests to the RC4700. Processor requests are initiated by

the RC4700 and responded to by an external device. External requests

are issued by an external device and require the RC4700 to respond.

The RC4700 supports one to eight byte and block transfers on the

SysAD bus. In the case of a sub-doubleword transfer, the low-order

three address bits give the byte address of the transfer, and the

SysCmd bus indicates the number of bytes being transferred.

Handshake Signals

There are six handshake signals on the system interface. Two of

these, RdRdy* and WrRdy* are used by an external device to indicate to

the RC4700 whether it can accept a new read or write transaction. The

RC4700 samples these signals before deasserting the address on read

and write requests.

ExtRqst* and Release* are used to transfer control of the SysAD and

SysCmd buses between the processor and an external device. When

an external device needs to control the interface, it asserts ExtRqst*.

The RC4700 responds by asserting Release* to release the system

interface to slave state.

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IDT79R4700

ValidOut* and ValidIn* are used by the RC4700 and the external

device respectively to indicate that there is a valid command or data on

the SysAD and SysCmd buses. The RC4700 asserts ValidOut* when it

is driving these buses with a valid command or data, and the external

device drives ValidIn* when it has control of the buses and is driving a

valid command or data.

Non-overlapping System Interface

The RC4700 bus uses a non-overlapping system interface. This

means that only one processor request may be outstanding at a time

and that the request must be serviced by an external device before the

RC4700 issues another request. The RC4700 can issue read and write

requests to an external device, and an external device can issue read

and write requests to the RC4700.

For processor read transaction the RC4700 asserts ValidOut* and

simultaneously drives the address and read command on the SysAD

and SysCmd buses. If the system interface has RdRdy* asserted, then

the processor tristates its drivers and releases the system interface to

slave state by asserting Release*. The external device can then begin

sending the data.

Figure 5 on page 10 shows a processor block read request and the

external agent read response. The read latency is four cycles (ValidOut*

to ValidIn*), and the response data pattern is DDxxDD. Figure 6 on

page 10 shows a processor block write.

Write Reissue and Pipeline Write

The RC4700 implements additional write protocols that have been

designed to improve performance. This implementation doubles the

effective write bandwidth. The write re-issue has a high repeat rate of

two cycles per write. A write issues if WrRdy* is asserted two cycles

earlier and is still asserted at the issue cycle. If it is not still asserted, the

last write re-issues again. Pipelined writes have the same two cycle per

write repeat rate but can issue one additional write after WrRdy* de-

asserts. They still follow the issue rule as R4x00 mode for other writes.

External Requests

The RC4700 responds to requests issued by an external device. The

requests can take several forms. An external device may need to supply

data in response to an RC4700 read request or it may need to gain

control over the system interface bus to access other resources which

may be on that bus. It also may issue requests to the processor, such as

a request for the RC4700 to write to the RC4700 interrupt register. The

RC4700 supports Write, Null, and Read Response external requests.

Boot-Time Options

Fundamental operational modes for the processor are initialized by

the boot-time mode control interface. The boot-time mode control inter-

face is a serial interface operating at a very low frequency (MasterClock

divided by 256). The low-frequency operation allows the initialization

information to be kept in a low-cost serial EEPROM; alternatively, the

20-or-so bits could be generated by the system interface ASIC or a

simple PAL.

Immediately after the VCCOK signal is asserted, the processor reads a

bit stream of 256 bits to initialize all fundamental operational modes.

After initialization is complete, the processor continues to drive the serial

clock output, but no further initialization bits are read.

JTAG Interface

The RC4700 supports the JTAG interface pins, with the serial input

connected to serial output. Boundary scan is not supported.

Boot-Time Modes

The boot-time serial mode stream is defined in Table 3. Bit 0 is the

first bit presented to the processor when VCCOK is asserted; bit 255 is the

last.

Power Management1

CP0 is also used to control the power management for the RC4700.

This is the standby mode and can be used to reduce the power

consumption of the internal core of the CPU. Standby mode is entered

by executing the WAIT instruction with the SysAD bus idle and is exited

by an interrupt.

Standby Mode Operations

The RC4700 provides a means to reduce the amount of power

consumed by the internal core when the CPU would otherwise not be

performing any useful operations. This is known as “Standby Mode.”

Entering Standby Mode

Executing the WAIT instruction enables interrupts and enters

Standby mode. When the WAIT instruction finishes the W pipe-stage, if

the SysAd bus is currently idle, the internal clocks will shut down, thus

freezing the pipeline. The PLL, internal timer, some of the input pin

clocks (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*), and the

output clocks—TClock[1:0], RClock[1:0] SyncOut, Modeclock and

MasterOut—will continue to run. If the conditions are not correct when

the WAIT instruction finishes the W pipe-stage (such as the SysAd bus

is not idle), the WAIT is treated as a NOP.

Once the CPU is in Standby Mode, any interrupt— including the

internally generated timer interrupt—will cause the CPU to exit Standby

Mode.

1. The R4700 implements advanced power management, to substantially

reduce the average power dissipation of the device. This operation is described

in the R4700 Microprocessor Hardware User’s Manual.

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IDT79R4700

Thermal Considerations

The RC4700 uses special packaging techniques to improve the

thermal properties of high-speed processors. The RC4700 is packaged

using cavity down packaging in a 179-pin PGA package, and a 208-lead

QFP package. These packages effectively dissipate the power of the

CPU, increasing device reliability.

The R4700 is guaranteed in a case temperature range of 0° to +85°

C. The type of package, speed (power) of the device, and airflow condi-

tions affect the equivalent ambient temperature conditions that will meet

this specification.

The equivalent allowable ambient temperature, TA, can be calculated

using the thermal resistance from case to ambient (∅CA) of the given

package. The following equation relates ambient and case tempera-

tures:

TA = TC - P * ∅CA

where P is the maximum power consumption at hot temperature,

calculated by using the maximum ICC specification for the device.

Typical values for ∅CA at various airflows are shown in Table 2:.

Revision History

January 1996: Initial draft.

March 1997: Deleted data on 150MHz speed for 5V part only.

August 1997: Upgraded 80 to 175 MHz speed specs from “Prelimi-

nary” to “Final.”

June 1999: Upgraded speed to 200MHz on 3V part specs. Package

change to DP.

June 29, 2000: Added back 175 and 200 MHz speeds.

April 10, 2001: In the Data Output category of the System Interface

Parameters tables, changed values in the Min column for all speeds

from 1.0 to 0.

∅CA

Airflow (ft/min) 0 200 400 600 800 1000

PGA 16 7 5 3 2.5 2

QFP 21 13 10 9 8 7

Table 2: Thermal Resistance (∅CA) at Various Airflows

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IDT79R4700

Mode bit Description Mode bit Description

0 reserved (must be zero) 14:13 Output driver strength

10 → 100% strength (fastest),

11 → 83% strength,

00 → 67% strength,

01 → 50% strength (slowest)

4:1 Writeback data rate

0 → ∆,

1 → DDx,

2 → DDxx,

3 → DxDx,

4 → DDxxx,

5 → DDxxxx,

6 → DxxDxx,

7 → DDxxxxxx,

8 → DxxxDxxx,

9-→ reserved

bit 15 0 → TClock[0] enabled

1 → TClock[0] disabled

7:5 Clock divisor

0 → 2,

1 → 3,

2 → 4,

3 → 5,

4 → 6,

5 → 7,

6 → 8,

7 reserved

bit 16 0 → TClock[1] enabled

1 → TClock[1] disabled

80 → Little endian,

1 → Big endian

bit 17 0 →RClock[0] enabled

1 → RClock[0] disabled

10:9 00 → R4000 compatible,

01 → reserved,

10 → pipelined writes,

11 → write re-issue

bit 18 0 → RClock[1] enabled

1 →RClock[1] disabled

11 Disable the timer interrupt on Int[5].

0 → Enabled

1 → Disabled

255:19 Reserved (must be zero)

12 reserved (must be zero)

Table 3 Boot-time Serial Mode Stream

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IDT79R4700

Figure 5 Processor Block Read

Figure 6 Processor Block Write

TClock

RClock

SysAD Addr Data0 Data1 Data2 Data3

SysCmd Read CData CData CData CEOD

ValidOut*

ValidIn*

RdRdy*

WrRdy*

Release*

TClock

RClock

SysAD Addr Data0 Data1 Data2 Data3

SysCmd

ValidOut*

ValidIn

RdRdy*

WrRdy*

Release*

Write CData CData CData CEOD

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Pin Description

The table below provides a list of interface, interrupt and miscellaneous pins that are available on the RC4700. Note that signals marked with an

asterisk are active when low. Boundary scan is not supported.

Pin Name Type Description

System Interface

ExtRqst* I External request

Signals that the system interface needs to submit an external request.

Release* O Release interface

Signals that the processor is releasing the system interface to slave state.

RdRdy* I Read Ready

Signals that an external agent can now accept a processor read.

WrRdy* I Write Ready

Signals that an external agent can now accept a processor write request.

ValidIn* I Valid Input

Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid com-

mand or data identifier on the SysCmd bus.

ValidOut* O Valid output

Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or

data identifier on the SysCmd bus.

SysAD(63:0) I/O System address/data bus

A 64-bit address and data bus for communication between the processor and an external agent.

SysADC(7:0) I/O System address/data check bus

An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.

SysCmd(8:0) I/O System command/data identifier bus

A 9-bit bus for command and data identifier transmission between the processor and an external agent.

SysCmdP I/O Reserved system command/data identifier bus parity

for the R4700 unused on input and zero on output.

Clock/Control Interface

MasterClock I Master clock

Master clock input at one half the processor operating frequency.

MasterOut O Master clock out

Master clock output aligned with MasterClock.

RClock(1:0) O Receive clocks

Two identical receive clocks at the system interface frequency.

TClock(1:0) O Transmit clocks

Two identical transmit clocks at the system interface frequency.

IOOut O Reserved for future output

Always HIGH.

IOIn I Reserved for future input

Should be driven HIGH.

SyncOut O Synchronization clock out

Must be connected to SyncIn through an interconnect that models the interconnect between MasterOut,

TClock, RClock, and the external agent.

SyncIn I Synchronization clock in

Synchronization clock input. See SyncOut.

Fault* O Fault

Always HIGH.

12 of 25 April 10, 2001

IDT79R4700

Absolute Maximum Ratings

Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

VCCPIQuiet VCC for PLL

Quiet VCC for the internal phase locked loop.

VSSPIQuiet VSS for PLL

Quiet VSS for the internal phase locked loop.

Interrupt Interface

Int*(5:0) I Interrupt

Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.

NMI* I Non-maskable interrupt

Non-maskable interrupt, ORed with bit 6 of the interrupt register.

Initialization Interface

VCCOkIVCC is OK

When asserted, this signal indicates to the R4700 that the power supply has been above the Vcc minimum

for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the reading of the

boot-time-mode-control serial stream.

ColdReset* I Cold reset

This signal must be asserted for a power on reset or a cold reset. The clocks SClock, TClock, and RClock

begin to cycle and are synchronized with the de-assertion edge of ColdReset. ColdReset must be de-

asserted synchronously with MasterOut.

Reset* I Reset

This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously

for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with

MasterOut.

ModeClock O Boot-mode clock

Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six.

ModeIn I Boot-mode data in

Serial boot-mode data input.

Symbol Rating

RV4700

3.3V±5%

R4700

5.0V±5% Unit

Commercial Commercial

VTERM Terminal Voltage with respect to GND –0.51 to +4.6

1. VIN minimum = -2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5V.

–0.51 to +7.0 V

TCOperating Temperature (case) 0 to +85 0 to +85 °C

TBIAS Case Temperature Under Bias –55 to +125 –55 to +125 °C

TSTG Storage Temperature –55 to +125 –55 to +125 °C

IIN DC Input Current 202

2. When VIN < 0.0V or VIN >VCC.

202mA

IOUT DC Output Current 50 503

3. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.

Pin Name Type Description

13 of 25 April 10, 2001
IDT79R4700
Recommended Operation Temperature and Supply Voltage
 
DC Electrical Characteristics—R4700
(Vcc = 5.0±5%, TCASE = 0°C to +85°C) 
  
Power Consumption—R4700
    
Grade Temperature GND
RV4700 R4700
VCC VCC
Commercial 0°C to +85°C (Case) 0V 3.3V±5% 5.0V±5%
Parameter R4700 80 MHz R4700 100MHz R4700 133MHz Conditions
Min Max Min Max Min Max
VOL — 0.1V — 0.1V — 0.1V |IOUT|= 20uA
VOH VCC - 0.1V — VCC - 0.1V — VCC - 0.1V —
VOL — 0.4V — 0.4V — 0.4V |IOUT|= 4mA
VOH 3.5V — 3.5V — 3.5V —
VIL –0.5V 0.8V –0.5V 0.8V –0.5V 0.8V —
VIH 2.0V VCC + 
0.5V
2.0V VCC + 
0.5V
2.0V VCC + 
0.5V
—
IIN — ±10uA — ±10uA — ±10uA 0 ≤ VIN ≤ VCC
CIN — 15pF — 15pF — 15pF —
COUT — 15pF — 15pF — 15pF —
I/OLEAK — 20uA — 20uA — 20uA Input/Output 
Leakage
Parameter
R4700 80 MHz R4700 100MHz R4700 133MHz
Conditions
Typical Max Typical1
1. Typical integer instruction mix and cache miss rates.
Max Typical1Max
System 
Condition: 80/20 MHz 100/25MHz 133/33MHz —
ICC
standby
— 150mA2
2. These are not tested. They are the result of engineering analysis and are provided for reference only.
— 175mA2— 225mA2CL = 0pF3
3. Guaranteed by design.
— 215mA2— 250mA2— 325mA2CL = 50pF
active
750mA2850 mA2875mA21000mA21175mA21300mA2CL = 0pF
No SysAd activity3
850mA21050mA2975mA21200mA21275mA21500mA2CL = 50pF 
R4x00 compatible writes
TC = 25oC
850mA21250mAa975mA21400mA4
4. These are the specifications IDT tests to insure compliance.
1275mA21675mA4CL = 50pF 
Pipelined writes or write 
re-issue 
TC = 25oC

14 of 25 April 10, 2001
IDT79R4700
AC Electrical Characteristics—R4700 
(VCC=5.0V ± 5%; TCASE = 0°C to +85°C)
Clock Parameters—R4700
    
System Interface Parameters—R4700
Note: Timings are measured from 1.5V of the clock to 1.5V of the signal.
  
Boot-Time Interface Parameters—R4700 
  
Parameter Symbol Test 
Conditions
R4700
80MHz
R4700
100MHz
R4700
133MHz Units
Min Max Min Max Min Max
MasterClock HIGH tMCHIGH Transition ≤ tMCRise 4— 4— 3 — ns
MasterClock LOW tMCLOW Transition ≤ tMCFall 4— 4— 3 — ns
MasterClock Frequency1
1.  Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled. 
——254025502567MHz
MasterClock Period tMCP —254020401540ns
Clock Jitter for MasterClock tJitterIn2
2. Guaranteed by design.
— — ±250 — ±250 — ±250 ps
Clock Jitter for 
MasterOut, SyncOut, TClock, RClock
tJitterOut2— — ±500 — ±500 — ±500 ps
MasterClock Rise Time tMCRise2——5.5—5—4ns
MasterClock Fall Time tMCFall2——5.5—5—4ns
ModeClock Period tModeCKP2— — 256*tMCP — 256*tMCP — 256*tMCP ns
JTAG Clock Period tJTAGCKP2——4*t
 MCP —4*t
 MCP —4*t
 MCP ns
SyncOut to SyncIn Delay tSync 2,3
3. Rise and fall times of the SyncIn signal must match those of MasterClock to avoid the introduction of additional clock skew.
——2*t
MCP —2*t
MCP —2*t
MCP ns
Parameter Symbol Test Conditions
R4700
80MHz
R4700 
100MHz
R4700 
133MHz Units
Min Max Min Max Min Max
Data Output tDO mode14..13 = 10 (fastest) 01
1. Guaranteed by design.
90
190
19ns
mode14..13 = 01 (slowest) 0115 0115 0112 ns
Input Data Setup tDS trise = 5ns
tfall = 5ns
3.5 — 3.5 — 3.5 — ns
Input Data Hold tDH 1.5 — 1.5 — 1.5 — ns
Parameter Symbol Test 
Conditions
R4700
80MHz
R4700
 100MHz
R4700
 133MHz Units
Min Max Min Max Min Max
Mode Data Setup tDS — 3 — 3 — 3 — Master ClockCycle
Mode Data Hold tDH — 0 — 0 — 0 — Master ClockCycle

15 of 25 April 10, 2001
IDT79R4700
Capacitive Load Deration—R4700   
  
AC Electrical Characteristics — RV4700 
(VCC=3.3V ± 5%; TCASE = 0°C to +85°C) 
Clock Parameters 
  
    
Parameter Symbol
R4700 80MHz R4700 100MHz R4700 133MHz
Units
Min Max Min Max Min Max
Load Derate CLD — 2 — 2 — 2 ns/25pF
Parameter Symbol Test 
Conditions
RV4700
100MHz
RV4700
133MHz
RV4700
150MHz Units
Min Max Min Max Min Max
MasterClock HIGH tMCHIGH Transition ≤ tMCRise/Fall 4— 3— 3 — ns
MasterClock LOW tMCLOW Transition ≤ tMCRise/Fall 4— 3— 3 — ns
MasterClock Frequency1
1. Typical integer instruction mix and cache miss rates.
—— 2550 2567 25 75 MHz
MasterClock Period tMCP — 2040 1540 13.340 ns
Clock Jitter for MasterClock tJitterIn2
2.  Guaranteed by Design.
— — ±250 — ±250 — ±250 ps
Clock Jitter for MasterOut, 
SyncOut, TClock, RClock
tJitterOut2— — ±500 — ±500 — ±500 ps
MasterClock Rise Time tMCRise2——5—4—3.5ns
MasterClock Fall Time tMCFall2——5—4—3.5ns
ModeClock Period tModeCKP — — 256*tMCP — 256*tMCP — 256*tMCP ns
SyncOut to SyncIn Delay tSync2, 3
3. Rise and fall times of the SyncIn signal must match those of MasterClock to avoid the introduction of additional clock skew.
——2*t
MCP —2*t
MCP —2*t
MCP ns
Parameter Symbol Test Conditions
RV4700
175MHz1
1. Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.
RV4700
200MHz1Units
Min Max Min Max
MasterClock HIGH tMCHIGH Transition ≤ tMCRise/Fall 3— 3— ns
MasterClock LOW tMCLOW Transition ≤ tMCRise/Fall 3— 3— ns
MasterClock Frequency2
2. Typical integer instruction mix and cache miss rates.
—— 2587.5 25100 MHz
MasterClock Period tMCP — 11.4 40 10 40 ns
Clock Jitter for MasterClock tJitterIn3
3. Guaranteed by design.
— — ±250 — ±250 ps
Clock Jitter for MasterOut, 
SyncOut, TClock, RClock
tJitterOu3— — ±500 — ±500 ps
MasterClock Rise Time tMCRise3— — 3.5 — 3.5 ns
MasterClock Fall Time tMCFall3— — 3.5 — 3.5 ns
ModeClock Period tModeCKP — — 256*tMCP — 256*tMCP ns
SyncOut to SyncIn Delay tSync 3, 4
4. Rise and fall times of the SyncIn signal must match those of MasterClock to avoid the introduction of additional clock skew.
——2*t
MCP —2*t
MCP —

16 of 25 April 10, 2001

IDT79R4700

DC Electrical Characteristics—RV4700

(VCC = 3.3±5%, TCASE = 0°C to +85°C)

Parameter

RV4700 100MHz RV4700 133MHz

Conditions

Min Max Min Max

VOL — 0.1V — 0.1V |IOUT|= 20uA

VOH VCC - 0.1V — VCC - 0.1V —

VOL — 0.4V — 0.4V |IOUT|= 4mA

VOH 2.4V — 2.4V —

VIL –0.5V 0.2VCC –0.5V 0.2VCC —

VIH 0.7VCC VCC + 0.5V 0.7VCC VCC + 0.5V —

IIN — ±10uA — ±10uA 0 ≤ VIN ≤ VCC

CIN — 15pF — 15pF —

COUT — 15pF — 15pF —

I/OLEAK — 20uA — 20uA Input/Output Leakage

Parameter

RV4700 150MHz RV4700 175MHz RV4700 200MHz

Conditions

Min Max Min Max Min Max

VOL — 0.1V — 0.1V — 0.1V |IOUT|= 20uA

VOH VCC- 0.1V — VCC - 0.1V — VCC - 0.1V —

VOL — 0.4V — 0.4V — 0.4V |IOUT|= 4mA

VOH 2.4V — 2.4V — 2.4V —

VIL –0.5V 0.2VCC –0.5V 0.2VCC –0.5V 0.2VCC —

VIH 0.7VCC VCC + 0.5V 0.7VCC VCC + 0.5V 0.7VCC VCC + 0.5V —

IIN — ±10uA — ±10uA — ±10uA 0 ≤ VIN ≤ VCC

CIN — 15pF — 15pF — 15pF —

COUT — 15pF — 15pF — 15pF —

I/OLEAK — 20uA — 20uA — 20uA Input/Output Leakage

17 of 25 April 10, 2001

IDT79R4700

System Interface Parameters—RV4700

Note: Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.

Boot-Time Interface Parameters—RV4700

Parameter Symbol Test Conditions

RV4700

100MHz

RV4700

133MHz

RV4700

150MHz Units

Min Max Min Max Min Max

Data Output1

1. Timings are measured from 1.5V of the clock to 1.5V of the signal.

tDM= Min

tDO = Max

mode14..13 = 10 (fastest)090908ns

mode14..13 = 01 (slowest) 0 15 0 12 0 12 ns

Input Data Setup tDS trise = 3ns

tfall = 3ns

3.5 — 3.5 — 3.5 — ns

Input Data Hold tDH 1.5 — 1.5 — 1.5 — ns

Parameter Symbol Test Conditions

RV4700

175MHz

RV4700

200MHz Units

Min Max Min Max

Data Output1

1. Capacitive load for all output timings is 50pF.

tDM= Min

tDO = Max

mode14..13 = 10 (fastest) 0808ns

mode14..13 = 01 (slowest) 0 12 0 12 ns

Input ata Setup tDS trise = 3ns

tfall = 3ns

3.5 — 3.5 — ns

Input Data Hold tDH 1.5 — 1.5 — ns

Parameter Symbol Test

Conditions

RV4700 100MHz RV4700 133MHz RV4700 150MHz

Units

Min Max Min Max Min Max

Mode Data Setup tDS — 3 —3 —3 —Master Clock Cycle

Mode Data Hold tDH — 0 —0 —0 —Master Clock Cycle

Parameter Symbol Test

Conditions

RV4700 175MHz RV4700 200MHz

Units

Min Max Min Max

Mode Data Setup tDS — 3 — 3 — Master Clock Cycle

Mode Data Hold tDH — 0 — 0 — Master Clock Cycle

18 of 25 April 10, 2001
IDT79R4700
Power Consumption—RV4700 
    
Parameter
RV4700 100MHz RV4700 133MHz RV4700 150MHz
Conditions
Typical1
1. Typical integer instruction mix and cache miss rates.
Max Typical1Max Typical1Max 
System 
Condition 100/25MHz 133/33MHz 150/38MHz —
ICC
standby — 125mA2
2. These are not tested. They are the result of engineering analysis and are provided for reference only.
— 175mA2— 200mA2CL = 0pF3
3. Guaranteed by design.
— 175mA2— 225mA2— 250mA2CL = 50pF
active 575mA2875mA2775mA21150mA2875mA21300mA2CL = 0pF, No SysAd activity3
650mA21100mA2850mA21375mA2950mA21550mA2CL = 50pF R4x00 compatible writes, TC = 25oC3
650mA21275mA4
4. These are the specifications IDT tests to insure compliance.
850mA21525mA4950mA21725mA2CL = 50pF  Pipelined writes or write re-issue, TC = 25oC
Parameter
RV4700 175MHz RV4700 200MHz
Conditions
Typical1
1. Typical integer instruction mix and cache miss rates.
Max Typical1Max
System Condition 175/44MHz 200/50MHz —
ICC
standby — 200mA2
2. These are not tested. They are the result of engineering analysis and are provided for reference only.
— 200mA2CL = 0pF3
3. Guaranteed by design.
— 250mA2— 250mA2CL = 50pF
active 1025mA21500mA21025mA21500mA2CL = 0pF, No SysAd activity3
1200mA21800mA21200mA21800mA2CL = 50pF R4x00 compatible writes, TC = 25oC3
1200mA22000mA4
4. These are the specifications IDT tests to insure compliance.
1200mA22000mA4CL = 50pF Pipelined writes or write re-issue, TC = 25oC

19 of 25 April 10, 2001

IDT79R4700

RC4700 QFP Package Pin-Out

Note: N.C. pins should be left floating for maximum flexibility and compatibility with future designs.

Pin Function Pin Function Pin Function Pin Function

1 N.C. 53 N.C. 105 N.C. 157 N.C.

2 N.C. 54 N.C. 106 N.C. 158 N.C.

3 VSS 55 SysCmd2 107 N.C. 159 RClock0

4 VCC 56 SysAD36 108 N.C. 160 RClock1

5 SysAD45 57 SysAD4 109 VCC 161 SyncOut

6 SysAD13 58 SysCmd1 110 VSS 162 SysAD30

7 Fault* 59 VSS 111 SysAD21 163 VCC

8 SysAD44 60 VCC 112 SysAD53 164 VSS

9 VSS 61 SysAD35 113 RdRdy* 165 SysAD62

10 VCC 62 SysAD3 114 ModeIn 166 MasterOut

11 SysAD12 63 SysCmd0 115 SysAD22 167 SysAD31

12 SysCmdP 64 SysAD34 116 SysAD54 168 SysAD63

13 SysAD43 65 VSS 117 VCC 169 VCC

14 SysAD11 66 VCC 118 VSS 170 VSS

15 VSS 67 N.C. 119 Release* 171 VCCOK

16 VCC 68 N.C. 120 SysAD23 172 SysADC3

17 SysCmd8 69 SysAD2 121 SysAD55 173 SysADC7

18 SysAD42 70 Int5* 122 NMI* 174 VCC

19 SysAD10 71 SysAD33 123 VCC 175 VSS

20 SysCmd7 72 SysAD1 124 VSS 176 N.C.

21 VSS 73 VSS 125 SysADC2 177 N.C.

22 VCC 74 VCC 126 SysADC6 178 N.C.

23 SysAD41 75 Int4* 127 VCC 179 N.C.

24 SysAD9 76 SysAD32 128 SysAD24 180 N.C.

25 SysCmd6 77 SysAD0 129 VCC 181 VCCP

26 SysAD40 78 Int3* 130 VSS 182 VSSP

27 N.C. 79 VSS 131 SysAD56 183 N.C.

28 N.C. 80 VCC 132 N.C. 184 N.C.

29 VSS 81 Int2* 133 SysAD25 185 MasterClock

30 VCC 82 SysAD16 134 SysAD57 186 VCC

31 SysAD8 83 SysAD48 135 VCC 187 VSS

32 SysCmd5 84 Int1* 136 VSS 188 SyncIn

33 SysADC4 85 VSS 137 IOOut 189 VCC

34 SysADC0 86 VCC 138 SysAD26 190 VSS

35 VSS 87 SysAD17 139 SysAD58 191 N.C.

36 VCC 88 SysAD49 140 IOIn 192 SysADC5

37 SysCmd4 89 Int0* 141 VCC 193 SysADC1

38 SysAD39 90 SysAD18 142 VSS 194 JTDI

39 SysAD7 91 VSS 143 SysAD27 195 VCC

40 SysCMD3 92 VCC 144 SysAD59 196 VSS

41 VSS 93 SysAD50 145 ColdReset* 197 SysAD47

42 VCC 94 ValidIn* 146 SysAD28 198 SysAD15

43 SysAD38 95 SysAD19 147 VCC 199 JTDO

44 SysAD6 96 SysAD51 148 VSS 200 SysAD46

45 ModeClock 97 VSS 149 SysAD60 201 VCC

46 WrRdy* 98 VCC 150 Reset* 202 VSS

47 SysAD37 99 ValidOut* 151 SysAD29 203 SysAD14

48 SysAD5 100 SysAD20 152 SysAD61 204 N.C.

49 VSS 101 SysAD52 153 VCC 205 TClock0

50 VCC 102 ExtRqst* 154 VSS 206 TClock1

51 N.C. 103 N.C. 155 N.C. 207 N.C.

52 N.C. 104 N.C. 156 N.C. 208 N.C.

20 of 25 April 10, 2001

IDT79R4700

Physical Specifications — 208-pin QFP

21 of 25 April 10, 2001

IDT79R4700

Physical Specifications - page 2

22 of 25 April 10, 2001

IDT79R4700

RC4700 PGA Package Pin-Out

Note: N.C. pins should be left floating for maximum flexibility and compatibility with future designs.

Function Pin Function Pin Function Pin

ColdReset* T14 SysAD36 C3 VCC B18

ExtRqst* U2 SysAD37 B3 VCC C1

Fault* B16 SysAD38 C6 VCC D18

Reserved O (NC) U10 SysAD39 C7 VCC F1

Reserved I (Vcc) T9 SysAD40 C10 VCC G18

IOIn T13 SysAD41 C11 VCC H1

IOOut U12 SysAD42 B13 VCC J18

Int0 N2 SysAD43 A15 VCC K1

Int1 L3 SysAD44 C15 VCC L18

Int2 K3 SysAD45 B17 VCC M1

Int3 J3 SysAD46 E17 VCC N18

Int4 H3 SysAD47 F17 VCC R1

Int5 F2 SysAD48 L2 VCC T18

MasterClock J17 SysAD49 M3 VCC U1

MasterOut P17 SysAD50 N3 VCC V3

ModeClock B4 SysAD51 R2 VCC V6

ModeIn U4 SysAD52 T3 VCC V8

NMI U7 SysAD53 U3 VCC V10

RClock0 T17 SysAD54 T6 VCC V12

RClock1 R16 SysAD55 T7 VCC V14

RdRdy* T5 SysAD56 T10 VCC V17

Release V5 SysAD57 T11 VSS A3

Reset* U16 SysAD58 U13 VSS A6

SyncIn J16 SysAD59 V15 VSS A8

SyncOut P16 SysAD60 T15 VSS A10

SysAD0 J2 SysAD61 U17 VSS A12

SysAD1 G2 SysAD62 N16 VSS A14

SysAD2 E1 SysAD63 N17 VSS A17

SysAD3 E3 SysADC0 C8 VSS A18

SysAD4 C2 SysADC1 G17 VSS B1

SysAD5 C4 SysADC2 T8 VSS C18

SysAD6 B5 SysADC3 L16 VSS D1

SysAD7 B6 SysADC4 B8 VSS F18

SysAD8 B9 SysADC5 H16 VSS G1

SysAD9 B11 SysADC6 U8 VSS H18

SysAD10 C12 SysADC7 L17 VSS J1

SysAD11 B14 SysCmd0 E2 VSS K18

SysAD12 B15 SysCmd1 D3 VSS L1

SysAD13 C16 SysCmd2 B2 VSS M18

SysAD14 D17 SysCmd3 A5 VSS N1

SysAD15 E18 SysCmd4 B7 VSS P18

SysAD16 K2 SysCmd5 C9 VSS R18

SysAD17 M2 SysCmd6 B10 VSS T1

SysAD18 P1 SysCmd7 B12 VSS U18

SysAD19 P3 SysCmd8 C13 VSS V1

SysAD20 T2 SysCmdP C14 VSS V2

23 of 25 April 10, 2001

IDT79R4700

SysAD21 T4 TClock1 C17 VSS V4

SysAD22 U5 TClock0 D16 VSS V7

SysAD23 U6 VCCOk M17 VSS V9

SysAD24 U9 ValidIn* P2 VSS V11

SysAD25 U11 ValidOut* R3 VSS V13

SysAD26 T12 WrRdy* C5 VSS V16

SysAD27 U14 VCCP K17 VSS V18

SysAD28 U15 VSSP K16 JTMS E16

SysAD29 T16 VCC A2 JTDO F16

SysAD30 R17 VCC A4 JTDI G16

SysAD31 M16 Reserved I (VCC) A7 JTCK H17

SysAD32 H2 VCC A9

SysAD33 G3 VCC A11

SysAD34 F3 VCC A13

SysAD35 D2 VCC A16

Function Pin Function Pin Function Pin

24 of 25 April 10, 2001

IDT79R4700

Physical Specifications — PGA

R4000, R4400

PC Pinout

Bottom

1 2 3 4 5 6 7 8 9 1011 1213 1415 1617 18

2884 drw 12

1 2 3 4 5 6 7 8 9 1011 1213 1415 1617 18

Bottom

R4700

Pinout

25 of 25 April 10, 2001

IDT79R4700

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

for Tech Support:

email: rischelp@idt.com

phone: 408-284-8208

The IDT logo is a trademark of Integrated Device Technology, Inc.

Ordering Information

Valid Combinations

IDT79R4700 - 80, 100, 133 - GH, DP PGA, QFP Package

IDT79RV4700 -100, 133, 150, 175, 200 - GH, DP PGA, QFP Package

Configuration

999

Speed

Package

Process/

Temperature

Range

Blank Commercial

PGA 179

208-Pin QFP

100

133

150

175

3.3V± 5%

XXXX

Device

Type

Enhanced 64-bit CPU

IDT79

100 MHz

133 MHz

150 MHz

175 MHz

4700

5.0V± 5%

80 80 MHz

(0°C to +85°C (Case))

200 200 MHz