Features
•Fast read access time – 55ns
•Low-power CMOS operation
– 100µA max standby
– 35mA max active at 5MHz
•JEDEC standard packages
– 44-lead PLCC
•Direct upgrade from 512Kbit and 1Mbit (Atmel® AT27C516 and AT27C1024)
EPROMs
•5V 10% supply
•High-reliability CMOS technology
– 2,000V ESD protection
– 200mA latchup immunity
•Rapid programming algorithm – 50µs/word (typical)
•CMOS- and TTL-compatible inputs and outputs
•Integrated product identification code
•Industrial temperature range
1. Description
The Atmel AT27C2048 is a low-power, high-performance 2,097,152-bit, one-time pro-
grammable, read-only memory (OTP EPROM) organized as 128K by 16 bits. It requires a
single 5V power supply in normal read mode operation. Any word can be accessed in less
than 55 ns, eliminating the need for speed-reducing WAIT states. The x16 organization
makes this part ideal for high-performance, 16- and 32-bit microprocessor systems.
In read mode, the AT27C2048 typically consumes 15mA. Standby mode supply current is
typically less than 10µA
The AT27C2048 is available in an industry-standard, JEDEC-approved, one-time program-
mable (OTP) PLCC package. The device features two-line control (CE, OE) to eliminate
bus contention in high-speed systems.
With high-density, 128K word storage capability, the AT27C2048 allows firmware to be
stored reliably and to be accessed by the system without the delays of mass storage media.
The AT27C2048 has additional features that ensure high quality and efficient production
use. The rapid programming algorithm reduces the time required to program the part and
guarantees reliable programming. Programming time is typically only 50 µs/word. The Inte-
grated product identification code electronically identifies the device and manufacturer. This
feature is used by industry-standard programming equipment to select the proper pro-
gramming algorithms and voltages.
2Mb (128K x 16)
One-time
Programmable,
Read-only Memory
Atmel AT27C2048
0632G–EPROM–4/11
2
0632G–EPROM–4/11
Atmel AT27C2048
2. Pin configurations
Note: Both GND pins must be
connected.
3. System considerations
Switching between active and standby conditions via the chip enable pin may produce transient voltage excursions. Unless
accommodated by the system design, these transients may exceed datasheet limits, resulting in device nonconformance.
At a minimum, a 0.1µF, high-frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the VCC and ground terminals of the device, as close to the device as possible.
Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7µF bulk electrolytic
capacitor should be utilized, again connected between the VCC and ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
Figure 3-1. Block diagram
Pin name Function
A0 - A16 Addresses
O0 - O15 Outputs
CE Chip enable
OE Output enable
PGM Program strobe
NC No connect
DC Don’t connect
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
O3
O2
O1
O0
OE
DC
A0
A1
A2
A3
A4
O13
O14
O15
CE
VPP
DC
VCC
PGM
A16
A15
A14
44-
l
ea
d
PLCC
Top view
Note: PLCC package pins 1 and 23 are “don’t
connect.”
GND
VPP
VCC DATA OUTPUTS
O0 - O15
OE, CE AND
PROGRAM LOGIC
Y DECODER
X DECODER
OUTPUT
BUFFERS
Y-GATING
CELL MATRIX
IDENTIFICATION
A0 - A17
ADDRESS
INPUTS
OE
CE
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0632G–EPROM–4/11
Atmel AT27C2048
4. Absolute maximum ratings*
Note: 1. Maximum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20ns. Maximum output pin voltage is
VCC + 0.75V DC, which may overshoot to +7.0V for pulses of less than 20ns.
5. DC and AC characteristics
Table 5-1. Operating modes
Notes: 1. X can be VIL or VIH.
2. Refer to the programming characteristics.
3. VH = 12.0 0.5V.
4. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9, which is set to VH, and A0, which is tog-
gled low (VIL) to select the manufacturer’s identification word and high (VIH) to select the device code word.
5. Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB.
Table 5-2. DC and AC operating conditions for read operation
Temperature under bias . . . . . . . . . . . . . -55C to +125C
Storage temperature . . . . . . . . . . . . . . . . -65C to +150C
Voltage on any pin with
respect to ground . . . . . . . . . . . . . . . . . . . -2.0V to +7.0V(1)
Voltage on A9 with
respect to ground . . . . . . . . . . . . . . . . . -2.0V to +14.0V(1)
VPP supply voltage with
respect to ground . . . . . . . . . . . . . . . . . . -2.0V to +14.0V(1)
*NOTICE: Stresses beyond those listed under “Absolute maximum
ratings” may cause permanent damage to the device. This
is a stress rating only, and functional operation of the
device at these or any other conditions beyond those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Mode/Pin CE OE PGM Ai VPP Outputs
Read VIL VIL X(1) Ai X(1) DOUT
Output disable X VIH X X X High Z
Standby VIH XX X X
(5) High Z
Rapid program(2) VIL VIH VIL Ai VPP DIN
PGM verify VIL VIL VIH Ai VPP DOUT
PGM inhibit VIH XX X V
PP High Z
Product identification(4) VIL VIL X
A9 = VH(3)
A0 = VIH or VIL
A1 - A16 = VIL
VCC Identification code
Atmel AT27C2048
-55 -90
Industrial operating temperature (case) -40C - 85C -40C - 85C
VCC power supply 5V 10% 5V 10%
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0632G–EPROM–4/11
Atmel AT27C2048
Table 5-3. DC and operating characteristics for read operation
Notes: 1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and
IPP..
Table 5-4. AC characteristics for read operation
Note: 2, 3, 4, 5. See the AC waveforms for read operation diagram.
Symbol Parameter Condition Min Max Units
ILI Input load current VIN = 0V to VCC 1µA
ILO Output leakage current VOUT = 0V to VCC 5µA
IPP1(2) VPP(1) read/standby current VPP = VCC 10 µA
ISB VCC(1) standby current
ISB1 (CMOS)
CE = VCC± 0.3V 100 µA
ISB2 (TTL)
CE = 2.0 to VCC + 0.5V 1mA
ICC VCC active current f = 5MHz, IOUT = 0mA, CE = VIL 35 mA
VIL Input low voltage -0.6 0.8 V
VIH Input high voltage 2.0 VCC + 0.5 V
VOL Output low voltage IOL = 2.1mA 0.4 V
VOH Output high voltage IOH = -400µA 2.4 V
Symbol Parameter Condition
Atmel AT27C2048
Units
-55 -90
Min Max Min Max
tACC(3) Address to output delay CE = OE
= VIL
55 90 ns
tCE(2) CE to output delay OE = VIL 55 90 ns
tOE(2)(3) OE to output delay CE = VIL 20 35 ns
tDF(4)(5) OE or CE high to output float, whichever occurred first 20 20 ns
tOH(4) Output hold from address, CE or OE, whichever occurred first 7 0 ns
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0632G–EPROM–4/11
Atmel AT27C2048
Figure 5-1. AC waveforms for read operation(1)
Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled, and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
Figure 5-2. Input test waveforms and measurement levels
For -55 devices only:
tR, tF < 5ns (10% to 90%)
For -90 devices:
tR, tF < 20ns (10% to 90%)
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0632G–EPROM–4/11
Atmel AT27C2048
Figure 5-3. Output test load
Note: CL = 100pF including jig capacitance, except for the -55 devices, where CL = 30pF.
Table 5-5. Pin capacitance
Note: Typical values for nominal supply voltage. This parameter is only sampled, and is not 100% tested.
Figure 5-4. Programming waveforms(1)
Notes: 1. The input timing reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device, but must be accommodated by the programmer.
3. When programming the Atmel AT27C2048, a 0.1µF capacitor is required across VPP and ground to suppress spurious volt-
age transients.
Symbol Typ Max Units Conditions
CIN 410pFV
IN = 0V
COUT 812pFV
OUT = 0V
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0632G–EPROM–4/11
Atmel AT27C2048
Table 5-6. DC programming characteristics
Table 5-7. AC programming characteristics
Notes: 1. VCC must be applied simultaneouslywithor before VPP and removed simultaneously with or after VPP.
2. This parameter is only sampled, and is not 100% tested. Output float is defined as the point where data is no longer driven.
See timing diagram.
3. Program pulse width tolerance is 50µs ± 5%.
Table 5-8. The Atmel AT27C2048 intergrated product identification code
TA = 25 5°C, VCC = 6.5 0.25V, VPP = 13.0 0.25V
Symbol Parameter Test conditions
Limits
UnitsMin Max
ILI Input load current VIN = VIL, VIH 10 µA
VIL Input low level -0.6 0.8 V
VIH Input high level 2.0 VCC + 0.5 V
VOL Output low voltage IOL = 2.1mA 0.4 V
VOH Output high voltage IOH = -400µA 2.4 V
ICC2 VCC supply current (program and verify) 50 mA
IPP2 VPP supply current CE = VIL 30 mA
VID A9 product identification voltage 11.5 12.5 V
TA = 25 5°C, VCC = 6.5 0.25V, VPP = 13.0 0.25V
Symbol Parameter Test Conditions(1)
Limits
UnitsMin Max
tAS Address setup time
Input rise and fall times
(10% to 90%) 20ns
Input pulse levels
0.45V to 2.4V
Input timing reference level
0.8V to 2.0V
Output timing reference level
0.8V to 2.0V
2µs
tOES OE setup time 2 µs
tDS Data setup time 2 µs
tAH Address hold time 0 µs
tDH Data hold time 2 µs
tDFP OE high to output float delay(2) 0 130 ns
tVPS VPP setup time 2 µs
tVCS VCC setup time 2 µs
tPW PGM program pulse width(3) 47.5 52.5 µs
tOE Data valid from OE 150 ns
tPRT
VPP pulse rise time during
programming 50 ns
Codes
Pins
Hex dataA0 O15-O8 O7 O6 O5 O4 O3 O2 O1 O0
Manufacturer 0 0 0 0 0 1 1110 001E
Device type 1 0 1 1 1 1 0111 00F7
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0632G–EPROM–4/11
Atmel AT27C2048
6. Rapid programming algorithm
A 50µs CE pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and VPP is raised to
13.0V. Each address is first programmed with one 50µs CE pulse without verification. Then a verification/reprogramming
loop is executed for each address. In the event a word fails to pass verification, up to 10 successive 50µs pulses are applied
with a verification after each pulse. If the word fails to verify after 10 pulses have been applied, the part is considered failed.
After the word verifies properly, the next address is selected until all have been checked. VPP is then lowered to 5.0V and
VCC to 5.0V. All words are read again and compared with the original data to determine if the device passes or fails.
Figure 6-1. Rapid programming algorithm
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0632G–EPROM–4/11
Atmel AT27C2048
7. Ordering Information
Green package (Pb/halide-free)
tACC
(ns)
ICC (mA)
Atmel ordering code Package Lead finish Operation rangeActive Standby
55 35 0.1 AT27C2048-55JU 44J Matte tin Industrial
(-40C to 85C)
90 35 0.1 AT27C2048-90JU 44J Matte tin Industrial
(-40C to 85C)
Package type
44J 44-lead, plastic, J-leaded chip carrier (PLCC)
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0632G–EPROM–4/11
Atmel AT27C2048
8. Packaging information
44J – PLCC
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102mm) maximum
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
E1 16.510 – 16.662 Note 2
D2/E2 14.986 – 16.002
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45° PIN NO. 1
IDENTIFIER
1.14(0.045) X 45°
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45° MAX (3X)
A
A1
B1 D2/E2
B
e
E1 E
D1
D
44J, 44-lead, Plastic J-leaded chip carrier (PLCC) B
44J
10/04/01
Package Drawing Contact:
packagedrawings@atmel.com
TITLE DRAWING NO. REV.
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0632G–EPROM–4/11
Atmel AT27C2048
9. Revision history
Doc. Rev. Date Comments
0632G 04/2011 Remove PDIP and VSOP packages
Add lead finish to ordering information
0632F 12/2007
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Fax: (+81) (3) 3523-7581
© 2011 Atmel Corporation. All rights reserved. / Rev.: 0632G–EPROM–4/11
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