FAN3850A Microphone Pre-Amplifier with Digital Output Features Description The FAN3850A integrates a pre-amplifier, LDO, and ADC that converts Electret Condenser Microphone (ECM) outputs to digital Pulse Density Modulation (PDM) data streams. The pre-amplifier accepts analog signals from the ECM and drives an over-sampled sigma delta Analog-to-Digital Converter (ADC) and outputs PDM data. The PDM digital audio has the advantage of noise rejection and easy interface to mobile handset processors. Optimized for Mobile Handset and Notebook PC Microphone Applications Accepts Input from Electret Condenser Microphones (ECM) Pulse Density Modulation (PDM) Output Standard 5-Wire Digital Interface 16dB and 19dB Gain Versions Available(1) The FAN3850A features an integrated LDO and is powered from the system supply rails up to 3.63V, with low power consumption of only 0.85mW and less than 20W in Power-Down Mode. Low Input Capacitance, High PSR, 20kHz Pre-Amplifier Low-Power 1.5A Sleep Mode Typical 470A Supply Current SNR of 62/61dB(A) for 16/19dB Gain Respectively Total Harmonic Distortion 0.02% Input Clock Frequency Range of 1-4MHz Integrated Low Drop-Out Regulator (LDO) Small 1.26mm x 0.86mm 6-Ball WLCSP Package Applications Electret Condenser Microphones with Digital Output Mobile Handset Headset Accessories Personal Computer (PC) . Ordering Information Operating Temperature Range Package Packing Method FAN3850AUC16X -30C to +85C 6 Ball, Wafer-Level Chip-Scale Package (WLCSP) 3000 Units on Tape & Reel FAN3850AUC19X -30C to +85C 6-Ball, Wafer-Level Chip-Scale Package (WLCSP) 3000 Units on Tape & Reel Part Number Note: 1. Alternate gain options are possible. Please contact Fairchild. (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 www.fairchildsemi.com FAN3850A -- Microphone Pre-Amplifier with Digital Output July 2011 VDD Sleep Mode Ctrl LDO INPUT 6' Pre-Amp CLOCK ADC DATA SELECT GND Figure 1. Block Diagram FAN3850A -- Microphone Pre-Amplifier with Digital Output Block Diagram Pin Configuration Figure 2. Pin Assignments Pin Definitions Pin# Name Type A1 CLOCK Input Clock Input B1 GND Input Ground Pin C1 DATA Output A2 SELECT Input Rising or Falling Clock Edge Select B2 INPUT Input Microphone Input C2 VDD Input Device Power Pin (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 Description PDM Output - 1 Bit ADC www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage -0.3 4.0 V VIO Analog and Digital I/O -0.3 VCC+0.3 V ESD Human Body Model, JESD22-A114, All Pins Except Microphone Input Human Body Model, JESD22-A114 - Microphone Input 7 kV 300 V Note: 2. This device is fabricated using CMOS technology and is therefore susceptible to damage from electrostatic discharges. Appropriate precautions must be taken during handling and storage of this device to prevent exposure to ESD. Reliability Information Symbol TJ Parameter Typ. Junction Temperature TSTG Storage Temperature Range TRFLW Peak Reflow Temperature 4JA Min. -65 Thermal Resistance, JEDEC Standard, Multilayer Test Boards, Still Air Max. Unit +150 C +125 C +260 C 90 FAN3850A -- Microphone Pre-Amplifier with Digital Output Absolute Maximum Ratings C/W Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. TA Operating Temperature Range -30 VDD Supply Voltage Range 1.64 tRF-CLK Clock Rise and Fall Time (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 Typ. Max. Unit +85 C 1.80 3.63 V 10 ns www.fairchildsemi.com 3 Unless otherwise specified, all limits are guaranteed for TA=25C, VDD=1.8V, VIN=94dB (SPL), and fCLK=2.4MHz. Duty Cycle=50% and CMIC=15pF. Symbol SNR eN VIN FAN3850AUC16X Parameter Min. Signal-to-Noise Ratio fIN=1kHz (1Pa), A-Weighted Total Input RMS Noise(4) 20Hz to 20kHz, A-Weighted Maximum Input Signal fIN=1kHz, THD+N < 10%, Level=0V Typ. FAN3850AUC19X Max. Min. 62 5.74 Typ. Max. 61 6.80 4.45 448 Unit dB(A) 5.30 VRMS 317 mVPP Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TA=25C, VDD=1.8V, VIN=94dB (SPL), and fCLK=2.4MHz. Duty Cycle=50% and CMIC=15pF. Symbol Parameter Condition Min. Typ. Max. Unit 1.64 1.80 3.63 V VDD Supply Voltage Range IDD Supply Current INPUT=AC Coupled to GND, CLOCK=On, No Load 470 Sleep Mode Current fCLK=GND 1.5 PSR Power Supply Rejection(4) INPUT=AC Coupled to GND, Test Signal on VDD=217Hz Square Wave and Broadband Noise(3), Both 100mVP-P -74 dBFS INNOM Nominal Sensitivity INPUT=94dBSPL (1Pa) -26 dBFS ISLEEP THD THD+N CIN (5) (6) Total Harmonic Distortion THD and Noise(4) (7) Input Capacitance (7) RIN Input Resistance VIL CLOCK & SELECT Input Logic LOW Level VIH CLOCK & SELECT Input Logic HIGH Level VOL Data Output Logic LOW Level VOH Data Output Logic HIGH Level VOUT Acoustic Overload Point 8.0 fIN=1kHz, INPUT=-26dBFS 0.02 0.20 50Hz fIN 1kHz, INPUT=-20dBFS 0.2 1.0 fIN=1kHz, INPUT=-5dBFS 1.0 5.0 fIN=1kHz, INPUT=0dBFS 5.0 10.0 INPUT 0.2 INPUT (7) A A % % pF >100 1.5 THD < 10% FAN3850A -- Microphone Pre-Amplifier with Digital Output Device Specific Electrical Characteristics G 0.3 V VDD+0.3 V 0.35*VDD V 0.65*VDD V 120 dBSPL Continued on the following page... (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 www.fairchildsemi.com 4 Unless otherwise specified, all limits are guaranteed for TA=25C, VDD=1.8V, VIN=94dB(SPL), and fCLK=2.4MHz. Duty Cycle=50% and CMIC=15pF. Symbol Parameter Condition Min. Typ. Max. Unit tA Time from CLOCK Transition to Data becoming Valid On Falling Edge of CLOCK, SELECT=GND, CLOAD=15pF 18 43 tB Time from CLOCK Transition to Data becoming HIGH-Z On Rising Edge of CLOCK, SELECT=GND, CLOAD=15pF 0 5 tA Time from CLOCK Transition to Data becoming Valid On Rising Edge of CLOCK, SELECT=VDD, CLOAD=15pF 18 56 tB Time from CLOCK Transition to Data becoming HIGH-Z On Falling Edge of CLOCK, SELECT=VDD, CLOAD=15pF 0 5 16 ns 1.0 2.4 4.0 MHz 40 50 60 % 0.35 2.00 ms 0.01 1.00 ms 100 pF fCLK CLKdc tWAKEUP tFALLASLEEP CLOAD (8) Input CLOCK Frequency Active Mode (4) CLOCK Duty Cycle (9) Wake-Up Time fCLK=2.4MHz (10) Fall-Asleep Time fCLK=2.4MHz 0 Load Capacitance on Data Notes: 3. Pseudo-random noise with triangular probability density function. Bandwidth up to 10MHz. 4. Guaranteed by characterization. 5. Assuming that 120dB(SPL) is mapped to 0dBFS. 6. Assuming an input of -45dBV 7. Guaranteed by design. 8. All parameters are tested at 2.4MHz. Frequency range guaranteed by characterization. 9. Device wakes up when fCLK 300kHz. 10. Device falls asleep when fCLK 70kHz. ns 16 ns ns FAN3850A -- Microphone Pre-Amplifier with Digital Output Electrical Characteristics (Continued) Figure 3. Interface Timing (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 www.fairchildsemi.com 5 Unless otherwise specified, all limits are guaranteed for TA=25C, VDD=1.8V, VIN=94dB(SPL), fCLK=2.4MHz, and duty cycle=50%. Amplitude Spectrum [dBFS], Fo = 1000.2135 Hz, Fs = 2.400000 MHz, SNR = 56.89 dB, SNR = 60.88 dB(A), THD = 0.008 % Noise Noise(A) Signal -20 m Fo(0)= -26.15 dBFS THD = 81.95 dB SNR = 60.88 dBc(A) SINAD = 56.87 dB ENOB = 13.50 N = 2097152 pts Blackman Window -40 Amplitude [dBFS] -60 -80 p Integrated Noise = -87.03 dBFS(A) p Spur = -101.34 dBFS, SFDR = 75.19 dBc -100 m Fo(1)= -110.28 dBFS m Fo(2)= -116.40 dBFS -120 m Fo(3)= -120.45 dBFS m Fo(4)= -125.03 dBFS -140 -160 1 10 2 3 10 10 4 10 5 10 Frequency [Hz] 6 10 FAN3850A -- Microphone Pre-Amplifier with Digital Output Typical Performance Characteristics Filename: fan3850a-1-BD92M-20110125T122914.dat Figure 4. Noise vs. Frequency Figure 5. THD, SINDA, and SNR vs. Input Amplitude (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 www.fairchildsemi.com 6 FAN3850A -- Microphone Pre-Amplifier with Digital Output Typical Performance Characteristics (Continued) Figure 6. THD, SINAD, and SNR vs. Output Level 4 Del ta (dB) 0.1971 0.1644 0.1260 0.0954 0.0657 0.0359 0.0139 0.0000 0.0097 0.0344 0.0514 0.0739 0.0998 0.1183 0.1271 3 2 Gain(dB) Temp(C) 40 30 20 10 0 10 20 25 30 40 50 60 70 80 85 1 0 1 2 3 4 40 30 20 10 0 10 20 30 40 50 60 70 80 JunctionTemperatureTjC Figure 7. Gain vs. Temperature (Nominal Temperature= 25C) (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 www.fairchildsemi.com 7 VDD Audio Output SPEAKER CLOCK INPUT PreAmp ADC DATA SELECT CLK SDI SDO L/R Serial Port Noise Shaper Low Pass Filter Decimation Interpolation Applications Software Figure 8. Mono Microphone Application Circuit VDD Audio Output FAN3850A -- Microphone Pre-Amplifier with Digital Output Applications Information SPEAKER CLOCK INPUT PreAmp ADC DATA SELECT CLK SDI SDO L/R Serial Port Noise Shaper Low Pass Filter Decimation VDD Interpolation CLOCK Applications Software INPUT PreAmp ADC DATA SELECT Figure 9. Stereo Microphone Application Circuit (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 www.fairchildsemi.com 8 Electret Diaphragm Airgap Backplate INPUT FAN3850A VDD CLOCK DATA SELECT GND Figure 10. MIC Element Drawing A 0.1F decoupling capacitor is required for VDD. It can be located inside the microphone or on the PCB very close to the VDD pin. A 100 resistance is recommended on the clock output of the device driving the FAN3850A to minimize ringing and improve signal integrity. Due to high input impedance, care should be taken to remove all flux used during the reflow soldering process. For optimal PSR, route a trace to the VDD pin. Do not place a VDD plane under the device. (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 FAN3850A -- Microphone Pre-Amplifier with Digital Output Applications Information (Continued) www.fairchildsemi.com 9 F 0.03 C E 2X A 0.570 A1 B (O0.120) CU PAD 0.485 PIN A1 AREA D (O0.220) SOLDER MASK 0.03 C 2X TOP VIEW RECOMMENDED LAND PATTERN (NSMD) 0.06 C 0.01 C 0.300 0.254 C 0.1970.013 0.0800.010 E SEATING D PLANE SIDE VIEWS NOTES: 0.005 0.570 C A B O0.1200.010 6X C 0.485 B (Y) +/-0.018 A 1 2 F (X) +/-0.018 BOTTOM VIEW A. NO JEDEC REGISTRATION APPLIES. FAN3850A -- Microphone Pre-Amplifier with Digital Output Physical Dimensions B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. DATUM C, THE SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. E. PACKAGE TYPICAL HEIGHT IS 273 MICRONS 23 MICRONS (254-300 MICRONS). F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. G. DRAWING FILENAME: UC006AHrev3. Figure 11. 6-Ball, Wafer-Level Chip-Scale Package (WLCSP) FAN3850A External Product Dimensions Product ID D E X Y All options 1.260mm 0.860mm 0.145mm 0.145mm Ball Composition: SN97.5-Ag2.5 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent version. Package specifications do not expand Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent packaging drawings and tape and reel specifications. http://www.fairchildsemi.com/packaging/. (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 www.fairchildsemi.com 10 FAN3850A -- Microphone Pre-Amplifier with Digital Output (c) 2010 Fairchild Semiconductor Corporation FAN3850A * Rev. 3.0.6 www.fairchildsemi.com 11