July 2011
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6
FAN3850A — Microphone Pre-Amplifier with Digital Output
FAN3850A
Microphone Pre-Amplifier with Digital Output
Features
Optimized for Mobile Handset and Notebook PC
Microphone Applications
Accepts Input from Electret Condenser
Microphones (ECM)
Pulse Density Modulation (PDM) Output
Standard 5-Wire Digital Interface
16dB and 19dB Gain Versions Available(1)
Low Input Capacitance, High PSR, 20kHz
Pre-Amplifier
Low-Power 1.5μA Sleep Mode
Typical 470μA Supply Current
SNR of 62/61dB(A) for 16/19dB Gain Respectively
Total Harmonic Distortion 0.02%
Input Clock Frequency Range of 1-4MHz
Integrated Low Drop-Out Regulator (LDO)
Small 1.26mm x 0.86mm 6-Ball WLCSP Package
Description
The FAN3850A integrates a pre-amplifier, LDO, and
ADC that converts Electret Condenser Microphone
(ECM) outputs to digital Pulse Density Modulation
(PDM) data streams. The pre-amplifier accepts analog
signals from the ECM and drives an over-sampled
sigma delta Analog-to-Digital Converter (ADC) and
outputs PDM data. The PDM digital audio has the
advantage of noise rejection and easy interface to
mobile handset processors.
The FAN3850A features an integrated LDO and is
powered from the system supply rails up to 3.63V, with
low power consumption of only 0.85mW and less than
20W in Power-Down Mode.
Applications
Electret Condenser Microphones with Digital Output
Mobile Handset
Headset Accessories
Personal Computer (PC)
.
Ordering Information
Part Number
Operating
Temperature
Range
Package Packing
Method
FAN3850AUC16X -30°C to +85°C 6 Ball, Wafer-Level Chip-Scale Package (WLCSP) 3000 Units on
Tape & Reel
FAN3850AUC19X -30°C to +85°C 6-Ball, Wafer-Level Chip-Scale Package (WLCSP) 3000 Units on
Tape & Reel
Note:
1. Alternate gain options are possible. Please contact Fairchild.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6 2
FAN3850A — Microphone Pre-Amplifier with Digital Output
Block Diagram
Figure 1. Block Diagram
Pin Configuration
Figure 2. Pin Assignments
Pin Definitions
Pin# Name Type Description
A1 CLOCK Input Clock Input
B1 GND Input Ground Pin
C1 DATA Output PDM Output – 1 Bit ADC
A2 SELECT Input Rising or Falling Clock Edge Select
B2 INPUT Input Microphone Input
C2 VDD Input Device Power Pin
LDO
Pre-Amp 6'
ADC
INPUT
Sleep
Mode Ctrl
DATA
SELECT
CLOCK
VDD
GND
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6 3
FAN3850A — Microphone Pre-Amplifier with Digital Output
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VDD DC Supply Voltage -0.3 4.0 V
VIO Analog and Digital I/O -0.3 VCC+0.3 V
ESD
Human Body Model, JESD22-A114, All Pins Except
Microphone Input ±7 kV
Human Body Model, JESD22-A114 – Microphone Input ±300 V
Note:
2. This device is fabricated using CMOS technology and is therefore susceptible to damage from electrostatic
discharges. Appropriate precautions must be taken during handling and storage of this device to prevent
exposure to ESD.
Reliability Information
Symbol Parameter Min. Typ. Max. Unit
TJ Junction Temperature +150 °C
TSTG Storage Temperature Range -65 +125 °C
TRFLW Peak Reflow Temperature +260 °C
4JA Thermal Resistance, JEDEC Standard,
Multilayer Test Boards, Still Air 90 °C/W
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Min. Typ. Max. Unit
TA Operating Temperature Range -30 +85 °C
VDD Supply Voltage Range 1.64 1.80 3.63 V
tRF-CLK Clock Rise and Fall Time 10 ns
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6 4
FAN3850A — Microphone Pre-Amplifier with Digital Output
Device Specific Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB (SPL), and fCLK=2.4MHz.
Duty Cycle=50% and CMIC=15pF.
Symbol Parameter FAN3850AUC16X FAN3850AUC19X Unit
Min. Typ. Max. Min. Typ. Max.
SNR Signal-to-Noise Ratio
fIN=1kHz (1Pa), A-Weighted 62 61 dB(A)
eN Total Input RMS Noise(4)
20Hz to 20kHz, A-Weighted 5.74 6.80 4.45 5.30 μVRMS
VIN Maximum Input Signal
fIN=1kHz, THD+N < 10%, Level=0V 448 317 mVPP
Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB (SPL), and fCLK=2.4MHz.
Duty Cycle=50% and CMIC=15pF.
Symbol Parameter Condition Min. Typ. Max. Unit
VDD Supply Voltage Range 1.64 1.80 3.63 V
IDD Supply Current INPUT=AC Coupled to GND,
CLOCK=On, No Load 470 A
ISLEEP Sleep Mode Current fCLK=GND 1.5 8.0 A
PSR Power Supply Rejection(4)
INPUT=AC Coupled to GND,
Test Signal on VDD=217Hz
Square Wave and
Broadband Noise(3), Both
100mVP-P
-74 dBFS
INNOM Nominal Sensitivity(5) INPUT=94dBSPL (1Pa)
-26 dBFS
THD Total Harmonic Distortion(6) f
IN=1kHz, INPUT=-26dBFS 0.02 0.20 %
THD+N THD and Noise(4)
50Hz  fIN  1kHz,
INPUT=-20dBFS 0.2 1.0
%
fIN=1kHz, INPUT=-5dBFS 1.0 5.0
fIN=1kHz, INPUT=0dBFS 5.0 10.0
CIN Input Capacitance(7) INPUT
0.2 pF
RIN Input Resistance(7) INPUT >100 G
VIL CLOCK & SELECT Input
Logic LOW Level
0.3 V
VIH CLOCK & SELECT Input
Logic HIGH Level 1.5 V
DD+0.3 V
VOL Data Output Logic LOW
Level
0.35*VDD V
VOH Data Output Logic HIGH
Level 0.65*VDD
V
VOUT Acoustic Overload Point(7) THD < 10% 120
dBSPL
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6 5
FAN3850A — Microphone Pre-Amplifier with Digital Output
Electrical Characteristics (Continued)
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB(SPL), and fCLK=2.4MHz.
Duty Cycle=50% and CMIC=15pF.
Symbol Parameter Condition Min. Typ. Max. Unit
tA Time from CLOCK Transition
to Data becoming Valid
On Falling Edge of CLOCK,
SELECT=GND, CLOAD=15pF 18 43 ns
tB Time from CLOCK Transition
to Data becoming HIGH-Z
On Rising Edge of CLOCK,
SELECT=GND, CLOAD=15pF 0 5 16
ns
tA Time from CLOCK Transition
to Data becoming Valid
On Rising Edge of CLOCK,
SELECT=VDD, CLOAD=15pF 18 56 ns
tB Time from CLOCK Transition
to Data becoming HIGH-Z
On Falling Edge of CLOCK,
SELECT=VDD, CLOAD=15pF 0 5 16
ns
fCLK Input CLOCK Frequency(8) Active Mode 1.0 2.4 4.0 MHz
CLKdc CLOCK Duty Cycle(4) 40 50 60 %
tWAKEUP Wake-Up Time(9) f
CLK=2.4MHz 0.35 2.00 ms
tFALLASLEEP Fall-Asleep Time(10) f
CLK=2.4MHz 0 0.01 1.00 ms
CLOAD Load Capacitance on Data 100 pF
Notes:
3. Pseudo-random noise with triangular probability density function. Bandwidth up to 10MHz.
4. Guaranteed by characterization.
5. Assuming that 120dB(SPL) is mapped to 0dBFS.
6. Assuming an input of -45dBV
7. Guaranteed by design.
8. All parameters are tested at 2.4MHz. Frequency range guaranteed by characterization.
9. Device wakes up when fCLK  300kHz.
10. Device falls asleep when fCLK  70kHz.
Figure 3. Interface Timing
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6 6
FAN3850A — Microphone Pre-Amplifier with Digital Output
Typical Performance Characteristics
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB(SPL), fCLK=2.4MHz, and duty
cycle=50%.
Figure 4. Noise vs. Frequency
Figure 5. THD, SINDA, and SNR vs. Input Amplitude
10
1
10
2
10
3
10
4
10
5
10
6
-160
-140
-120
-100
-80
-60
-40
-20
Frequency [Hz]
Amplitude [dBFS]
Amplitude Spectrum [dBFS], Fo = 1000.2135 Hz, Fs = 2.400000 MHz, SNR = 56.89 dB, SNR = 60.88 dB(A), THD = 0.008 %
m
Fo(0)= -26.15 dBFS
m
Fo(1)= -110.28 dBFS
m
Fo(2)= -116.40 dB FS
m
Fo(3)= -120.45 dBFS
m
Fo(4)= -125.03 dBFS
p
Integrat ed Noise = -87.03 dBFS(A)
p
Spur = -101.34 dBFS, SFDR = 75.19 dBc
Noise
Noise(A)
Signal
Filename: fan3850a-1-BD9
2
M-20110125T122914.dat
THD = 81.95 dB
SNR = 60.88 dBc(A)
SINAD = 56.87 dB
ENOB = 13.50
N = 2097152 pts
Blackman Window
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6 7
FAN3850A — Microphone Pre-Amplifier with Digital Output
Typical Performance Characteristics (Continued)
Figure 6. THD, SINAD, and SNR vs. Output Level
Figure 7.  Gain vs. Temperature (Nominal Temperature= 25°C)
Temp(C) Delta(dB)
40 0.1971
30 0.1644
20 0.1260
10 0.0954
0 0.0657
10 0.0359
20 0.0139
25 0.0000
30 0.0097
40 0.0344
50 0.0514
60 0.0739
70 0.0998
80 0.1183
85 0.1271
403020100 1020304050607080
4
3
2
1
0
1
2
3
4
JunctionTemperatureTjC
Gain(dB)
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6 8
FAN3850A — Microphone Pre-Amplifier with Digital Output
Applications Information
Figure 8. Mono Microphone Application Circuit
Figure 9. Stereo Microphone Application Circuit
L/R
Decimation
VDD
Interpolation
SELECT
SPEAKER
Applications Software
ADC
SELECT
CLK
Pre-
Amp
SDI
ADC
INPUT
SDO
Pre-
Amp
DATA
INPUT
CLOCK
VDD
Serial Port
CLOCK
Audio
Output
DATA
Low Pass Filter Noise Shaper
Decimation
Noise Shaper
Low Pass Filter
INPUT
Serial Port
CLK
Pre-
Amp
Applications Software
ADC
Interpolation
CLOCK
SDI
DATA
SPEAKER
VDD
SELECT
SDO
Audio
Output
L/R
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6 9
FAN3850A — Microphone Pre-Amplifier with Digital Output
Applications Information (Continued)

Diaphragm
Backplate
A
irgap
Electre
t
FAN3850A
INPUT
CLOCK
DATA
SELECT
V
DD
GND
Figure 10. MIC Element Drawing
A 0.1μF decoupling capacitor is required for VDD. It can
be located inside the microphone or on the PCB very
close to the VDD pin.
Due to high input impedance, care should be taken to
remove all flux used during the reflow soldering process.
A 100 resistance is recommended on the clock output
of the device driving the FAN3850A to minimize ringing
and improve signal integrity.
For optimal PSR, route a trace to the VDD pin. Do not
place a VDD plane under the device.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6 10
FAN3850A — Microphone Pre-Amplifier with Digital Output
Physical Dimensions
Figure 11. 6-Ball, Wafer-Level Chip-Scale Package (WLCSP)
FAN3850A External Product Dimensions
Product ID D E X Y
All options 1.260mm 0.860mm 0.145mm 0.145mm
Ball Composition: SN97.5-Ag2.5
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent version. Package specifications do not expand Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent packaging drawings and tape and reel
specifications. http://www.fairchildsemi.com/packaging/.
BOTTOM VIEW
TOP VIEW
12
A
B
C
6X
0.005 C
A
B
(X) +/-0.018
(Y) +/-0.018
Ø0.120±0.010
F
E
D
B
A
PIN A1
A
REA
F
2X
2X
(Ø0.120)
CU PAD
SIDE VIEWS
0.06 C
D
CSEATING
PLANE
0.03 C
0.03 C
NOTES:
A
. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. DATUM C, THE SEATING PLANE IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
E. PACKAGE TYPICAL HEIGHT IS 273 MICRONS
±23 MICRONS (254-300 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILENAME: UC006AHrev3.
E0.080±0.010
0.570
0.485
0.197±0.013
0.300
0.254
0.570
0.485
RECOMMENDED LAND
PATTERN (NSMD)
(Ø0.220)
SOLDER MASK
A
1
0.01 C
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3850A • Rev. 3.0.6 11
FAN3850A — Microphone Pre-Amplifier with Digital Output