Integrated Device Technology, Inc. CMOS ASYNCHRONOUS FIFO dt 256 x 9,512 x9, 1K x9 IDT7200L IDT7201LA IDT7202LA FEATURES: * First-In/First-Out dual-port memory * 256 x 9 organization (IDT7200) * 512 x 9 organization (IDT7201) * 1K x 9 organization (IDT7202) Low power consumption Active: 770mW (max.) Power-down: 2.75mW (max.) Ultra high speed12ns access time Asynchronous and simultaneous read and write Fully expandable by both word depth and/or bit width Pin and functionally compatible with 720X family Status Flags: Empty, Half-Full, Full Auto-retransmit capability High-performance CEMOS technology Military product compliant to MIL-STD-883, Class B Standard Military Drawing #5962-87531, 5962-89666, 5962-89863 and 5962-89536 are listed on this function. DESCRIPTION: The IDT7200/7201/7202 are dual-port memories that load and empty data on a first-in/first-out basis. The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. The devices utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. It also features a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed low to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. The IDT7200/7201/7202 are fabricated using !DTs high- speed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/ writes in multiprocessing and rate buffer applications. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM OAL Ney TS < WRITE W "| CONTROL TOOT To os q $ e WRITE KN RAM READ POINTER [1] ARRAY POINTER 256 x9 qj 512 x9 1024x9 e LUT Lo LTT THREE- . a STATE _ BUFFERS * \7 s DATA OUTPUTS Ale] _ READ ors) RESET CONTROL || [ >! LOGIC 4 v j FLAG - am LOGIC ~ EE FURT _ EXPANSION |* Xl *| LoGi ~__* XO/HF 2679 drw 01 The IDT logo 1s a trademark of integraled Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 11996 Integrated Devica Technology, Inc. DECEMBER 1995 DSC-267941 5.24 110T7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9,512 x9and1Kx9 PIN CONFIGURATIONS MILITARY AND COMMERCIAL TEMPERATURE RANGES INDEX 8a&es Q Sas 7 \ Ww q t 28 [J vec De 2 27 {_] Ds 32 31 30 ps [| 3 26 [_] Ds , De be [J 4 25 |_] De " 07 bi ])s5 284, 24(-] Do Ne Dolje fees 23] FUAT xi FURT Ki f_]7 Deas) 22[ 1 BS FF RS FF |s = &8?, a CF Qo EF Qo [] 9 20 [_] XG/HF Q1 XO/HF a: [_] 10 19 |_] a . ar 2 Q6 ora 18 [|_] Qs 14 15 16 17 18 19 20 Q3 (] 12 17 [J as Qs [_] 13 16 |__] Qa = 2 epaglt x @np [_} 14 15 [I R o9 5 = oo 2679 rw 2b 2679 drw O2a DIP/SOIC/CERPACK LCC/PLCC TOP VIEW TOP VIEW NOTE: NOTE: 1. CERPACK (E28-2) and 600-mil-wide DIP (P28-1 andD28-1)notavailable 1. LCC (L32-1) not available for 7200. for 7200. 1 RECOMMENDED DC OPERATING ABSOLUTE MAXIMUM RATINGS") CONDITIONS Symbol Rating Com't. Nil. Unit Symbol Parameter Min. | Typ. | Max. | Unit VTERM | Terminal Voltage 0.5 to +7.0|-0.5to+7.0] V Vocm Military Supply 45 5.0 5.5 Vv with Respect Voitage to GND , Vcc Cc jal Suppl 4. 0 5.5 Vv TA Operating Oto+70 | -55to +125] C cee Voltage PPy 8 Temperature ; Vv TBIAS Temperature 55 to +125] -65 to +135] C GND Supply Voltage o o Under Bias Vint!) Input High Voltage | 2.0 v Tsta | Storage 55 to +125| 65 to +155| C Commercial Temperature vin) Input High Voltage | 2.2 v lout DC Output 50 50 mA Mlitary Current vi 2) Input Low Voltage 0.8 Vv NOTE: 2679 tbl 01 Commercial and 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS Military may cause permanent damage to the device. This is a stress rating only worTe: 2679 thi 03 and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specitication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. CAPACITANCE (Ta = +25C, f = 1.0 MHz) 1. Vit = 2.6 for XI input (commercial). Vin = 2.8V for XI input (military). 2. 1.5V undershoots are allowed for 10ns once per cycle. Symbol Parameter) Condition Max. | Unit CIN Input Capacitance VIN = OV 8 pF CouT Output Capacitance | VouT = 0V 8 pF NOTE: 2679 Ibi 02 1. This parameter is sampled and not 100% tested. 5.24 2IDT7200/7201 A/7202A CMOS ASYNCHRONOUS FIFO 256 x 8, 512 x9 and 1K x9 DC ELECTRICAL CHARACTERISTICS (Commercial: Vcc = 5.0V10%, Ta = 0C to +70C; Military: VCC = 5.0V+10%, TA = -55C to +125C) MILITARY AND COMMERCIAL TEMPERATURE RANGES (DT7200L IDT7200L IDT7200L IDT7201LA IOT7201LA IDT7201LA IDT7202LA IDT7202LA IDT7202LA Commercial Milltary Commercial ta = 12, 15, 20 ns ta =20 ns ta = 25, 35 ns Symbol Parameter Min. | Typ. | Max. | Min. | Typ. | Max. | Min. | Typ. | Max. | Unit i) Input Leakage Current (Any Input) =-1 1 | -10 | 10 | -1 |] 1 [pa Lo Output Leakage Current -10/ | 10 | -10 | 10 | -1o[ | 10 | pA VOH Output Logic 1 Voltage lon =-2mA 2.4 2.4 _ 2.4 _ Vv VoL Output Logic 0 Voltage lo. = 8mA _ 0.4 0.4 | 04 Vv Icc1! Active Power Supply Current 125") [14087 4125 | mA Icca) Standby Current (R=W=RS=FL/RT=Vin) _ _ 15 _ 20 _ | 15 [mA Icca(L)' | Power Down Current (All Input = Vcc - 0.2V) | 05 _ 0.9 [05 [mA NOTES: 2670 tl 08 1. Measurements with 0.4 < VIN < Vcc. 2, R> Vin, 0.4 < Vout s Vec. 3. Icc measurements are made with outputs open (only capacitive loading). 4. Tested at f = 20MHz. DC ELECTRICAL CHARACTERISTICS (Continued) (Commercial: Vcc = 5.0V410%, TA = 0C to +70C; Military: Vcc = 5.0V+10%, TA = -55C to +125C) IDT7200L IDT?7200L IDT7200L IDT7201LA IDT7201LA IDT7201LA IDT7202LA IDT7202LA IDT7202LA Military Commercial Military ta = 30, 40 ns ta=50ns ta = 50, 65, 80, 120 ns Symbol Parameter Min. | Typ. |Max.| Min.| Typ. | Max.| Min. | Typ. | Max. /Unit i) Input Leakage Current (Any Input) ~10/ | 10] -1 | [1 -10 | | 10 [yA ILo!*) Output Leakage Current -10] | 10 | -10/ | 10] -10 | | 10 [ya VOH Output Logic 1 Voltage oH = ~2mA 2.4 _ 2.4 _ 2.4 - Vv VoL Output Logic 0 Voltage lol = 8mA _ _ 0.4 _ | 04 _ _ 0.4 Vv icc} Active Power Supply Current _ |140) 50 | 80 _ 70 100 | mA Ieca?) Standby Current (R=W=RS=FL/RT=Vin) | | 20 5 8 8 15 [mA Icca(L) | Power Down Current (All Input = Voc - 0.2V) _ |os | 05 0.9 [mA NOTES: 2679 tbl O& 1. Measurements with 0.4 < VIN < Vcc. 2. Re Vin, 0.4 < Vout < Voc. 3. icc measurements are made with outputs open (only capacitive Joading). 4. Tested at t = 20MHz. $.24 3IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x9, 512 x 9and 1K x9 MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: Vcc = 5.0V+10%, TA = 0C to +70C; Military: Vcc = 5.0V+10%, TA = 55C to +125C) , Commercial Com & Mi} Com't Military Com'l 7200L12 | 7200L15 | 7200L20 | 7200L25 | 7200L30 7200L35 7201LA12 {7201LA15 | 7201LA20 | 7201LA25 | 7201LA30 | 7201LA35 7202LA12 |7202LA15 | 7202LA20 | 7202LA25 | 7202LA30 | 7202LA35 Symbol] Parameter Min.| Max. | Min.| Max.| Min.| Max.| Min. | Max. | Min. | Max.) Min. | Max.| Unit ts Shift Frequency | 50) ]|] 40] |] 333] ~ | 285] 25 | 22.2) MHz tRC Read Cycle Time 20; | 25] ] 30] ~ | 35] 40 _ 45 |] ns tA Access Time | 12] ] 15) |] 20 | |] 25 _ 30 35 | ns tar Read Recovery Time 8 | ] to} ] 10} |] 107 {| 10] 10 | ]|aAs trew | Read Pulse Width?) 12} | 15} | 20| | 2] | 30} ] 35 | ] ns {RUZ Read Pulse Low to Data Bus at Low 2) 3/]5/}] 5}/]5]/]5]| 5 | | os twiz | Write Pulse High to Data Bus atLowZ@- 4] 39] ] 5/] 5/]5]/]5 ]] to] ] ns tov Data Valid from Read Pulse High 5|]| 5] ]}] 5] ] 5] 5 = 5 [ns tRHz | Read Pulse High to Data Bus at High Z) | | 12 | ] 16] ] 15] ] 18 | ] 20] | 20] ns twe Write Cycle Time 20] | 25{ ]}] 30] ]}] 35] | 40] | 45 | | ns iwew | Write Pulse Width?) 12] 415] ] 20] | 25] | 30] ] 35 | | ns twR Write Recovery Time 8 | 10} |] 107; ] 10] 10 10 |ons tps Data Set-up Time 9 ]ui} ] 2) ] 6] 18 _ 18 | ns {DH Data Hold Time 0 - 0 - 0 _ 0 _ 0 _ 0 | ns tRSc Reset Cycle Time 20}; |] 25] ]| 30] | 35] | 40] ] 45 | ] ns tRs Reset Pulse Width?) 12] | 15} ] 20] | 25{ | 30] ] 35 | | ns trss__| Reset Set-up Time) 12) ] 15] | 20] ] 25] | 30] ] 35 | ] ns tRSR Reset Recovery Time 8 |10/ ] 10] |] 107 10] 10 | | ns trTc Retransmit Cycle Time 20] 12 | ] 25] ] 30 | | 35 _ 40 _ 45 | ns tat Retransmit Pulse Width?) i2| ~ | 15| ~] 20] | 25| | 30] ] 35 | | ns taTS Retransmit Set-up Time) 12] ] 1S} ]}] 20]; |] 2b] 30 ~ 35 | ns taTA Retransmit Recovery Time 8 |10} ] 10] | 10] 10] 10 |ons teFL Reset to Empty Flag Low ] 12] ] 2] ] 30] ] 35 _ 40 _ 45 | ns tHFH,FFH] Reset to Half-Full and Full Flag High | 17] ] 25] ] 30] |] 35 - 40 _ 45 | ns tRTF Retransmit Low to Flags Valid ] 20] ] 25] ] 30 | ] 35 | ] 40] | 45] ns tREF Read Low to Empty Flag Low |] 12] ] 15] ] 20] ] 2 | 30 _ 30 | ns iGlag Read High to Full Flag High |] 14]/] 15] ]|] 20 | ] 25 | ] 30] | 30] ns tAPE Read Pulse Width after EF High 12; ]|] 15] ] 20] | 257 30 _ 35 [ons {WEF Write High to Empty Flag High |] 12]>-|] 15], |] 20] ] 256 _ 30 _ 30 | ns {WFF Write Low to Fuil Flag Low | 147] 15] ] 20 | ] 25 _ 30 _ 30 | ns {WHF Write Low to Half-Full Flag Low |] 177 ] 27] ] 30} ] 35 _ 40 _ 45 | ns tRHF Read High to Half-Full Flag High | 17] ] 25] ] 30] ] 35 J 40 | 45] ns twPF Write Pulse Width after FF High 2], ]}] 16) ] 20] J] 2b] 30 _ 35 ]oons tXOL Read/Mrite to KO Low ]} 2])]]|] 15, ]|] 20] ] 2] 30 _ 35 | ns ixoH | Read/Write to XO High | 12/] 1/ ]| 20 | | 25 | ]| 30] |] 35] ns tx! XI Pulse Width? i2| |] 15] ]| 20] | 25] | 30] ] 35 | | ns txIR XI Recovery Time 8 | ]10/ }| 10] | 10] | 10] ] 10 | ] ns 1xis XJ Set-up Time s| ]|10| | 10] f{ 10] | 10] ] 10] ] ns NOTES: 2679 thi 06 1. Timings referenced as in AC Test Conditions. 3. Values guaranteed by design, not currently tested. 2. Pulse widths less than minimum value are not allowed. 4. Only applies to read data flow-through mode. 5.24 41DT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x98 and 1K x9 MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS") (Continued) (Commercial: Vcc = 5.0V+10%, TA = 0C to +70C; Military: Vcc = 5.0V410%, TA = -55C to +125C) Military Com & Mil. Military?! 7200 L40 7200L50 7200L65 7200L80 7200L120 7201LA40 7201LA50 7201LA65 | 7201LA80 7201LA120 7202LA40 7202LA50 7202LA65 7202LA80 7202LA120 Symbol Parameter Min. | Max.| Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit ts Shift Frequency _ 20 | 15 | 125] 10 _- 7 MHz tRC Read Cycle Time 50 | 65 _ 80 _ 100 _ 140 -_ ns ta Access Time _ 40 | 50 _ 65 _ 80 - 120 ns tAR Read Recovery Time 10 _ 15 _ 15 _ 20 _ 20 _- ns trew__| Read Pulse Width) 40 | 50 | | 65] | so | | 120 | | os tRALZ Read Pulse Low to Data Bus at Low 24) 5 = 10 _ 10 _ 10 _ 10 _ ns twiz__| Write Pulse High to Data Bus at Low Z45))_ 10 | 15 _ is | | 20 | 20 ns tbv Data Valid from Read Pulse High 5 _ 5 _ 5 _ 5 _ 5 _ ns TRHZ Read Pulse High to Data Bus at High Zz | 2a) 30 30 _ 30 - 35 ns two Write Cycle Time 50 = 65 _ 80 _- 100 - 140 - ns twew | Write Pulse Width) 40 |50 | }] 6 | | so | | 120 | | ns twa Write Recovery Time 10 _ 15 _ 15 - 20 20 ns tos Data Set-up Time 20 _ 30 _ 30 _ 40 _ 40 ns tDH Data Hold Time 0 _ 5 _ 10 = 10 _ 10 _ ns tRsc Reset Cycle Time 50 | 65 80 100 140 ns tRS Reset Pulse Width 40 |50 | | 65 {| | 80 |] |] 120] | ns trss Reset Set-up Time) 40 | 50 ~ 65 | | so | | t2z0 | ns tRSR Reset Recovery Time 10 _ 15 _ 15 _ 20 _ 20 _ ns tATC Retransmit Cycle Time 50 | 65 = 80 | 100; 140 _ ns {RT Retransmit Pulse Width 40 | 50 | | 6 | | 80 | | 120] | ns {RTS Retransmit Set-up Time") 40 | 50 _ 65 | | so | | 120 | ns {ATR Retransmit Recovery Time 10 _ 15 _ 15 _ 20 _ 20 ns tEFL Reset to Empty Flag Low 50 - 65 80 100 _ 140 ns tHFH,FFH] Reset to Half-Full and Full Flag High _ 50 |} 65 _ 80 _ 100 _ 140 ns tRTF Retransmit Low to Flags Valid _- 50 - 65 _ 80 =_ 100 - 140 ns tREF Read Low to Empty Flag Low 30 45 60 60 60 ns tRFF Read High to Full Flag High _ 35 _ 45 _ 60 _ 60 _ 60 ns {RPE Read Pulse Width after EF High 40 _ 50 _ 65 _ 80 _ 120 _ ns tWweEF Write High to Empty Flag High _ 35 _ 45 _ 60 _ 60 _- 60 ns tWFF Write Low to Full Flag Low _ 35 _ 45 _ 60 60 _ 60 ns {WHF Write Low to Half-Full Flag Low _ 50} 65 _ 80 | 100 _ 140 ns tRHF Read High to Half-Full Flag High - 50 ~ 65 - 80 _ 100 _ 140 ns twpr Write Pulse Width after FF High 40 _ 50 _ 65 _ 80 _ 120 _ ns txOL Read/Write to XO Low =_ 40 | 50 | 6 | | 80 | | 120 | ns txOH ReadMWrite to XO High _ 40 _- 50 _ 65 80 _ 120 ns tx! XW Pulse Width) 40 | 50 | | 6 | | 80 | | 120 | | ns tan Xi Recovery Time 10 | 10 = 10] | 10] 10 ns txts Xi Set-up Time 10 | 15 _ is | | 15 | 15 _ ns NOTES: 2679 tbl 07 1. Timings referenced as in AC Test Conditions 4. Values guaranteed by design, not currently tested. 2. Speed grades 65, 80 and 120 not available in the CERPACK 5. Only applies to read data flow-through mode. 3. Pulse widths less than minimum value are not allowed.1DT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9,512 x9 and 1K x9 MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 1 2679 Ibl 08 SIGNAL DESCRIPTIONS INPUTS: DATA IN (Do Ds) Data inputs for 9-bit wide data. CONTROLS: RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a low state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the high state during the window shown in Figure 2, (i.e., trss before the rising edge of RS) and should not change until tasR after the rising edge of RS. Half-Full Flag (HF) will be reset to high after Reset (RS). WRITE ENABLE (W) Awrite cycle is initiated on the falling edge of this inputif the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled and at the falling edge of the next write operation, the Haif-Full Flag (HF) will be set to low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go high after trFF, allowing a valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. READ ENABLE (A) A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes high, 5V { 1.1K TO OUTPUT PIN aa . 6800 => 30pF = 2679 drw 08 or equivalent circuit Figure 1. Output Load " Includes scope and jig capacitances. the Data Outputs (Qo Qs) will return to a high impedance condition until the next Read operation. When all data has been read from the FIFO, the Empty Flag (EF) will go low, allowing the final read cycle but inhibiting further read operations with the data outputs remaining in a high imped- ance state. Once a valid write operation has been accom- plished, the Empty Flag (EF) will go high after tweF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from F so external changes in Rwill not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT (FU/AT) This is a dual-purpose input. Inthe Depth Expansion Mode, this pin is grounded to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the restransmit input. The Single Device Mode is initiated by grounding the Expansion In (XI). The IDT7200/7201A/7202A can be made to retransmit data when the Retransmit Enabie control (RT) input is pulsed low. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the high state during retransmit. This feature is useful when less than 256/ 512/1024 writes are performed between resets. The retrans- mit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers. EXPANSION IN (XI) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (Xl) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. OUTPUTS: FULL FLAG (FF) The Full Flag (FF) will go low, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go low after 256 writes for IDT7200, 512 writes for the IDT7201A and 1024 writes for the IDT7202A.IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x9 EMPTY FLAG (EF) The Empty Flag (EF) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HP) This is a dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set low and will remain set until the difference between the write MILITARY AND COMMERCIAL TEMPERATURE RANGES pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by using rising edge of the read operation. in the Depth Expansion Mode, Expansion In (XI) is con- nected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. DATA OUTPUTS (Qo Qs) Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a high state. tHFH, tFFH 2679 drw 04 Reset trsc tRS AS W R EF HE, FE NOTES: Figure 2. 1. EF, FF, HF may change status during Reset, but flags will be valid at tasc. 2. WandA = Vin around the rising edge of AS. |___- bit R47 o4 It tRLZ tov Qo Qs t DATA OUT VALID DATA OUT vALIOK Kj} two t{wPw > tWR Kf tps ->e tDH Do Da DATA IN VALID DATA IN VALID 2679 drw 05 Figure 3. Asynchronous Write and Read OperationIDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x9 and 1K x9 MILITARY AND COMMERCIAL TEMPERATURE RANGES LAST WRITE IGNORED FIRST READ ADDITIONAL FIRST WRITE READS WRITE " S| \_/ tWFF tRFF : 2679 drw 06 Figure 4. Full Flag From Last Write to First Read IGNORED FIRST WRITE ADDITIONAL; FIRST WRITES READ READ J E tA oxracur }-_{RY vaio XX RXvAOXY) 2679 drw 07 Figure 5. Empty Flag From Last Read to First Write LAST READ FLAG VALID 2679 drw 08 Figure 6. Retransmit10T7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x9 MILITARY AND COMMERCIAL TEMPERATURE RANGES wo | a j yy Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse 2679 drw 09 Dl w VAULT HALF-FULL OR LESS L, WHF HE MORE THAN HALF-FULL 2678 dew 11 HALF-FULL OR LESS Figure 9. Half-Full Flag Timing WAITE TO LAST PHYSICAL LOCATION =| AEAD FROM LAST PRYSICAL LOCATION tXOL t XOH tXOL t XOH xO ft Figure 10. Expansion Out Dl 2679 drew 12 5.24 9IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x9, 512x9 and 1K x9 xl {xis WRITE TO FIRST PHYSICAL Ww LOCATION a MILITARY AND COMMERCIAL TEMPERATURE RANGES txis READ FROM FIRST PHYSICAL LOGATION 2679 drw 13 Figure 11. Expansion In OPERATING MODES: Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). For additional information, refer to Tech Note 8: Oper- ating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. Single Device Mode A single IDT7200/7201A/7202A may be used when the application requirements are for 256/512/1024 words or less. The IDT7200/7201A/7202A is in a Single Device Configura- tion when the Expansion In (XI) control input is grounded (see Figure 12). Depth Expansion The IDT7200/7201 A/7202A can easily be adapted to appli- cations when the requirements are for greater than 256/512/ 1024 words. Figure 14 demonstrates Depth Expansion using three IDT7200/7201A/7202As. Any depth can be attained by adding additional 1DT7200/7201A/7202As. The IDT7200/ 7201 A/7202A operates in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the high state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 14. 4, External logic is needed to generate a composite Full Flag (FF) and Empty Flag (I (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite F FF or EF), See Figure 14. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. For additional information, refer to Tech Note 9: Cascading FIFOs or FIFO Modules. USAGE MODES: Width Expansion Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Sta- tus flags (EF, FF and HF) canbe detected from any one device. Figure 13 demonstrates an 18-bit word width by using two IDT7200/7201 A/7202As. Any word width can be attained by adding additional IDT7200/7201A/7202As (Figure 13). Bidirectional Operation Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT7200/7201 A/7202As as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this made. Data Flow-Through Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow- through mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tweF + ta) ns after the rising edge of W, called the first write edge, and it remains on the bus until the R line is raised from low-to-high, after which the bus would go into a three-state mode after tRHz ns. The EFline would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the W line being low causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer. Compound Expansion The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15). .24 101DT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x9 MILITARY AND COMMERCIAL TEMPERATURE RANGES (HALF-FULL FLAG) = (HF) WRITE (W) > READ (AR) 9 IDT 3 DATA IN a 7200/ _ DATA OUT (Q) FULL FLAG (FF) J 7201A/ | ____ EMPTY FLAG F) RESET (RS) 7202A RETRANSMIT (AT) EXPANSION IN (xl) i 2679 drw 14 Figure 12. Block Diagram of Single 256/512/1024 x 9 FIFO DATAIN (D) WRITE (W) FULL FLAG (FF) RESET (RS) READ (R) EMPTY FLAG F) RETRANSMIT (RT) 18 DATA ouT(Q) 2679 drw 15 Figure 13. Block Diagram of 256/512/1024 x 18 FIFO Memory Used in Width Expansion Mode TABLE IRESET AND RETRANSMIT Single Device Configuration/Width Expansion Mode Internal Status Mode ' Read Pointer Write Pointer Reset Location Zero Location Zero Read/Write x NOTE: 2679 tbi 09 1. Pointer will increment if flag is High. TABLE IIRESET AND FIRST LOAD TRUTH TABLE Depth Expansion/Compound Expansion Mode Internal Status Mode Read Pointer Write Pointer Reset First Device (1) Location Zero Location Zero ReadMWrite 1 x (1) x xX x x NOTE: 2679 tbl 10 1. Xlis connected to XO of previous device. See Figure 14. RS = Reset Input, FL/AT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output, Xl = Expansion Input, HF = Half-Full Flag Output 5.24 11DT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 8, 512 x 9 and 1K x9 MILITARY AND COMMERCIAL TEMPERATURE RANGES w R D Q Vec FULL EMPTY RS xi 2679 drw 16 Figure 14. Block Diagram of 768 x 9/1536 x 9/3072 x 9 FIFO Memory (Depth Expansion) Qo-Qa Q9-Q17 Q(N-8) -QN | Qo-as | | Q9-Q17 | | Qi N-8) -QN IDT7200/ IDT7200/ (DT7200/ IDT7201A/ IDT7201A/ IDT7201A/ =-o= IDT7202A IDT7202A IDT7202A R,W. RS DEPTH > DEPTH [**? * DEPTH EXPANSION EXPANSION EXPANSION BLOCK BLOCK BLOCK 4) Do -Da st Do -D17 fi D(n-8)-DN Do-DNn eee Do -DN Dis -DN D(n-8)-DN 2679 drw 17 Figure 15. Compound FIFO Expansion NOTES: 1. For depth expsansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13.1DT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, $512 x 9 and 1K x9 MILITARY AND COMMERCIAL TEMPERATURE RANGES WA") 15; [t Re _ 7200 | EFs ssa) tek |= He Da o-8 QB0-8 SYSTEM A < Ln, SYSTEMB Qa0-8 7OB 0-8 Aa>| 700 o_o, ae ey EFa* | [- FFe 2679 drw 18 Figure 16. Bidirectional FIFO Mode DATAIN W | 6 + tAPE a WAAAY EF f tREF twer+ twiz >4 re ta onthe HXRRRKKN oataonrvan) 2679 drw 19 Figure 17. Read Data Flow-Through Mode t wer w h l+ t RFF + FF t i l+ t WFF iN f+ t DH DATAIN + t Ds KiH ta ARK DAracir VAUD XXX Figure 18. Write Data Fiow-Through Mode DATA out 2679 drw 20 5.24 131DT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1K x9 ORDERING INFORMATION IDT = XXXX Xx XXX x X Device Type Power Speed Package Process/ Temperature Range | 8 * "A" to be included for 7201 and 7202 ordering part number. MILITARY AND COMMERCIAL TEMPERATURE RANGES Commercial (0C to + 70C) Military (-55C to + 125C) Compliant to MIL-STD-883, Class B Plastic DIP (7201 & 7202 Only) Plastic THINDIP CERDIP (7201 & 7202 Only) Ceramic THINDIP Plastic Leaded Chip Carrier Soic Leadless Chip Carrier (7201 & 7202 Only) CERPACK (7201 & 7202 Only) Commerical Only Commercial Only Commercial Only Conavorciat Only Access Time (ta) Military Only Speed in Nanoseconds Military only-- except XE package Low Power* 256 x 9-Bit FIFO 512 x 9-Bit FIFO 1024 x 9-Bit FIFO 2679 drw 21 14