Low Skew, 1:18 Crystal-to-LVCMOS/LVTTL Fanout Buffer ICS83918I DATA SHEET General Description Features The ICS83918I is a low skew, 1:18 Crystal-to- LVCMOS/LVTTL Fanout Buffer. The ICS83918I has selectable LVCMOS/LVTTL clock or crystal inputs. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. * * * * * Eighteen LVCMOS/LVTTL output * * Output skew: 75ps (maximum) @ 3.3V/3.3V * * -40C to 85C ambient operating temperature The ICS83918I is characterized at full 3.3V, full 2.5V and mixed 3.3V/2.5V, 3.3V/1.8V, and 2.5V/1.8V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83918I ideal for those clock distribution applications demanding well defined performance and repeatability. Block Diagram Selectable crystal oscillator interface or LVCMOS_CLK Maximum output frequency: 200MHz Crystal input frequency range: 10MHz to 40MHz RMS phase jitter using a 25MHz crystal (1kHz - 1MHz): 0.449ps (typical) @ 3.3V/3.3V Operating supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment Q5 GND Q3 Q4 LVCMOS_CLK Pulldown 32 31 30 29 28 27 26 25 0 18 XTAL_OUT VDDO OSC Q1 XTAL_IN Q2 Q0 CLK_SEL Pulldown Q0:Q17 1 GND 1 24 Q6 GND 2 23 Q7 LVCMOS_CLK 3 22 Q8 CLK_SEL 4 21 VDDO XTAL_IN 5 20 Q9 XTAL_OUT 6 19 Q10 VDD 7 18 Q11 VDDO 8 17 GND Q12 VDDO Q13 Q14 Q15 GND Q16 Q17 9 10 11 12 13 14 15 16 ICS83918I 32 Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ICS83918AYI REVISION B AUGUST 17, 2010 1 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 2, 12, 17, 25 GND Power 3 LVCMOS_CLK Input Pulldown Power supply ground. Single-ended clock input. LVCMOS/LVTTL interface levels. 4 CLK_SEL Input Pulldown Clock select pin. When HIGH, selects LVCMOS_CLK. When LOW, selects crystal inputs. LVCMOS/LVTTL interface levels. 5, 6 XTAL_IN, XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 7 VDD Power Positive supply pin. 8, 16, 21, 29 VDDO Power Output supply pins. 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2,Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (per output) Test Conditions Minimum Output Impedance ICS83918AYI REVISION B AUGUST 17, 2010 Maximum Units 4 pF VDDO = 3.465V 9 pF VDDO = 2.625V 8 pF VDDO = 2V 8 pF 51 k RPULLDOWN Input Pulldown Resistor ROUT Typical VDDO = 3.465V 18 19 20 VDDO = 2.625V 20 22 24 VDDO = 2V 25 29 34 2 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 53.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V5%, TA = -40C to 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 24 mA IDDO Output Supply Current 27 mA No Load Table 3B. Power Supply DC Characteristics, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C to 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 24 mA IDDO Output Supply Current 26 mA No Load Table 3C. Power Supply DC Characteristics, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C to 85C Symbol Parameter VDD Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 24 mA IDDO Output Supply Current 29 mA ICS83918AYI REVISION B AUGUST 17, 2010 Test Conditions No Load 3 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 3D. Power Supply DC Characteristics, VDD = VDDO = 2.5V5%, TA = -40C to 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 23 mA IDDO Output Supply Current 25 mA No Load Table 3E. Power Supply DC Characteristics, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = -40C to 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 23 mA IDDO Output Supply Current 24 mA No Load Table 3F. LVCMOS/LVTTL DC Characteristics, TA = -40C to 85C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current CLK_SEL, LVCMOS_CLK VDD = VIN = 3.465V IIL Input Low Current CLK_SEL, LVCMOS_CLK VDD = 3.465V, VIN = 0V -5 A VDDO = 3.465V 2.6 V VDDO = 2.625V 1.8 V VDDO = 2V VDDO - 0.3 V VOH VOL Output High Voltage Output Low Voltage Test Conditions Minimum VDD = 3.465V Typical Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.465V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 150 A VDDO = 3.465 or 2.625V 0.5 V VDDO = 2V 0.35 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Table 4. Crystal Characteristics Parameter Test Conditions Minimum Maximum Units 40 MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Mode of Oscillation Fundamental Frequency ICS83918AYI REVISION B AUGUST 17, 2010 Typical 10 4 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDO = 3.3V5%, TA = -40C to 85C Symbol Parameter fOUT Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 tjit(O) RMS Phase Jitter, (Random); NOTE 2 tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 3, 6 75 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps tR / tF Output Rise/Fall Time; NOTE 5 odc Output Duty Cycle Test Conditions Minimum Typical 1.85 Maximum Units 200 MHz 3.0 ns 25MHz, Integration Range: 1kHz to 1MHz 0.449 ps 155.52MHz, Integration Range: 12kHz to 20MHz 0.145 ps 20% to 80% 300 700 ps OUT 150MHz 45 55 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at fOUT unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Refer to the Phase Noise Plot following this section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. ICS83918AYI REVISION B AUGUST 17, 2010 5 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 5B. AC Characteristics, VDD = 3.3V5%,VDDO = 2.5V5%, TA = -40C to 85C Symbol Parameter fOUT Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 tjit(O) RMS Phase Jitter, (Random); NOTE 2 tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 3, 6 75 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 1 ns tR / t F Output Rise/Fall Time; NOTE 5 odc Output Duty Cycle Test Conditions Minimum Typical 2 Maximum Units 200 MHz 3 ns 25MHz, Integration Range: 1kHz to 1MHz 0.465 ps 155.52MHz, Integration Range: 12kHz to 20MHz 0.161 ps 20% to 80% 300 700 ps OUT 150MHz 45 55 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at fOUT unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Refer to the Phase Noise Plot following this section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5C. AC Characteristics, VDD = 3.3V5%,VDDO = 1.8V0.2V, TA = -40C to 85C Symbol Parameter Test Conditions Minimum Typical fOUT Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 tjit(O) RMS Phase Jitter, (Random); NOTE 2 tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 3, 6 75 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 1 ns tR / tF Output Rise/Fall Time; NOTE 5 odc Output Duty Cycle 1.65 Maximum Units 200 MHz 4.3 ns 25MHz, Integration Range: 1kHz to 1MHz 0.595 ps 155.52MHz, Integration Range: 12kHz to 20MHz 0.228 ps 20% to 80% 200 800 ps OUT 150MHz 40 60 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at fOUT unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Refer to the Phase Noise Plot following this section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. ICS83918AYI REVISION B AUGUST 17, 2010 6 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 5D. AC Characteristics, VDD = VDDO = 2.5V5%, TA = -40C to 85C Symbol Parameter fOUT Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 tjit(O) RMS Phase Jitter, (Random); NOTE 2 tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 3, 6 75 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 1 ns tR / t F Output Rise/Fall Time; NOTE 5 odc Output Duty Cycle Test Conditions Minimum Typical 2 Maximum Units 200 MHz 3 ns 25MHz, Integration Range: 1kHz to 1MHz 0.478 ps 155.52MHz, Integration Range: 12kHz to 20MHz 0.157 ps 20% to 80% 300 700 ps OUT 150MHz 45 55 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at fOUT unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Refer to the Phase Noise Plot following this section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5E. AC Characteristics, VDD = 2.5V5%,VDDO = 1.8V0.2V, TA = -40C to 85C Symbol Parameter fOUT Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 tjit(O) RMS Phase Jitter, (Random); NOTE 2 tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 3, 6 tsk(pp) Part-to-Part Skew; NOTE 4, 6 tR / tF Output Rise/Fall Time; NOTE 5 odc Output Duty Cycle Test Conditions Minimum Typical 1.75 Maximum Units 200 MHz 3.85 ns 25MHz, Integration Range: 1kHz to 1MHz 0.591 ps 155.52MHz, Integration Range: 12kHz to 20MHz 0.175 ps 75 ps 1.15 ns 20% to 80% 200 800 ps OUT 150MHz 45 55 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at fOUT unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Refer to the Phase Noise Plot following this section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. ICS83918AYI REVISION B AUGUST 17, 2010 7 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Noise Power dBc Hz Typical Phase Noise at 25MHz Crystal (3.3V core/3.3V output) Offset Frequency (Hz) ICS83918AYI REVISION B AUGUST 17, 2010 8 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Additive Phase Jitter (2.5V output) The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio SSB Phase Noise dBc/Hz of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.161ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. ICS83918AYI REVISION B AUGUST 17, 2010 The source generator "IFR2042 10kHz - 56.4GHz Low Noise Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator". 9 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information 2.05V5% 1.65V5% 1.25V5% SCOPE VDD, SCOPE VDD VDDO LVCMOS VDDO Qx Qx GND LVCMOS GND -1.65V5% -1.25V5% 3.3V Core/2.5V Output Load AC Test Circuit 3.3 Core/3.3V Output Load AC Test Circuit 2.4V5% 1.25V5% 0.9V0.1V SCOPE VVDD DD V VDDO DDO SCOPE VDD, VDDO Qx Qx LVCMOS GND LVCMOS GND -1.25V5% -0.9V0.1V 2.5V/2.5V Output Load AC Test Circuit 3.3V Core/1.8V Output Load AC Test Circuit 1.6V0.025V Phase Noise Plot Noise Power 0.9V0.1V SCOPE VDD VDDO Qx GND LVCMOS f1 f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers -0.9V0.1V RMS Phase Jitter 2.5V/1.8V Output Load AC Test Circuit ICS83918AYI REVISION B AUGUST 17, 2010 Offset Frequency 10 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information, continued Part 1 VCCO 2 Qx V DDO Qx Part 2 VCCO 2 Qy 2 V DDO Qy 2 tsk(pp) tsk(b) Output Skew Part-to-Part Skew VDD 2 80% 80% LVCMOS_CLK Q0:Q17 20% 20% tR VDDO 2 tF Q0:Q17 t PD Propagation Delay Output Rise/Fall Time V V DD DD 2 Q0:Q17 2 t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period ICS83918AYI REVISION B AUGUST 17, 2010 11 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Applications Information Crystal Input Interface The ICS83918I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 27pF X1 18pF Parallel Crystal XTAL_OUT C2 27pF Figure 1. Crystal Input Interface Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 2A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. 3.3V 3.3V R1 100 Ro ~ 7 Ohm C1 Zo = 50 Ohm XTAL_IN RS 43 R2 100 Driv er_LVCMOS 0.1uF XTAL_OUT Cry stal Input Interf ace Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V C1 Zo = 50 Ohm XTAL_IN R1 50 Zo = 50 Ohm 0.1uF XTAL_OUT LVPECL Cry stal Input Interf ace R2 50 R3 50 Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface ICS83918AYI REVISION B AUGUST 17, 2010 12 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Recommendations for Unused Input and Output Pins Inputs: Outputs: Crystal Inputs LVCMOS Outputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached. LVCMOS_CLK Input For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the LVCMOS_CLK to ground. LVCMOS Control Pin The control pin has an internal pulldown; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. ICS83918AYI REVISION B AUGUST 17, 2010 13 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS83918I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS83918I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * Power (core)MAX = VDD_MAX * (IDD + IDDO) = 3.465V *(24mA + 27mA) = 176.7mW Dynamic Power Dissipation at 200MHz Power (200MHz) = CPD * Frequency * (VDD)2 * number of outputs = 9pF * 200MHz * (3.465V)2 * 18 = 389mW Total Power Dissipation * Total Power = Power (core)MAX + Power (200MHz) = 176.7mW + 389mW = 565.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 53.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.566W * 53.5C/W = 115.3C. This is well below the limit of 125C. This calculation is only an example. Tj will vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 32 Lead LQFP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS83918AYI REVISION B AUGUST 17, 2010 0 1 2.5 53.5C/W 48.0C/W 44.0C/W 14 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Reliability Information Table 7. JA vs. Air Flow Table for a 32 Lead LQFP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 53.5C/W 48.0C/W 44.0C/W Transistor Count The transistor count for ICS83918I is: 909 ICS83918AYI REVISION B AUGUST 17, 2010 15 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Package Outline and Package Dimensions Package Outline - Y Suffix for 32 Lead LQFP Table 8. Package Dimensions for 32 Lead LQFP JEDEC Variation: BBC - HD All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75 0 7 ccc 0.10 Reference Document: JEDEC Publication 95, MS-026 ICS83918AYI REVISION B AUGUST 17, 2010 16 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number 83918AYI 83918AYIT 83918AYILF 83918AYILFT Marking ICS83918AYI ICS83918AYI ICS83918AYIL ICS83918AYIL Package 32 Lead LQFP 32 Lead LQFP "Lead-Free" 32 Lead LQFP "Lead-Free" 32 Lead LQFP Shipping Packaging Tray 1000 Tape & Reel Tray 1000 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS83918AYI REVISION B AUGUST 17, 2010 17 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER Revision History Sheet Rev Table Page Description of Change B T5A, T5B, T5D, T5E T5D 5-7 7 AC Characteristic Tables - added Test Conditions to Output Duty Cycle. 2.5 AC Characteristics Table - changed Part-to-Part skew from 1.1ns max to 1.0 ns max. ICS83918AYI REVISION B AUGUST 17, 2010 18 Date 8/17/10 (c)2010 Integrated Device Technology, Inc. ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER We've Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.