DATA SHEET
ICS83918AYI REVISION B AUGUST 17, 2010 1 ©2010 Integrated Device Technology, Inc.
Low Skew, 1:18 Crystal-to-LVCMOS/LVTTL
Fanout Buffer
ICS83918I
General Description
The ICS83918I is a low skew, 1:18 Crystal-to- LVCMOS/LVTTL
Fanout Buffer. The ICS83918I has selectable LVCMOS/LVTTL clock
or crystal inputs. The low impedance LVCMOS/LVTTL outputs are
designed to drive 50Ω series or parallel terminated transmission
lines.
The ICS83918I is characterized at full 3.3V, full 2.5V and mixed
3.3V/2.5V, 3.3V/1.8V, and 2.5V/1.8V output operating supply modes.
Guaranteed output and part-to-part skew characteristics make the
ICS83918I ideal for those clock distribution applications demanding
well defined performance and repeatability.
Features
•Eighteen LVCMOS/LVTTL output
•Selectable crystal oscillator interface or LVCMOS_CLK
•Maximum output frequency: 200MHz
•Crystal input frequency range: 10MHz to 40MHz
•RMS phase jitter using a 25MHz crystal (1kHz – 1MHz): 0.449ps
(typical) @ 3.3V/3.3V
•Output skew: 75ps (maximum) @ 3.3V/3.3V
•Operating supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
OSC 0
1
18 Q0:Q17
Pulldown
Pulldown
CLK_SEL
LVCMOS_CLK
XTAL_IN
XTAL_OUT
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDDO
Q9
Q10
Q11
GND
GND
GND
LVCMOS_CLK
CLK_SEL
XTAL_IN
XTAL_OUT
VDD
VDDO
GND
Q5
Q4
Q3
VDDO
Q2
Q1
Q0
Q17
Q16
Q14
Q15
GND
Q13
Q12
VDDO
Pin Assignment
ICS83918I
32 Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
Block Diagram
ICS83918AYI REVISION B AUGUST 17, 2010 2 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2, 12, 17, 25 GND Power Power supply ground.
3 LVCMOS_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
4 CLK_SEL Input Pulldown Clock select pin. When HIGH, selects LVCMOS_CLK. When LOW,
selects crystal inputs. LVCMOS/LVTTL interface levels.
5,
6
XTAL_IN,
XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
7V
DD Power Positive supply pin.
8, 16, 21, 29 VDDO Power Output supply pins.
9, 10, 11,
13, 14, 15,
18, 19, 20, 22,
23, 24, 26, 27,
28, 30, 31, 32
Q17, Q16, Q15,
Q14, Q13, Q12,
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2,Q1, Q0
Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4pF
CPD
Power Dissipation Capacitance
(per output)
VDDO = 3.465V 9 pF
VDDO = 2.625V 8 pF
VDDO = 2V 8 pF
RPULLDOWN Input Pulldown Resistor 51 kΩ
ROUT Output Impedance
VDDO = 3.465V 18 19 20 Ω
VDDO = 2.625V 20 22 24 Ω
VDDO = 2V 25 29 34 Ω
ICS83918AYI REVISION B AUGUST 17, 2010 3 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C
Table 3B. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C to 85°C
Table 3C. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C to 85°C
Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, VO -0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA 53.5°C/W (0 mps)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 3.135 3.3 3.465 V
VDDO Output Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 24 mA
IDDO Output Supply Current No Load 27 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 3.135 3.3 3.465 V
VDDO Output Supply Voltage 2.375 2.5 2.625 V
IDD Power Supply Current 24 mA
IDDO Output Supply Current No Load 26 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 3.135 3.3 3.465 V
VDDO Output Supply Voltage 1.6 1.8 2.0 V
IDD Power Supply Current 24 mA
IDDO Output Supply Current No Load 29 mA
ICS83918AYI REVISION B AUGUST 17, 2010 4 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 3D. Power Supply DC Characteristics, VDD = VDDO = 2.5V±5%, TA = -40°C to 85°C
Table 3E. Power Supply DC Characteristics, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C to 85°C
Table 3F. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
Table 4. Crystal Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 2.375 2.5 2.625 V
VDDO Output Supply Voltage 2.375 2.5 2.625 V
IDD Power Supply Current 23 mA
IDDO Output Supply Current No Load 25 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 2.375 2.5 2.625 V
VDDO Output Supply Voltage 1.6 1.8 2.0 V
IDD Power Supply Current 23 mA
IDDO Output Supply Current No Load 24 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage VDD = 3.465V 2 VDD + 0.3 V
VDD = 2.5V 1.7 VDD + 0.3 V
VIL
Input
Low Voltage
VDD = 3.465V -0.3 0.8 V
VDD = 2.5V -0.3 0.7 V
IIH
Input
High Current
CLK_SEL,
LVCMOS_CLK VDD = VIN = 3.465V 150 µA
IIL
Input
Low Current
CLK_SEL,
LVCMOS_CLK VDD = 3.465V, VIN = 0V -5 µA
VOH Output High Voltage
VDDO = 3.465V 2.6 V
VDDO = 2.625V 1.8 V
VDDO = 2V VDDO – 0.3 V
VOL Output Low Voltage VDDO = 3.465 or 2.625V 0.5 V
VDDO = 2V 0.35 V
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 10 40 MHz
Equivalent Series Resistance (ESR) 50 Ω
Shunt Capacitance 7pF
ICS83918AYI REVISION B AUGUST 17, 2010 5 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at fOUT unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Refer to the Phase Noise Plot following this section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 200 MHz
tpLH
Propagation Delay, Low to High;
NOTE 1 1.85 3.0 ns
tjit(Ø) RMS Phase Jitter, (Random);
NOTE 2
25MHz,
Integration Range: 1kHz to 1MHz 0.449 ps
tjit Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range: 12kHz to 20MHz 0.145 ps
tsk(o) Output Skew; NOTE 3, 6 75 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 300 700 ps
odc Output Duty Cycle ƒ
OUT ≤ 150MHz 45 55 %
ICS83918AYI REVISION B AUGUST 17, 2010 6 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 5B. AC Characteristics, VDD = 3.3V±5%,VDDO = 2.5V±5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at fOUT unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Refer to the Phase Noise Plot following this section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5C. AC Characteristics, VDD = 3.3V±5%,VDDO = 1.8V±0.2V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at fOUT unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Refer to the Phase Noise Plot following this section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 200 MHz
tpLH
Propagation Delay, Low to High;
NOTE 1 23ns
tjit(Ø) RMS Phase Jitter, (Random);
NOTE 2
25MHz,
Integration Range: 1kHz to 1MHz 0.465 ps
tjit Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range: 12kHz to 20MHz 0.161 ps
tsk(o) Output Skew; NOTE 3, 6 75 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6 1ns
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 300 700 ps
odc Output Duty Cycle ƒ
OUT ≤ 150MHz 45 55 %
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 200 MHz
tpLH
Propagation Delay, Low to High;
NOTE 1 1.65 4.3 ns
tjit(Ø) RMS Phase Jitter, (Random);
NOTE 2
25MHz,
Integration Range: 1kHz to 1MHz 0.595 ps
tjit Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range: 12kHz to 20MHz 0.228 ps
tsk(o) Output Skew; NOTE 3, 6 75 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6 1ns
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 200 800 ps
odc Output Duty Cycle ƒ
OUT ≤ 150MHz 40 60 %
ICS83918AYI REVISION B AUGUST 17, 2010 7 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 5D. AC Characteristics, VDD = VDDO = 2.5V±5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at fOUT unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Refer to the Phase Noise Plot following this section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5E. AC Characteristics, VDD = 2.5V±5%,VDDO = 1.8V±0.2V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at fOUT unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Refer to the Phase Noise Plot following this section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 200 MHz
tpLH
Propagation Delay, Low to High;
NOTE 1 23ns
tjit(Ø) RMS Phase Jitter, (Random);
NOTE 2
25MHz,
Integration Range: 1kHz to 1MHz 0.478 ps
tjit Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range: 12kHz to 20MHz 0.157 ps
tsk(o) Output Skew; NOTE 3, 6 75 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6 1ns
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 300 700 ps
odc Output Duty Cycle ƒ
OUT ≤ 150MHz 45 55 %
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 200 MHz
tpLH
Propagation Delay, Low to High;
NOTE 1 1.75 3.85 ns
tjit(Ø) RMS Phase Jitter, (Random);
NOTE 2
25MHz,
Integration Range: 1kHz to 1MHz 0.591 ps
tjit Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range: 12kHz to 20MHz 0.175 ps
tsk(o) Output Skew; NOTE 3, 6 75 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6 1.15 ns
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 200 800 ps
odc Output Duty Cycle ƒ
OUT ≤ 150MHz 45 55 %
ICS83918AYI REVISION B AUGUST 17, 2010 8 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Typical Phase Noise at 25MHz Crystal (3.3V core/3.3V output)
Noise Power dBc
Hz
Offset Frequency (Hz)
ICS83918AYI REVISION B AUGUST 17, 2010 9 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Additive Phase Jitter (2.5V output)
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator".
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.161ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
ICS83918AYI REVISION B AUGUST 17, 2010 10 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Parameter Measurement Information
3.3 Core/3.3V Output Load AC Test Circuit
3.3V Core/1.8V Output Load AC Test Circuit
2.5V/1.8V Output Load AC Test Circuit
3.3V Core/2.5V Output Load AC Test Circuit
2.5V/2.5V Output Load AC Test Circuit
RMS Phase Jitter
SCOPE
Qx
LVCMOS
GND
1.65V±5%
-1.65V±5%
VDD,
VDDO
VDD
VDDO
SCOPE
Qx
LVCMOS
GND
2.4V±5%
-0.9V±0.1V
0.9V±0.1V
VDD
VDDO
SCOPE
Qx
LVCMOS
GND
1.6V±0.025V
-0.9V±0.1V
0.9V±0.1V
VDD
VDDO
SCOPE
Qx
LVCMOS
GND
2.05V±5%
-1.25V±5%
1.25V±5%
VDD
VDDO
SCOPE
Qx
LVCMOS
GND
1.25V±5%
-1.25V±5%
VDD,
VDDO
Offset Frequency
f1f2
Phase Noise Plot
RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers
Noise Power
ICS83918AYI REVISION B AUGUST 17, 2010 11 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Parameter Measurement Information, continued
Output Skew
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
Part-to-Part Skew
Propagation Delay
Qx
Qy
tsk(b)
V
CCO
2
V
CCO
2
20%
80% 80%
20%
tRtF
Q0:Q17
tPERIOD
tPW
tPERIOD
odc =
V
DD
2
V
DD
2
x 100%
tPW
Q0:Q17
Qx
Qy
tsk(pp)
V
DDO
2
V
DDO
2
Part 1
Part 2
tPD
VDD
2
VDDO
2
Q0:Q17
LVCMOS_CLK
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ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Applications Information
Crystal Input Interface
The ICS83918I has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 1 below
were determined using an 18pF parallel resonant crystal and were
chosen to minimize the ppm error. The optimum C1 and C2 values
can be slightly adjusted for different board layouts.
Figure 1. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
applications, R1 and R2 can be 100Ω. This can also be
accomplished by removing R1 and making R2 50Ω. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27pF
C2
27pF
R2
100
R1
100
RS 43
Ro ~ 7 Ohm
Driver_LVCMOS
Zo = 50 Ohm C1
0.1uF
3.3V
3.3V
Cry stal Input Interface
XTA L _ I N
XTA L _ O U T
Cry stal Input Interface
XTAL_IN
XTAL_OUT
R3
50
C1
0.1uF
R2
50
R1
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
VCC=3.3V
ICS83918AYI REVISION B AUGUST 17, 2010 13 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
LVCMOS_CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the LVCMOS_CLK to ground.
LVCMOS Control Pin
The control pin has an internal pulldown; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Outputs:
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. We recommend that
there is no trace attached.
ICS83918AYI REVISION B AUGUST 17, 2010 14 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS83918I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS83918I is the sum of the core power plus the power dissipated in the load(s). The following is the power
dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)MAX = VDD_MAX * (IDD + IDDO) = 3.465V *(24mA + 27mA) = 176.7mW
Dynamic Power Dissipation at 200MHz
Power (200MHz) = CPD * Frequency * (VDD)2 * number of outputs = 9pF * 200MHz * (3.465V)2 * 18 = 389mW
Total Power Dissipation
•Total Power
= Power (core)MAX + Power (200MHz)
= 176.7mW + 389mW
= 565.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 53.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.566W * 53.5°C/W = 115.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will vary depending on the number of loaded outputs, supply voltage, air flow and the type of board
(multi-layer).
Table 6. Thermal Resistance θJA for 32 Lead LQFP, Forced Convection
θJA by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 53.5°C/W 48.0°C/W 44.0°C/W
ICS83918AYI REVISION B AUGUST 17, 2010 15 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 32 Lead LQFP
Transistor Count
The transistor count for ICS83918I is: 909
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 53.5°C/W 48.0°C/W 44.0°C/W
ICS83918AYI REVISION B AUGUST 17, 2010 16 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32 Lead LQFP
Table 8. Package Dimensions for 32 Lead LQFP
Reference Document: JEDEC Publication 95, MS-026
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N32
A1.60
A1 0.05 0.10 0.15
A2 1.35 1.40 1.45
b0.30 0.37 0.45
c0.09 0.20
D & E 9.00 Basic
D1 & E1 7.00 Basic
D2 & E2 5.60 Ref.
e0.80 Basic
L0.45 0.60 0.75
θ0° 7°
ccc 0.10
ICS83918AYI REVISION B AUGUST 17, 2010 17 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Ordering Information
Table 9. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
83918AYI ICS83918AYI 32 Lead LQFP Tray -40°C to 85°C
83918AYIT ICS83918AYI 32 Lead LQFP 1000 Tape & Reel -40°C to 85°C
83918AYILF ICS83918AYIL “Lead-Free” 32 Lead LQFP Tray -40°C to 85°C
83918AYILFT ICS83918AYIL “Lead-Free” 32 Lead LQFP 1000 Tape & Reel -40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
ICS83918AYI REVISION B AUGUST 17, 2010 18 ©2010 Integrated Device Technology, Inc.
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Revision History Sheet
Rev Table Page Description of Change Date
B
T5A, T5B, T5D, T5E
T5D
5 - 7
7
AC Characteristic Tables - added Test Conditions to Output Duty Cycle.
2.5 AC Characteristics Table - changed Part-to-Part skew from 1.1ns max to
1.0 ns max.
8/17/10
ICS83918I Data Sheet LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
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