24LC04B/SLRVC - Microchip Technology, Inc.



1999 Microchip Technology Inc. DS21051G-page 1

FEATURES

• Single supply with operation down to 2.5V

• Low power CMOS technology

- 1 mA active current typical

- 10

A standby current typical at 5.5V

-5

A standby current typical at 3.0V

• Organized as two or four blocks of 256 bytes

(2 x 256 x 8) and (4 x 256 x 8)

• 2-wire serial interface bus, I



compatible

• Schmitt trigger, ﬁltered inputs for noise suppres-

sion

• Output slope control to eliminate ground bounce

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles guaranteed

• Data retention > 200 years

• 8-pin DIP, 8-lead or 14-lead SOIC packages

• Available temperature ranges:

DESCRIPTION

The Microchip Technology Inc. 24LC04B/08B is a 4K or

8K bit Electrically Erasable PR OM. The de vice is orga-

nized as two or four blocks of 256 x 8-bit memor y with

a 2-wire serial interface. Low voltage design permits

operation down to 2.5 volts with typical standby and

active currents of only 5

A and 1 mA respectively. The

24LC04B/08B also has a page-write capability for up to

16 bytes of data. The 24LC04B/08B is available in the

standard 8-pin DIP and both 8-lead and 14-lead sur-

face mount SOIC packages.

- Commercial (C): 0°C to +70°C

- Industrial (I): -40°C to +85°C

P ACKAGE TYPES

BLOCK DIAGRAM

SCL

SDA

14-lead

SOIC

24LC04B/08B

VSS

VCC

SCL

SDA

24LC04B/08B

VSS

VCC

SCL

SDA

PDIP

8-lead

SOIC

HV GENERATOR

EEPROM ARRAY

(2 x 256 x 8) or

(4 X 256 X 8)

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA SCL

VCC

VSS

24LC04B/08B

4K/8K 2.5V I

™

Serial EEPROMs

C is a trademark of Philips Corporation.

24LC04B/08B

DS21051G-page 2



1999 Microchip Technology Inc.

1.0 ELECTRICAL CHARA CTERISTICS

1.1 Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

...............-0.3V to V

+ 1.0V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied.................-65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins

..................................................≥

4 kV

*Notice:

Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

Ground

SDA Serial Address/Data I/O

SCL Serial Clock

WP Write Protect Input

+2.5V to 5.5V Power Supply

A0, A1, A2

No Internal Connection

TABLE 1-2: DC CHARACTERISTICS

FIGURE 1-1: BUS TIMING START/STOP

= +2.5V to +5.5V

Commercial (C): Tamb = 0˚C to +70˚C

Industrial (I): Tamb = -40˚C to +85˚C

Parameter Symbol Min Max Units

WP, SCL and SDA pins:

High level input voltage

Low level input voltage

Hysteresis of Schmitt trigger

Inputs

Low level output voltage

HYS

.7 V

—

.05 V

—

.3 V

—

.40

(Note)

= 3.0mA, V

= 2.5V

Input leakage current I

-10 10

= .1V to V

Output leakage current I

-10 10

OUT

= .1V to V

Pin capacitance

(all inputs/outputs) C

, C

OUT

—10pFV

= 5.0V (Note)

Tamb = 25˚C, Fclk = 1 MHz

Operating current I

RITE

EAD

—

—3

1mA

mA V

= 5.5V, SCL = 400 kHz

Standby current I

CCS

—

—30

100

= 3.0V, SDA = SCL = V

= 5.5V, SDA = SCL = V

WP = V

Note: This parameter is periodically sampled and not 100% tested.

TSU:STA THD:STA

VHYS

TSU:STO

START STOP

SCL

SDA



1999 Microchip Technology Inc. DS21051G-page 3

24LC04B/08B

TABLE 1-3: AC CHARACTERISTICS

FIGURE 1-2: BUS TIMING DATA

Parameter Symbol STANDARD

MODE V

= 4.5 - 5.5V

FAST MODE Units Remarks

Min Max Min Max

Clock frequency F

CLK

— 100 — 400 kHz

Clock high time T

HIGH

4000 — 600 — ns

Clock low time T

LOW

4700 — 1300 — ns

SDA and SCL rise time T

— 1000 — 300 ns (Note 1)

SDA and SCL fall time T

— 300 — 300 ns (Note 1)

START condition hold time T

STA

4000 — 600 — ns After this period the ﬁrst clock

pulse is generated

START condition setup time T

STA

4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time T

DAT

0—0—ns

Data input setup time T

DAT

250 — 100 — ns

STOP condition setup time T

STO

4000 — 600 — ns

Output valid from clock T

— 3500 — 900 ns (Note 2)

Bus free time T

BUF

4700 — 1300 — ns Time the bus must be free

before a new transmission can

start

Output fall time from V

min

to V

max T

— 250 20 +0.1

250 ns (Note 1), C

≤

100 pF

Input ﬁlter spike suppression

(SDA and SCL pins) T

— 50 — 50 ns (Note 3)

Write cycle time T

— 10 — 10 ms Byte or Page mode

Endurance — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block Mode

(Note 4)

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

speciﬁcations are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a Ti speciﬁcation for standard operation.

4: This parameter is not tested b ut guar anteed b y characterization. F or endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model whcih can be obtained on our website.

TSU:STA

TLOW

THIGH

THD:DAT TSU:DAT TSU:STO

THD:STA TBUF

TAA

TSP

THD:STA

SCL

SDA

OUT

24LC04B/08B

DS21051G-page 4  1999 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

The 24LC04B/08B supports a Bi-directional 2-wire bus

and data transmission protocol. A device that sends

data onto the bus is deﬁned as transmitter, and a

device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access , and gener-

ates the START and STOP conditions, while the

24LC04B/08B works as slave. Both, master and slave

can operate as transmitter or receiver but the master

device determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been deﬁned:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the cloc k line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

deﬁned (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition.

All commands must be preceded by a START condi-

tion.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a ST OP condition. All

operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last 16

will be stored when doing a write operation. When an

ov erwrite does occur it will replace data in a ﬁrst in ﬁrst

out fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

The device that acknowledges, has to pull down the

SD A line during the ac kno wledge cloc k pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the sla ve must lea ve the data line HIGH to enable

the master to generate the STOP condition.

Note: The 24LC04B/08B does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A) (B) (D) (D) (A)(C)

START

CONDITION ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

 1999 Microchip Technology Inc. DS21051G-page 5

24LC04B/08B

3.6 Device Addressing

A control byte is the ﬁrst byte received following the

start condition from the master device . The control b yte

consists of a 4-bit control code, for the 24LC04B/08B

this is set as 1010 binary f or read and write operations.

The next three bits of the control byte are the block

select bits (B2, B1, B0). B2 is a don't care for both the

24LC04B and 24LC08B; B1 is a don't care for the

24LC04B. They are used by the master device to

select which of the two or f our 256 word bloc ks of mem-

ory are to be accessed. These bits are in effect the

most signiﬁcant bits of the word address.

The last bit of the control byte deﬁnes the operation to

be performed. When set to one a read operation is

selected, when set to zero a write operation is selected.

Following the start condition, the 24LC04B/08B moni-

tors the SDA bus checking the device type identiﬁer

being transmitted, upon a 1010 code the slave device

outputs an acknowledge signal on the SDA line.

Depending on the state of the R/W bit, the 24LC04B/

08B will select a read or write operation.

Operation Control

Code Block Select R/W

Read 1010 Block Address 1

Write 1010 Block Address 0

FIGURE 3-2: CONTROL BYTE

ALLOCATION

SLAVE ADDRESS

X = Don’t care. B1 is don’t care f or 24LC04B.

1010XB1B0

R/W A

START READ/WRITE

24LC04B/08B

DS21051G-page 6  1999 Microchip Technology Inc.

4.0 WRITE OPERATION

4.1 Byte Write

Following the start condition from the master, the

de vice code (4 bits), the b loc k address (3 bits), and the

R/W bit which is a logic low is placed onto the bus by

the master transmitter. This indicates to the addressed

slav e receiver that a byte with a w ord address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore the next byte transmitted

by the master is the word address and will be written

into the address pointer of the 24LC04B/08B. After

receiving another acknowledge signal from the

24LC04B/08B the master device will transmit the data

word to be written into the addressed memory location.

The 24LC04B/08B acknowledges again and the mas-

ter generates a stop condition. This initiates the inter-

nal write cycle, and during this time the 24LC04B/08B

will not generate acknowledge signals (Figure 4-1).

4.2 Page Write

The write control byte, word address and the ﬁrst data

byte are transmitted to the 24LC04B/08B in the same

wa y as in a b yte write. But instead of generating a stop

condition the master transmits up to 16 data bytes to

the 24LC04B/08B which are temporarily stored in the

on-chip page buff er and will be written into the memory

after the master has transmitted a stop condition. After

the receipt of each word, the four lower order address

pointer bits are internally incremented by one. The

higher order seven bits of the word address remains

constant. If the master should transmit more than 16

words prior to generating the stop condition, the

address counter will roll over and the previously

received data will be o verwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 4-2).

Note: Page write operations are limited to writing

bytes within a single physical page, regard-

less of the number of bytes actually being

written. Physical page boundaries start at

addresses that are integer multiples of the

page buffer size (or Ôpage sizeÕ) and end at

addresses that are integer multiples of

[page size - 1]. If a page write command

attempts to write across a physical page

boundary, the result is that the data wraps

around to the beginning of the current page

(overwriting data previously stored there),

instead of being written to the next page as

might be expected. It is therefore neces-

sary for the application software to prevent

page write operations that would attempt to

cross a page boundary.

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: PAGE WRITE

S P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE WORD

ADDRESS DATA

S P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE WORD

ADDRESS (n) DATA n DATA n + 15 S

DATA n + 1

 1999 Microchip Technology Inc. DS21051G-page 7

24LC04B/08B

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed wr ite cycle. ACK polling can

be initiated immediately. This involves the master

sending a start condition followed by the control byte f or

a write command (R/W = 0). If the device is still busy

with the write cycle, then no A CK will be returned. If the

cycle is complete, then the device will retur n the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for ﬂow diagram.

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

6.0 WRITE PROTECTION

The 24LC04B/08B can be used as a serial ROM when

the WP pin is connected to VCC. Programming will be

inhibited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

7.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slav e address is set to one. There are three basic types

of read operations: current address read, random

read, and sequential read.

7.1 Current Address Read

The 24LC04B/08B contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by one. Therefore, if the previous

access (either a read or write operation) was to

address n, the next current address read operation

would access data from address n + 1. Upon receipt of

the slave address with R/W bit set to one, the

24LC04B/08B issues an acknowledge and transmits

the 8-bit data word. The master will not acknowledge

the transf er b ut does generate a stop condition and the

24LC04B/08B discontinues transmission (Figure 7-1).

7.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perfor m

this type of read operation, ﬁrst the word address m ust

be set. This is done by sending the w ord address to the

24LC04B/08B as part of a write operation. After the

word address is sent, the master generates a start con-

dition following the acknowledge. This terminates the

write operation, but not before the internal address

pointer is set. Then the master issues the control byte

again but with the R/W bit set to a one. The 24LC04B/

08B will then issue an acknowledge and transmits the

8-bit data word. The master will not acknowledge the

transfer but does generate a stop condition and the

24LC04B/08B discontinues transmission (Figure 7-2).

7.3 Sequential Read

Sequential reads are initiated in the same wa y as a ran-

dom read e xcept that after the 24LC04B/08B transmits

the ﬁrst data byte, the master issues an acknowledge

as opposed to a stop condition in a random read. This

directs the 24LC04B/08B to transmit the next sequen-

tially addressed 8-bit word (Figure 7-3).

To provide sequential reads the 24LC04B/08B contains

an internal address pointer which is incremented by

one at the completion of each operation. This address

pointer allows the entire memory contents to be serially

read during one operation.

7.4 Noise Protection

The 24LC04B/08B employs a VCC threshold detector

circuit which disables the internal erase/write logic if

the VCC is below 1.5 volts at nominal conditions.

The SCL and SD A inputs hav e Schmitt trigger and ﬁlter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

24LC04B/08B

DS21051G-page 8  1999 Microchip Technology Inc.

FIGURE 7-1: CURRENT ADDRESS READ

FIGURE 7-2: RANDOM READ

FIGURE 7-3: SEQUENTIAL READ

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE DATA n

S P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS (n) CONTROL

BYTE

TDATA (n)

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

8.0 PIN DESCRIPTIONS

8.1 SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pullup

resistor to VCC (typical 10KΩ for 100 kHz, 2 KΩ for

400 kHz).

F or normal data transf er SDA is allo wed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

8.2 SCL Serial Clock

This input is used to synchronize the data transf er from

and to the device.

8.3 WP

This pin must be connected to either VSS or VCC.

If tied to VSS, normal memory operation is enabled

(read/write the entire memory).

If tied to VCC, WRITE operations are inhibited. The

entire memory will be write-protected. Read opera-

tions are not affected.

This feature allows the user to use the 24LC04B/08B

as a serial ROM when WP is enabled (tied to VCC).

8.4 A0, A1, A2

These pins are not used by the 24LC04B/08B. They

may be left ﬂoating or tied to either VSS or VCC.

 1999 Microchip Technology Inc. DS21051G-page 9

24LC04B/08B

NOTES:

24LC04B/08B

DS21051G-page 10  1999 Microchip Technology Inc.

NOTES:

24LC04B/08B

24LC04B/08B Product Identiﬁcation System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factor y o r the listed

sales ofﬁces.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales ofﬁce

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notiﬁcation System

Package: P = Plastic DIP (300 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

SN = Plastic SOIC (150 mil Body), 8-lead

SM = Plastic SOIC (207 mil Body), 8-lead

Temperature Blank = 0°C to +70°C

Range: I= -40°C to +85°C

Device: 24LC04B 4K I2C Serial EEPROM

24LC04BT 4K1 2C Serial EEPROM (Tape and Reel)

24LC08B 8K1 2C Serial EEPROM

24LC04BT 8K 12C Serial EEPROM

(

Tape and Reel

)

24LC04B/08B – /P

 1999 Microchip Technology Inc. DS21051G-page 11

Information cont ai ned in this publication reg ardi ng device app l icat i ons and the like is i nte nded for sugge sti on onl y and may be superseded by u pdat es. No representation or warranty is given and no liability is assumed

by Microchip Tec hnology Incor porated with respec t to the accurac y or use of such informa tion, or infri ngement of patent s or other int ellectual proper ty rights aris ing from such use or othe rwise. Use of Microchip’ s products

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logo and name are registered trade ma rks of Microchip Technol ogy Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of t hei r res pective comp ani es.

 1999 Microchip Technology Inc.

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Arizona Microchip Technology SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

Tel: 39-039-65791-1 Fax: 39-039-6899883

11/15/99

WORLDWIDE SALES AND SERVICE

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.