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IXLD02SI
Differential Ultra Fast Laser Diode Driver
General Description
IXLD02SI Data Sheet
Figure 1 - Functional Diagram
The IXLD02 is an ultra high-speed differential laser diode
driver designed specically to drive single junction laser
diodes. Complementary sink outputs are provided via a
low inductance multi-pin topology. These two signals make
their transitions at the same time with transition times in
the picoseconds. This technique provides the highest pos-
sible slew rate across the diode.
These performance features are combined with frequen-
cy agility to a maximum operating frequency of 17MHz,
a minimum pulse width of <1.5ns and rise and fall times
of approximately 600ps. In addition, the pulse width and
the current programming can be modulated in real time to
>10MHz. The IXLD02 is assembled in a high power SO-28
surface mount package.
For additional operational instructions, see the IXLD02
Evaluation Board application note on the IXYSRF wesite at
www.ixysrf.com.
Features
• Ultra Fast Pulsed Current Sink
• 17MHz Max Operating Frequency
• <1.5ns Minimum Pulse Width
• 600ps Rise and Fall Times
• Pulse Width and Frequency Agile
• Real Time Electronic Programming of
Current and Pulse Width
• Low Inductance High Power Package
Design
• Simultaneous Frequency, Pulse Width
and Amplitude Modulation
Applications
• High Speed Laser Diode Drivers
• Low Power Ultra Fast Line Drivers
• Differential Power Drivers
• Pulse Generators
• High Speed High Frequency Modulators
OUT SINK
OUTB SINK
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Absolute Maximum Ratings (Note 1)
Note 1: Operating the device beyond parameters with listed “Absolute Maximum Ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do
not guarantee specic performance limits. The guaranteed specications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD proce-
dures when handling and assembling this component.
Name Denition Min Typ Max Units Test Conditions
VDD Logic supply voltage input -0.4 5.5 V
VDDA Analog bias supply voltage input -0.4 5.5 V
VTT Internal bias voltage input -0.4 VDDA/2 VDDA+.5 V
IBI Internal bias current input -10 0.1 10 mA
VIBI Applied IBI terminal voltage -0.4 VDDin+0.5 V
IPW Pulse width programming
current input
-10 0.1 10 mA
VIPW Applied IPW terminal voltage -0.4 VDDin+0.5 V
IOP Output sink current programming
input
-10 1 10 mA
VIOP Applied IOP terminal voltage -0.4 VDDin+0.5 V
VPDN Power-down logic input -0.4 VDDin+0.5 V
VRST Reset logic input -0.4 VDDin+0.5 V
VFIN Pulse frequency logic input -0.4 VDDin+0.5 V
IOUT Output sink pulse current -0.1 3 ANote 2
VOUT True ouput voltage -0.4 9 V
IOUTB Complement
output sink pulse current
-0.1 3 ANote 2
VOUTB Complement
output voltage
-0.4 9 V
TC Device Case Temperature -40 25 85 oC Measured at the
bottom of the
SO28 package
heat slug insert
PDPackage power dissipation @
Tc=85C
32 Watts SO28 package
heat slug insert
held at TC=85oC
RTHJC Thermal resistance, junction to
case
2 oC/W
TJJunction Temperature 150 oC
TS Storage temperature -55 150 oC
TLLead temperature (soldering, 10
sec)
300 oC
Ordering Information
Part Number Package Type Temp Range Grade
IXLD02SI 28-Pin SOIC -40°C to +85°C Industrial
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Recommended Operating Conditions
Unless otherwise noted, VDD=VDDA=5V, TC=25C
Name Denition Min Typ Max Units Test Conditions
VDD Logic supply input voltage 4.5 5.5 V
VDDA Analog bias supply input
voltage
4.5 5.5 V
VTT Internal bias voltage input 2 VDDA/2 3 V Measured with
Zin>10meg DVM
RVTT VTT terminal resistance 30 50 70 Kohms Measured with
VDDin=VDDA=0V
IIBI Internal bias current input
range
10 100 300 uA External current
source between
VDDA and IBI termi-
nals
VIBI Measured IBI terminal
voltage
0.6 1.7 V IIBI=100uA
IIPW Pulse width programming
current input
range
-1 100 400 uA External current
source between
VDDA and IPW ter-
minals
VIPW Measured IPW terminal
voltage
0.6 1.7 V IIPW=100uA
tPW IOUT=2A peak, Output sink
current pulse width
1 ns IIBI=400uA,
IIPW=300uA,
IIOP=1mA
IIOP OUT and OUTB output
sink current, IOUT
programming current
0 1 3 mA External current
source between
VDDA and IOP termi-
nals.
VIOP Measured IOP terminal
voltage
0.6 1.7 V IBI=100uA
IOUT/IIOP Output current to pro-
gramming current gain
1800 2000 2200 I/I IIOP=1mA
VOUT=VOUTB=10V
VIH Logic input high threshold
for PDN, RST, &
FIN inputs
0.7
*VDD
V
VIL Logic input high threshold
for PDN, RST, &
FIN inputs
.3*VDD V
ILIN Logic input bias current for
PDN, RST, &
FIN inputs
-10 10 uA For logic inputs, PDN,
RST, & FIN
held at:-
0.5V<VLIN<VDD
tPDN
disable
IXLD02 power down delay,
VPDN logical low
to high transition
50 ns
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tPDN
enable
IXLD02 power up delay,
VPDN logical high to
low transition
30 ns
tRST. IXLD02 reset logic delay,
VRST logical low to
high transition
100 ns
tRST. IXLD02 reset logic delay,
VRST logical low to
high transition
100 ns
tFIN IXLD02 pulse frequency
input, VFIN, logical
low to high transition to
IOUT pulse delay
50 ns IIBI=400uA, IIPW=300uA,
IIOP=1mA
fFINmax Maximum pulse frequen-
cy, FIN, logic input
17 MHz IIBI=400uA, IIPW=300uA,
IIOP=1mA
IOUT Peak pulse sink current 1.6 2 2.4 A
Note 2
IIBI=400uA, IIPW=300uA,
IIOP=1mA,
VOUT=VOUTB=10V
tRRise time 600 ps
tF Fall time 600 ps
TONDLY On-time propagation delay 30 ns
TOFFDLY Off-time propagation delay 30 ns
PWmax Pulse width maximum >1 us
TjJitter <300 ps
VOUT OUT terminal voltage 5 7 V IIBI=400uA, IIPW=300uA,
IIOP=1mA,
1.4A<IOUT<2.6A peak
IOUTB Minimum complement sink
pulse current OUTB.
0 0.2 0.4 AIIBI=400uA, IIPW=300uA,
IIOP=1mA.,
VOUT=VOUTB=10V
VOUTB OUTB terminal voltage 8 7 V IIBI=400uA, IIPW=300uA,
IIOP=1mA,
0A<IOUT<0.6A minimum
Note 2: The IXLD02 does not provide any output voltage or current, rather it sinks
current by manipulating the output SINK MOSFETs in a linear manner. The apparent
resistance of the SINK MOSFETs are typically used with external resistors to form
two voltage divider networks, one at the anode and one at the cathode of the diode.
In order to maintain a nominal reverse and forward diode bias, the external resistors
need to be within a certain range of values relative to the resistance presented by
the SINK MOSFETs. This range of values however limits the maximum current deliv-
ered to the diode and is well below the maximum current level that SINK MOSFETs
can actually sink, upwards of 1A is common in practice. Please refer to the EVLD02
application note for further information.
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Pin Description
Pin Congurations And Package Outline
SYM
INCHES MILLIMETERS
MIN MAX MIN MAX
A.093 .104 2.35 2.65
A1 .004 .012 .10 .30
B .013 .020 .33 .51
C .009 .013 .23 .32
D .697 .713 17.70 18.10
E .291 .299 7.40 7.60
e .050 BSC 1.27 BSC
H .394 .419 10.00 10.65
h .010 .029 .25 .75
L .016 .050 .40 1.27
0O8O0O8O
Bottom-side heat sinking metalization
NOTE: Bottom-side heat sinking metalization is connected to ground
Pins Name Description
1, 2, 13, 14 VDD This pin is a high current, low inductance pin designed to accept peaks
of 2Amps at 5V.
3VDDA This is a low current analog power input. Circuit components sensitive
to the noise present on VDD in are supplied by this pin.
4 VTT This pin is the 1/2VDDA internal analog comparator reference point.
5GNDA Low current, low noise analog return. Noise sensitive circuit
components are returned here.
6 IBI The current, IIBI, owing into the IBI pin acts as a baseline current with
respect to IIPW current to compensate for internal delays. See Figure 2
7 IOP A current, IIOP, into the IOP pin programs the laser diode output
switches, pins 19 through 24. The program ratio is 1:1000X. This
means a 1mA current will produce 1Amp. See Figure 2.
8IPW A current, IIPW
, owing into the IPW pin determines the output current
pulse width, tPW , w ith respect to IIBI. If IIPW=IIBI, the pulse width is 0. As
IIPW approaches IIBI but less than IIBI, the pulse width becomes nonzero.
See Figure 2 for tPW as a function of IIBI and IIPW.
9 PDN A TTL high on this pin will power down the device so that only leakage
current will ow from VDD to DGND. A TTL low will turn on the device
within 30ns. See Figure 3.
10 RST A system reset pin, which initializes the device so that it starts in a
predetermined initial state.
11 DGND This pin is the return for the input logic, IIBI, IIOP
, and IIPW currents. It is
internally connected to the other grounds, AGND or GND, through the
substrate.
12 FIN With PDN low, a positive edge of a TTL compatible signal here will
produce the pulse current output available at the OUT and a
complement of it at OUTB pins. Refer to Figure 3 for FIN and PDN
timing.
15, 16, 17, 18 ,25, 26, 27, 28 GND Output ground pins designed for low inductance.
19, 20.
21
OUT True laser d iode drive sink output. Designed for low inductance and
output voltage compliance to +7V.
22, 23,
24
OUTB Complementary laser diode drive sink output. Designed for low
inductance and output voltage compliance to +7V.
15
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Figure 2 is an illustration of the pulse width vs. programming current. The programming current is typically a DC
level, however it could just as well be a time varying signal. The bandwidth of this portion of the IXLD02 is equi-
valent to the maximum operating frequency of 17MHz. For the fastest response time this pin 8 (IPW) should be
driven from a low source impedance.
Figure 2 - Programmed IOUT pulse width, tPW as a function of IIPW and IIBI
Figure 3 - Control Gate Timing Diagram
Figure 3 is a timing chart for the IXLD02. The proper gating of the IXLD02 is extremely important. The device is
capable of 2A of current and may consume in excess of 3A during the pulse. If the supply voltage is at 7V with
3A of current, the total power dissipated is 21W. Therefore ample heat sinking must be provided, and/or the duty
cycle must be limited so that the power dissipation capability of the device is not exceeded.
The Power Up Gate (PDN) is applied to activate the device. Time interval “A” can be >30ns. At the end of this
time period the control gate “B” (FIN), can be applied. The range of “B” is from 1ns to several µs. The maximum
frequency 1/C is approximately 17MHz.
Programming Current
tpw Pulse width
POWER UP GATE
PDN
LASER CONTROL
PULSE FIN
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Figure 4 illustrates the Duty Cycle (DC), FIN and PDN relation ships. The PDN command must be in a TTL “High”
state 30ns prior to the rst FIN pulse. It must stay in this state for the duration of the laser light burst, T1 to T2.
The Duty cycle is dened as:
1T3T
1T2T
DC
−
−
=
Power in the IC is: Total DC Power x Duty Cycle
Figure 4 - Duty Cycle
Figure 5 - IPW And IOP Modulation
Figure 5 illustrates the simultaneous modulation of both the IPW control current and the IOP control current. The
FIN frequency in this gure is held constant. At T0 the IPW and the IOP signals are near zero, both begin to ramp
up at T1 and reach their maximums at T2. As illustrated, the output current rises in amplitude with the increasing
IOP and the pulse width widens with the IPW ramp.
An additional mode of modulation can be added to the two above by also modulating the frequency of the FIN
signal. This will allow three mode of simultaneous modulation. The three modes do not have to be used together;
each is fully independent. The obvious caveat is that the pulse width must be consistent with the chosen frequency.
This agility provides the designer with a broad range of design choices.
Doc #9200-0258 Rev 2
Duty Cycle