DIFFERENTIAL-TO-0.7V DIFFERENTIAL
PCI EXPRESS™ JITTER ATTENUATOR
ICS871004I-04
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 1 ICS871004AGI-04 REV A JANUARY 17, 2008
PRELIMINARY
GENERAL DESCRIPTION
The ICS871004I-04 is a high performance
Differential-to-0.7V Differential Jitter Attenuator
designed for use in PCI Express™ systems. In some
PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are
generated from a low bandwidth, highphase noise PLL
frequency synthesizer. In these systems, a jitter attenuator may
be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer and
from the system board. The ICS871004I-04 has 3 PLL
bandwidth modes: 200kHz, 400kHz and 800kHz. The 200kHz
mode will provide maximum jitter attenuation, but with higher
PLL tracking skew and spread spectrum modulation from the
motherboard synthesizer may be attenuated. The 400kHz
provides an intermediate bandwidth that can easily track tri-
angular spread profiles, while providing good jitter attenuation.
The 800kHz bandwidth provides the best tracking skew and
will pass most spread profiles, but the jitter attenuation will not
be as good as the lower bandwidth modes. The ICS871004I-
04 can be set for different modes using the F_SEL pins as
shown in Table 3C.
The ICS871004I-04 uses IDT’s 3rd Generation FemtoClockTM PLL
technology to achieve the lowest possible phase noise. The device
is packaged in a 24 Lead TSSOP package, making it ideal for
use in space constrained applications such as PCI Express add-
in cards.
Features
•Four 0.7V differential output pairs
•One differential clock input
•CLK and nCLK supports the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
•Output frequency range: 98MHz - 640MHz
•Input frequency range: 98MHz - 128MHz
•VCO range: 490MHz - 640MHz
•Cycle-to-cycle jitter: 19ps (typical)
•Additive phase jitter, RMS: 0.23ps (typical)
•3.3V operating supply
•Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
HiPerClockS™
ICS
Q0
nQ0
BLOCK DIAGRAM
BW_SEL[1:0]
0 0 = PLL Bandwidth: ~200kHz
0 1 = PLL Bandwidth: ~400kHz (default)
1 0 = PLL Bandwidth: ~800kHz
1 1 = PLL BYPASS
PLL BANDWIDTH
0 0 ÷5
(default)
0 1 ÷4
1 0 ÷2
1 1 ÷1
÷5
VCO
490 - 640MHz
Phase
Detector
2
2
-
+
M
U
X
Control
Logic
Pulldown
OE
F_SEL[1:0]
BW_SEL[1:0]
CLK
nCLK
MR
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pulldown
Pulldown
Pullup
Pullup
PIN ASSIGNMENT
ICS871004I-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQ0
nQ2
Q2
VDD
IREF
GND
MR
BW_SEL0
VDDA
F_SEL0
VDD
OE
1
2
3
4
5
6
7
8
9
10
11
12
Q0
VDD
Q1
nQ1
Q3
nQ3
BW_SEL1
F_SEL1
GND
GND
nCLK
CLK
24
23
22
21
20
19
18
17
16
15
14
13
IREF
Pulldown:Pullup
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 2 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
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42,10Q,0QntuptuO.slevelecafretnisserpxEICP.riaptuptuolaitnereffiD
3,22Q,2QntuptuO.slev
elecafretnisserpxEICP.riaptuptuolaitnereffiD
32,11,4V
DD
rewoP.nipylppuseroC
5FERItupnI
574(rotsisernoisicerpdexifA Ωasedivorpdnuorgotnipsihtmorf)
dnaxAQn/xAQedom-tn
erruclaitnereffidrofdesutnerrucecnerefer
.stuptuokcolcxBQn/xBQ
61,51,6DNGrewoP.dnuorgylppusrewoP
7RMtupnInwodl
luP
erasredividlanretnieht,HGIHcigolnehW.teseRretsaMHGIHevitcA
stuptuodetrevniehtdnawologot)xQn(stuptuo
eurtehtgnisuacteser
stuptuoehtdnasredividlanretnieht,WOLcigolnehW.hgihogot)xQ(
.slevelecafretniLTTVL/SO
MCVL.delbaneera
80LES_WBtupnIpulluP .slevelecafretniLTTVL/SOMCVL.tupnihtdiwdnaBLLPstceleS
.B3elbaTeeS
9V
ADD
rewoP.nipylppusgolanA
,01
71
,0LES_F
1LES_F tupnInwodlluP .slevelecafretniLTTVL/SOMCVL.sniptcelesycneuqerF
.C3
elbaTeeS
21EOtupnIpulluP eht,WOLnehW.evitcaerastuptuoeht,HGIHnehW.nipelbanetuptuO
.slevelecafretniLTTVL/SOM
CVL.etatsecnadepmihgihanierastuptuo
31KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
41KLCntupnIpulluP.tu
pnikcolclaitnereffidgnitrevnI
811LES_WBtupnInwodlluP .slevelecafretniLTTVL/SOMCVL.tupnihtdiwdnaBLLPstceleS
.B3elbaTeeS
02,913Q,3QntuptuO.slevelecafretnisserpxEICP.riaptuptuolaitnereffiD
22,121Q,1QntuptuO.slevelecafre
tnisserpxEICP.riaptuptuolaitnereffiD
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 3 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL
TABLE 3C. FREQUENCY SELECT FUNCTION TABLE
stupnIstuptuO
EO3Q:0Q3Qn:0Qn
0ZiHZiH
1delbanEdelbanE
stupnI htdiwdnaBLLP
1LES_WB0LES_WB
00 zHk002~
01 )tluafed(zHk004~
10 zHk008~
11 SSAPYBLLP
stupnI egnaRycneuqerFtuptuO
)zHM(
ycneuqerFtupnI1LES_F0LES_FeulaVrediviD
001005 )tluafed(001
001014 521
001102 052
001111 005
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 4 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, VO-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA 82.3°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, TA = -40°C TO 85°C
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DD
egatloVylppuSeroC 531.33.3564.3V
V
ADD
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DD
I–
ADD
01* Ω3.3V
DD
V
I
DD
tnerruCylppuSrewoP DBTAm
I
ADD
tnerruCylppuSgolanA DBTAm
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCV
DD
V=
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V564.3=051Aµ
,KLCnV
DD
V=
NI
V564.3=5 Aµ
I
LI
tnerruCwoLtupnI KLCV
DD
V=
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V564.3=051Aµ
KLCnV
DD
V=
NI
V564.3=051-Aµ
V
PP
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V
RMC
2,1ETON;egatloVtupnIedoMnommoC 5.0+DNGV
DD
58.0-V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.
VtaKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
DD
.V3.0+
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V
HI
tupnI
egatloVhgiH
,EO,RM
,1LES_F.0LES_F 2V
DD
3.0+V
1LES_WB,0LES_WBV
DD
3.0-V
DD
3.0+V
V
LI
tupnI
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,EO,RM
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1LES_WB,0LES_WB3.0-3.0V
I
HI
tupnI
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EO,0LES_WBV
DD
V=
NI
V564.3=5Aµ
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1LES_F.0LES_F V
DD
V=
NI
V564.3=051Aµ
I
LI
tupnI
tnerruCwoL
EO,0LES_WBV
DD
V,V564.3=
NI
V0=051-Aµ
,1LES_WB,RM
1LES_F.0LES_F V
DD
V,V564.3=
NI
V0=5-Aµ
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 5 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, TA = -40°C TO 85°C
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t
DP
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t
tij ;SMR,rettiJesahPevitiddAreffuB
noitceSrettiJesahPevitiddAotrefeR
edoMSSAPYBniLLP
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32.0sp
t
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t
L
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HGIH
hgiHegatloV 066058Vm
V
WOL
woLegatloV 051-Vm
V
SVO
toohsrevO,egatloV.xaM V
HGIH
3.0+V
V
SDU
toohsrednU,egatloV.niM 3.0-V
V
br
egatloVkcabgniR 2.0V
V
SSORC
egatloVgnissorCetulosbA 052055Vm
ΔV
SSORC
VfonoitairaVlatoT
SSORC
segdellarevo 041Vm
t
R
t/
F
emiTllaF/esiRtuptuO neewtebderusaem
525.0ot571.0 574sp
Δt
R
/Δt
F
noitairaVemiTllaF/esiR 521sp
t
MFR
gnihctaMllaF/esiR 521sp
cdoelcyCytuDtuptuO 05%
.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitne
reffidehtmorfderusaeM:1ETON
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:2ETON
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 6 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
ADDITIVE PHASE JITTER
Additive Phase Jitter @ 100MHz
(12kHz to 20MHz) = 0.23ps typical
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 7 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
CYCLE-TO-CYCLE JITTER
DIFFERENTIAL INPUT LEVEL3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT - TBD
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
VDD
➤
➤
➤
➤
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
Q0:Q3
nQ0:nQ3
475Ω
Measurement
Point
33Ω100Ω
100Ω
33Ω
Measurement
Point
49.9Ω
49.9Ω
HSCL
GND
2pF
2pF
VDD
VDDA
DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD
SE MEASUREMENT POINTS FOR RISE/FALL TIME MATCHING
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 8 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
PARAMETER MEASUREMENT INFORMATION, CONTINUED
SE MEASUREMENT POINTS FOR DELTA CROSS POINT
SE MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL T IME
DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 9 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
APPLICATION INFORMATION
Figure 2
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
POWER SUPPLY FILTERING T ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS871004I-
04 provides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. VDD, VDDA and VDDO
should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin.
Figure 1
illustrates this for a generic VDD pin and also
shows that VDDA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VDDA pin. FIGURE 1. POWER SUPPLY FILTERING
10Ω
VDDA
10μF
.01μF
3.3V
.01μF
VDD
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
DIFFERENTIAL OUTPUTS
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 10 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements.
Figures 3A to 3F
show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
HIPERCLOCKS LVHSTL DRIVER
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
HCSL
*R3 33
*R4 33
CLK
nCLK
2.5V 3.3V
Zo = 50Ω
Zo = 50Ω
HiPerClockS
Input
R1
50
R2
50
*Optional – R3 and R4 can be 0Ω
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
CLK
nCLK
HiPerClockS
SSTL
2.5V
Zo = 60Ω
Zo = 60Ω
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 11 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
RECOMMENDED T ERMINATION
Figure 4A
is the recommended termination for applications
which require the receiver and driver to be on a separate PCB.
All traces should be 50Ù impedance.
FIGURE 4A. RECOMMENDED TERMINATION
Figure 6B
is the recommended termination for applications
which require a point to point connection and contain the driver
FIGURE 4B. RECOMMENDED TERMINATION
and receiver on the same PCB. All traces should all be 50Ù
impedance.
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 12 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS871004I-04 is: 1395
TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 82.3°C/W 78°C/W 75.9°C/W
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 13 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N42
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D07.709.7
ECISAB04.6
1E03.405.4
eCISAB56.0
L5
4.057.0
α°0°8
aaa--01.0
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 14 ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
TABLE 8. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
40-IGA400178SCI40IA400178SCIPOSSTdaeL42ebutC°58otC°
04-
T40-IGA400178SCI40IA400178SCIPOSSTdaeL42leer&epat0052C°58otC°04-
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Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
