1
AT49F1025
PLCC Top View
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
I/O12
I/O11
I/O10
I/O9
I/O8
GND
NC
I/O7
I/O6
I/O5
I/O4
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
I/O3
I/O2
I/O1
I/O0
OE
NC
A0
A1
A2
A3
A4
I/O13
I/O14
I/O15
CE
NC
NC
VCC
WE
NC
A15
A14
Features
•Single-voltage Operation
–5V Read
– 5V Reprogramming
•Fast Read Access Time – 35 ns
•Internal Program Control and Timer
•8K Word Boot Block with Lockout
•Fast Erase Cycle Time – 10 seconds
•Word-by-word Programming – 10 µs/Word Typical
•Hardware Data Protection
•Data Polling for End of Program Detection
•Small 10 x 14 mm VSOP Package
•Typical 10,000 Write Cycles
Description
The AT49F1024 and the AT49F1025 are 5-volt-only in-system Flash memories. Their
1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to
35 ns with power dissipation of just 275 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 µA. The
only difference between the AT49F1024 and the AT49F1025 is the package.
To allow for simple in-system reprogrammability, the AT49F1024/1025 does not
require high-input voltages for programming. Five-volt-only commands determine the
Rev. 0765I–05/01
1-megabit
(64K x 16)
5-volt Only
Flash Memory
AT49F1024
AT49F1025
Pin Configurations
Pin Name Function
A0 - A15 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O15 Data Inputs/Outputs
NC No Connect
(continued)
AT49F1024 VSOP Top View
Type 1
10 x 14 mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
NC
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
2AT49F1024/1025
0765I–05/01
read and programming operation of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the AT49F1024/1025 is performed by
erasing a block of data (entire chip or main memory block) and then programming on a
word-by-word basis. The typical word programming time is a fast 10 µs. The end of a
program cycle can be optionally detected by the Data Polling feature. Once the end of a
byte program cycle has been detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in excess of 10,000 cycles.
The optional 8K word boot block section includes a reprogramming write lockout feature
to provide data integrity. The boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is permanently protected from being erased
or reprogrammed.
Block Diagram
Device Operation READ: The AT49F1024/1025 is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high impedance state whenever
CE or OE is high. This dual line control gives designers flexibility in preventing bus
contention.
CHIP ERASE: When the boot block programming lockout feature is not enabled, the
boot block and the main memory block will erase together from the same Chip Erase
command (See Command Definitions table). If the boot block lockout function has been
enabled, data in the boot section will not be erased. However, data in the main memory
section will be erased. After a chip erase, the device will return to the read mode.
MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block
erase can be performed, which will erase all words not located in the boot block region
to an FFFFH. Data located in the boot region will not be changed during a main memory
block erase. The Main Memory Erase command is a six-bus cycle operation. The
address (5555H) is latched on the falling edge of the sixth cycle while the 30H data input
is latched on the rising edge of WE. The main memory erase starts after the rising edge
of WE of the sixth cycle. Please see main memory erase cycle waveforms. The main
memory erase operation is internally controlled; it will automatically time to completion.
WORD PROGRAMMING: Once the memory array is erased, the device is programmed
(to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming
is accomplished via the internal device command register and is a four-bus cycle
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (8K WORDS)
MAIN MEMORY
(56K WORDS)
OE
WE
CE
ADDRESS
INPUTS
VCC
GND
DATA INPUTS/OUTPUTS
I/O15 - I/O0
16
2000H
1FFFH
0000H
FFFFH
3
AT49F1024/1025
0765I–05/01
operation (please refer to the Command Definitions table). The device will automatically
generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever
occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first.
Programming is completed after the specified tBP cycle time. The Data Polling feature
may also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block
that has a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. The size of the block is 8K
words. This block, referred to as the boot block, can contain secure code that is used to
bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be
activated; the boot block’s usage as a write-protected region is optional to the user. The
address range of the boot block is 0000H to 1FFFH.
Once the feature is enabled, the data in the boot block can no longer be erased or pro-
grammed. Data in the main memory block can still be changed through the regular
programming method and can be erased using either the Chip Erase or the Main Mem-
ory Block Erase command. To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be performed. Please refer to
the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if
programming of the boot block section is locked out. When the device is in the software
product identification mode (see Software Product Identification Entry and Exit sec-
tions), a read from address location 0002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on
I/O0 is high, the program lockout feature has been activated and the block cannot be
programmed. The software product identification exit code should be used to return to
standard operation.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identifi-
cation. The manufacturer and device code is the same for both modes.
DATA POLLING: The AT49F1024/1025 features Data Polling to indicate the end of a
program or erase cycle. During a program cycle, an attempted read of the last byte
loaded will result in the complement of the loaded data on I/O7. Once the program cycle
has been completed, true data is valid on all outputs and the next cycle may begin. Data
Polling may begin at any time during the program cycle.
TOGGLE BIT: In addition to Data Polling, the AT49F1024/1025 provides another
method for determining the end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a pro-
gram cycle.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro-
grams to the AT49F1024/1025 in the following ways: (a) VCC sense: if VCC is below 3.8V
(typical), the program function is inhibited. (b) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15
ns (typical) on the WE or CE inputs will not initiate a program cycle.
4AT49F1024/1025
0765I–05/01
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex); A15 (Don’t Care).
2. The 8K word boot sector has the address range 00000H to 1FFFH.
3. Either one of the Product ID Exit commands can be used.
Command Definition (in Hex)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read 1 Addr DOUT
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Main Memory Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 30
Word Program 4 5555 AA 2AAA 55 5555 A0 Addr DIN
Boot Block Lockout(2) 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit(3) 3 5555 AA 2AAA 55 5555 F0
Product ID Exit(3) 1xxxxF0
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
5
AT49F1024/1025
0765I–05/01
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 001FH, Device Code: 0087H.
5. See details under “Software Product Identification Entry/Exit” on page 11.
Note: 1. In the erase mode, ICC is 90 mA.
DC and AC Operating Range
AT49F1024-35
AT49F1025-35
AT49F1024-45
AT49F1025-45 AT49F1024-50
AT49F1024-55
AT49F1025-55
AT49F1024-70
AT49F1025-70
Operating
Temperature (Case)
Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
Operating Modes
Mode CE OE WE Ai I/O
Read VIL VIL VIH Ai DOUT
Program(2) VIL VIH VIL Ai DIN
Standby/Write Inhibit VIH X(1) X X High-Z
Program Inhibit X X VIH
Program Inhibit X VIL X
Output Disable X VIH X High-Z
Product Identification
Hardware VIL VIL VIH
A1 - A15 = VIL, A9 = VH(3), A0 = VIL Manufacturer Code(4)
A1 - A15 = VIL, A9 = VH(3), A0 = VIH Device Code(4)
Software(5) A0 = VIL, A1 - A15 = VIL Manufacturer Code(4)
A0 = VIH, A1 - A15 = VIL Device Code(4)
DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10.0 µA
ILO Output Leakage Current VI/O = 0V to VCC 10.0 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC
Com. 100.0 µA
Ind. 300.0 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3.0 mA
ICC (1) VCC Active Current f = 5 MHz; IOUT = 0 mA 50.0 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
6AT49F1024/1025
0765I–05/01
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol Parameter
AT49F1024-35
AT49F1025-35
AT49F1024-45
AT49F1025-45 AT49F1024-50
AT49F1024-55
AT49F1025-55
AT49F1024-70
AT49F1025-70
UnitsMin Max Min Max Min Max Min Max Min Max
tACC Address to Output Delay 35 45 50 55 70 ns
tCE(1) CE to Output Delay 3545505570ns
tOE(2) OE to Output Delay025030303035ns
tDF(3)(4) CE or OE to Output Float 0 25 0 25 25 0 25 0 25 ns
tOH
Output Hold from OE,
CE or Address,
whichever occurred first
00000ns
8AT49F1024/1025
0765I–05/01
AC Word Load Waveforms
WE Controlled
CE Controlled
AC Word Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Setup Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Setup Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE)50ns
tDS Data Setup Time 50 ns
tDH, tOEH Data, OE Hold Time 0 ns
tWPH Write Pulse Width High 40 ns
t
DH
t
DS
t
AS
t
AH
t
WP
CE
ADDRESS
DATA IN
OE
t
OES
t
OEH
WE t
CS
t
CH
t
WPH
t
DH
t
DS
t
AS
t
AH
t
WP
WE
ADDRESS
DATA IN
OE
t
OES
t
OEH
CE
t
CS
t
CH
t
WPH
9
AT49F1024/1025
0765I–05/01
Program Cycle Waveforms
Main Memory or Chip Erase Cycle Waveforms
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 10H. For a main memory erase, the data should be 30H.
Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
tBP Word Programming Time 10 50 µs
tAS Address Setup Time 0 ns
tAH Address Hold Time 50 ns
tDS Data Setup Time 50 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 50 ns
tWPH Write Pulse Width High 40 ns
tEC Erase Cycle Time 3 seconds
A0-A15
OE
AA
80 NOTE 2
55 55
5555 5555 5555
AA
WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5
2AAA 2AAA
t
WPH
t
WP
CE
WE
A0-A15
DATA
t
AS
t
AH
t
EC
t
DH
t
DS
5555
10 AT49F1024/1025
0765I–05/01
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 6.
Data Polling Waveforms
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 6.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
Data Polling Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tWR Write Recovery Time 0 ns
Toggle Bit Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
11
AT49F1024/1025
0765I–05/01
Software Product Identification Entry(1)
Software Product Identification Exit(1)
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). Address Format: A15 - A0 (Hex); A15 (Don’t Care).
2. A1 - A15 = VIL.
Manufacturer Code is read for A0 = VIL.
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH
Device Code: 0087H
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE
(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
OR LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
12 AT49F1024/1025
0765I–05/01
Boot Block Lockout Enable Algorithm(1)
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). Address Format: A15 - A0 (Hex); A15 (Don’t Care).
2. Boot Block Lockout feature enabled.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
PAUSE 1 second
(2)
13
AT49F1024/1025
0765I–05/01
AT49F1024 Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
35 50 0.1 AT49F1024-35VC 40V Commercial
(0° to 70°C)
45 50 0.1 AT49F1024-45VC 40V Commercial
(0° to 70°C)
50 50 0.1 AT49F1024-50VC 40V Commercial
(0° to 70°C)
55 50 0.1 AT49F1024-55VC 40V Commercial
(0° to 70°C)
50 0.3 AT49F1024-55VI 40V Industrial
(-40° to 85°C)
70 50 0.1 AT49F1024-70VC 40V Commercial
(0° to 70°C)
50 0.3 AT49F1024-70VI 40V Industrial
(-40° to 85°C)
AT49F1025 Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
35 50 0.1 AT49F1025-35JC 44J Commercial
(0° to 70°C)
45 50 0.1 AT49F1025-45JC 44J Commercial
(0° to 70°C)
55 50 0.1 AT49F1025-55JC 44J Commercial
(0° to 70°C)
50 0.3 AT49F1025-55JI 44J Industrial
(-40° to 85°C)
70 50 0.1 AT49F1025-70JC 44J Commercial
(0° to 70°C)
50 0.3 AT49F1025-70JI 44J Industrial
(-40° to 85°C)
Package Type
44J 44-lead, Plastic J-leaded Chip Carrier Package (PLCC)
40V 40-lead, 10 mm x 14 mm, Thin Small Outline Package (VSOP)
Packaging Information
14 AT49F1024/1025
0765I–05/01
.045(1.14) X 45°PIN NO. 1
IDENTIFY
.045(1.14) X 30° - 45°.012(.305)
.008(.203)
.021(.533)
.013(.330)
.630(16.0)
.590(15.0)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
.500(12.7) REF SQ
.032(.813)
.026(.660)
.050(1.27) TYP
.022(.559) X 45° MAX (3X)
.656(16.7)
.650(16.5)
.695(17.7)
.685(17.4)SQ
SQ
*Controlling dimension: millimeters
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
40V, 40-lead, Plastic Thin Small Outline
Package (VSOP)
Dimensions in Millimeters and (Inches)*
© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
Atmel Headquarters Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Europe
Atmel SarL
Route des Arsenaux 41
Casa Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Atmel Rousset
Zone Industrielle
13106 Rousset Cedex
France
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
Atmel Smart Card ICs
Scottish Enterprise Technology Park
East Kilbride, Scotland G75 0QR
TEL (44) 1355-357-000
FAX (44) 1355-242-743
Atmel Grenoble
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex
France
TEL (33) 4-7658-3000
FAX (33) 4-7658-3480
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
Printed on recycled paper.
0765I–05/01/xM
Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
