OBSOLETE - No Longer Available TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 * * * * TIBPAL16L8' C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J PACKAGE (TOP VIEW) I I I I I I I I I GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC O I/O I/O I/O I/O I/O I/O O I Functionally Equivalent, but Faster than, Existing 20-Pin PLDs TIBPAL16L8' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE Preload Capability on Output Registers Simplifies Testing (TOP VIEW) Power-Up Clear on Registered Devices (All Register Outputs are Set Low, but Voltage Levels at the Output Pins Go High) I I I VCC O * High-Performance Operation: fmax (no feedback) TIBPAL16R' -5C Series . . . 125 MHz Min TIBPAL16R' -7M Series . . . 100 MHz Min fmax (internal feedback) TIBPAL16R' -5C Series . . . 125 MHz Min TIBPAL16R' -7M Series . . . 100 MHz Min fmax (external feedback) TIBPAL16R' -5C Series . . . 117 MHz Min TIBPAL16R' -7M Series . . . 74 MHz Min Propagation Delay TIBPAL16L8-5C Series . . . 5 ns Max TIBPAL16L8-7M Series . . . 7 ns Max TIBPAL16R' -5C Series (CLK-to-Q) . . . 4 ns Max TIBPAL16R ' -7M Series (CLK-to-Q) . . . 6.5 ns Max Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs I I I I I Security Fuse Prevents Duplication DEVICE I INPUTS 3-STATE O OUTPUTS REGISTERED Q OUTPUTS I/O PORT S 'PAL16L8 10 2 0 6 'PAL16R4 8 0 4 (3-state buffers) 4 'PAL16R6 8 0 6 (3-state buffers) 2 'PAL16R8 8 0 8 (3-state buffers) 0 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I/O I/O I/O I/O I/O I GND I O I/O * Pin assignments in operating mode description These programmable array logic devices feature high speed and functional equivalency when compared with currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically results in a more compact circuit board. The TIBPAL16' C series is characterized from 0C to 75C. The TIBPAL16' M series is characterized for operation over the full military temperature range of -55C to 125C. These devices are covered by U.S. Patent 4,410,987. IMPACT-X is a trademark of Texas Instruments Incorporated. PAL is a registered trademark of Advanced Micro Devices Inc. Copyright 1992, Texas Instruments Incorporated This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 OBSOLETE - No Longer Available TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 TIBPAL16R4' C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J PACKAGE TIBPAL16R4' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW) 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC I/O I/O Q Q Q Q I/O I/O OE TIBPAL16R6' C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J PACKAGE I I I I I 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 TIBPAL16R6' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW) 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC I/O Q Q Q Q Q Q I/O OE TIBPAL16R8' C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J PACKAGE I I I I I 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I GND 1 I I CLK VCC I/O (TOP VIEW) CLK I I I I I I I I GND (TOP VIEW) 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 I I CLK VCC Q 20 2 VCC Q Q Q Q Q Q Q Q OE I I I I I Pin assignments in operating mode 2 POST OFFICE BOX 655303 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I GND 1 Q Q Q Q Q TIBPAL16R8' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW) CLK I I I I I I I I GND I/O Q Q Q Q OE I/O I/O 19 OE I/O Q 20 2 * DALLAS, TEXAS 75265 OE Q Q 1 I GND CLK I I I I I I I I GND I I CLK VCC I/O (TOP VIEW) Q Q Q Q Q OBSOLETE - No Longer Available TIBPAL16L8-5C, TIBPAL16R4-5C TIBPAL16L8-7M, TIBPAL16R4-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 functional block diagrams (positive logic) TIBPAL16L8' & 32 X 64 16 x I 10 16 6 16 EN 1 7 O 7 O 7 I/O 7 I/O 7 I/O 7 I/O 7 I/O 7 I/O 6 TIBPAL16R4' OE CLK EN 2 C1 & 32 X 64 16 x I 8 1 8 I=0 2 Q 1D 8 Q 8 Q 8 Q 16 4 4 16 EN 1 7 I/O 7 I/O 7 I/O 7 I/O 4 4 denotes fused inputs POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 OBSOLETE - No Longer Available TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 functional block diagrams (positive logic) TIBPAL16R6' OE CLK EN 2 C1 & 32 X 64 16 x I 8 1 8 I=0 2 Q 1D 8 Q 8 Q 8 Q 8 Q 8 Q 16 6 2 16 EN 1 7 I/O I/O 7 2 6 TIBPAL16R8' OE CLK EN 2 C1 & 32 X 64 16 x I 8 8 1 I=0 2 8 Q 8 Q 8 Q 8 Q 8 Q 8 Q 8 Q 16 8 16 8 denotes fused inputs 4 Q 1D POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OBSOLETE - No Longer Available TIBPAL16L8-5C TIBPAL16L8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 logic diagram (positive logic) I 1 INCREMENT FIRST FUSE NUMBERS 0 I I I I I I I I 2 3 4 5 6 7 8 9 4 8 12 16 20 24 28 0 32 64 96 128 160 192 224 31 19 256 288 320 352 384 416 448 480 18 512 544 576 608 640 672 704 736 17 768 800 832 864 896 928 960 992 16 1024 1056 1088 1120 1152 1184 1216 1248 15 1280 1312 1344 1376 1408 1440 1472 1504 14 1536 1568 1600 1632 1664 1696 1728 1760 13 1792 1824 1856 1888 1920 1952 1984 2016 12 11 O I/O I/O I/O I/O I/O I/O O I Fuse number = First fuse number + Increment POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 OBSOLETE - No Longer Available TIBPAL16R4-5C TIBPAL16R4-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 logic diagram (positive logic) CLK 1 INCREMENT FIRST FUSE NUMBERS I I I I I I I I 2 3 4 5 6 7 8 9 0 4 8 12 16 20 24 28 19 256 288 320 352 384 416 448 480 18 512 544 576 608 640 672 704 736 I=0 1D 768 800 832 864 896 928 960 992 I=0 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=0 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=0 1D 17 I/O I/O Q C1 16 Q C1 15 Q C1 14 Q C1 1536 1568 1600 1632 1664 1696 1728 1760 13 1792 1824 1856 1888 1920 1952 1984 2016 12 11 Fuse number = First fuse number + Increment 6 31 0 32 64 96 128 160 192 224 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 I/O I/O OE OBSOLETE - No Longer Available TIBPAL16R6-5C TIBPAL16R6-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 logic diagram (positive logic) CLK 1 INCREMENT FIRST FUSE NUMBERS I I I I I I I I 2 3 4 5 6 7 8 9 0 4 8 12 16 20 24 28 31 0 32 64 96 128 160 192 224 19 256 288 320 352 384 416 448 480 I=0 1D 512 544 576 608 640 672 704 736 I=0 1D 768 800 832 864 896 928 960 992 I=0 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=0 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=0 1D 1536 1568 1600 1632 1664 1696 1728 1760 I=0 1D 18 I/O Q C1 17 Q C1 16 Q C1 15 Q C1 14 Q C1 13 Q C1 1792 1824 1856 1888 1920 1952 1984 2016 12 11 I/O OE Fuse number = First fuse number + Increment POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 OBSOLETE - No Longer Available TIBPAL16R8-5C TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 logic diagram (positive logic) CLK 1 INCREMENT FIRST FUSE NUMBERS I I I I I I I I 2 3 4 5 6 7 8 9 0 4 8 12 16 20 24 28 I=0 1D 256 288 320 352 384 416 448 480 I=0 1D 512 544 576 608 640 672 704 736 I=0 1D 768 800 832 864 896 928 960 992 I=0 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=0 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=0 1D 1536 1568 1600 1632 1664 1696 1728 1760 I=0 1D 1792 1824 1856 1888 1920 1952 1984 2016 I=0 1D 19 Q C1 18 Q C1 17 Q C1 16 Q C1 15 Q C1 14 Q C1 13 Q C1 12 Q C1 11 Fuse number = First fuse number + Increment 8 31 0 32 64 96 128 160 192 224 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OE OBSOLETE - No Longer Available TIBPAL16L8-5C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle. recommended operating conditions VCC VIH Supply voltage VIL IOH Low-level input voltage (see Note 2) IOL TA Low-level output current High-level input voltage (see Note 2) MIN NOM MAX UNIT 4.75 5 5.25 V 5.5 V 2 0.8 High-level output current Operating free-air temperature 0 25 V - 3.2 mA 24 mA 75 C NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester noise. Testing these parameters should not be attempted without suitable equipment. electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS VIK VOH VCC = 4.75 V, VCC = 4.75 V, II = - 18 mA IOH = - 3.2 mA VOL IOZH IOZL VCC = 4.75 V, VCC = 5.25 V, IOL = 24 mA VO = 2.7 V VCC = 5.25 V, VCC = 5.25 V, VO = 0.4 V VI = 5.5 V VCC = 5.25 V, VCC = 5.25 V, VI = 2.7 V VI = 0.4 V IOS ICC VCC = 5.25 V, VCC = 5.25 V, VO = 0.5 V VI = 0, Ci f = 1 MHz, Co f = 1 MHz, VI = 2 V VO = 2 V II IIH IIL MIN TYP MAX UNIT -0.8 - 1.5 V 2.4 2.7 0.3 - 30 -70 Outputs open V 0.5 V 100 A -100 A 100 A 25 A -250 A -130 mA 180 mA 8.5 pF 10 pF All typical values are at VCC = 5 V, TA = 25C. I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) I, I/O O, I/O with up to 4 outputs switching I, I/O O, I/O with more than 4 outputs switching tpd ten tdis I, I/O O, I/O I, I/O O, I/O TEST CONDITIONS R1 = 200 , R2 = 200 , See Figure 8 TIBPAL16L8-5CFN TIBPAL16L8-5CJ TIBPAL16L8-5CN MIN MAX MIN MAX 1.5 5 1.5 5 1.5 5 1.5 5.5 2 7 2 7 ns 2 7 2 7 ns UNIT ns PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 OBSOLETE - No Longer Available TIBPAL16R4-5C, TIBPAL16R6-5C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle. recommended operating conditions VCC VIH Supply voltage VIL IOH Low-level input voltage (see Note 2) IOL fclock Low-level output current tw Pulse duration, clock tsu th Setup time, input or feedback before clock High-level input voltage (see Note 2) MIN NOM MAX UNIT 4.75 5 5.25 V 5.5 V 2 0.8 High-level output current - 3.2 Clock frequency 0 High 4 Low 4 Hold time, input or feedback after clock V mA 24 mA 125 MHz ns 4.5 ns 0 ns TA Operating free-air temperature 0 25 75 C NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester noise. Testing these parameters should not be attempted without suitable equipment. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OBSOLETE - No Longer Available TIBPAL16R4-5C, TIBPAL16R6-5C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS VIK VOH VCC = 4.75 V, VCC = 4.75 V, II = - 18 mA IOH = - 3.2 mA VOL IOZH IOZL VCC = 4.75 V, VCC = 5.25 V, IOL = 24 mA VO = 2.7 V VCC = 5.25 V, VCC = 5.25 V, VO = 0.4 V VI = 5.5 V VCC = 5.25 V, VCC = 5.25 V, VI = 2.7 V VI = 0.4 V VCC = 5.25 V, VCC = 5.25 V, VO = 0.5 V VI = 0, II IIH IIL IOS ICC I Ci CLK/OE I/O Co Q f = 1 MHz, VI = 2 V f = 1 MHz, VO = 2 V MIN TYP MAX UNIT - 0.8 - 1.5 V 2.4 2.7 0.3 - 30 -70 Outputs open V 0.5 V 100 A -100 A 100 A 25 A - 250 A -130 mA 200 mA 7 pF 5 10 pF 7 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS TIBPAL16R4-5CFN TIBPAL16R6-5CFN MIN fmax TYP MAX without feedback 125 125 125 125 with external feedback 117 111 CLK Q CLK Internal feedback tpd ten I, I/O I/O R2 = 200 , 1.5 5 OE Q See Figure 8 1.5 6 tdis ten OE Q 1 I, I/O I/O I, I/O I/O tf tsk (o) # MIN with internal feedback (counter configuration) tpd tpd tdis tr TIBPAL16R4-5CJ TIBPAL16R6-5CJ TIBPAL16R4-5CN TIBPAL16R6-5CN 1.5 4 TYP MAX MHz 4.5 ns 3.5 ns 1.5 5 ns 1.5 6 ns 6.5 1 7 ns 2 7 2 7 ns 2 7 2 7 ns R1 = 200 , 1.5 3.5 Skew between registered outputs UNIT 1.5 1.5 ns 1.5 1.5 ns 0.5 0.5 ns All typical values are at VCC = 5 V, TA = 25C. I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation. See 'fmax Specification' near the end of this data sheet. # tsk (o) is the skew time between registered outputs. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 OBSOLETE - No Longer Available TIBPAL16R8-5C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle. recommended operating conditions VCC VIH Supply voltage VIL IOH Low-level input voltage (see Note 2) IOL fclock Low-level output current tw Pulse duration, clock tsu th Setup time, input or feedback before clock High-level input voltage (see Note 2) MIN NOM MAX UNIT 4.75 5 5.25 V 5.5 V 2 0.8 High-level output current - 3.2 Clock frequency 0 High 4 Low 4 Hold time, input or feedback after clock V mA 24 mA 125 MHz ns 4.5 ns 0 ns TA Operating free-air temperature 0 25 75 C NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester noise. Testing these parameters should not be attempted without suitable equipment. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OBSOLETE - No Longer Available TIBPAL16R8-5C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 electrical characteristics over recommended operating free-air temperature range TIBPAL16R8-5CJ TIBPAL16R8-5CN TIBPAL16R8-5CFN PARAMETER TEST CONDITIONS MIN TYP MAX - 0.8 - 1.5 MIN MAX - 0.8 - 1.5 VIK VOH VCC = 4.75 V, VCC = 4.75 V, II = - 18 mA IOH = -3.2 mA VOL IOZH VCC = 4.75 V, VCC = 5.25 V, IOL = 24 mA VO = 2.7 V IOZL II VCC = 5.25 V, VCC = 5.25 V, VO = 0.4 V VI = 5.5 V IIH IIL VCC = 5.25 V, VCC = 5.25 V, VI = 2.7 V VI = 0.4 V IOS ICC VCC = 5.25 V, VCC = 5.25 V, VO = 0.5 V VI = 0, Outputs open 8.5 6.5 f = 1 MHz, VI = 2 V 7.5 5.5 f = 1 MHz, VO = 2 V 10 8 2.4 2.7 -70 CLK/OE Co V 2.7 0.5 0.3 V 0.5 V 100 100 A -100 -100 A 100 100 A 25 25 A - 250 - 30 -130 - 30 -70 180 I Ci 2.4 0.3 UNIT TYP - 250 A -130 mA 180 mA pF pF switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS TIBPAL16R8-5CFN MIN fmax TYP MAX TIBPAL16R8-5CJ TIBPAL16R8-5CN MIN without feedback 125 125 with internal feedback (counter configuration) 125 125 with external feedback 117 111 CLK Q with up to 4 outputs switching CLK Q with more than 4 outputs switching tpd R1 = 200 , R2 = 200 , See Figure 8 TYP UNIT MAX MHz 1.5 4 1.5 4 1.5 4 1.5 4.5 ns tpd CLK Internal feedback ten OE Q 1.5 tdis OE Q 1 3.5 6 1.5 6.5 1 3.5 ns 6 ns 7 ns tr 1.5 1.5 ns tf 1.5 1.5 ns 0.5 0.5 ns tsk (o)# Skew between outputs All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation. See 'fmax Specification' near the end of this data sheet. This parameter is calculated from the measured fmax with internal feedback in a counter configuration (see Figure 2 for illustration). # tsk (o) is the skew time between registered outputs. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 OBSOLETE - No Longer Available TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT V 5.5 V VCC VIH Supply voltage VIL IOH Low-level input voltage (see Note 2) 0.8 V High-level output current -2 mA IOL fclock Low-level output current 12 mA 100 MHz High-level input voltage (see Note 2) 2 Clock frequency 0 High 5 Low 5 tw Pulse duration, clock tsu th Setup time, input or feedback before clock 7 ns Hold time, input or feedback after clock 0 ns ns TA Operating free-air temperature -55 25 125 C fclock, tw, tsu, and th do not apply to TIBPAL16L8' NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester noise. Testing these parameters should not be attempted without suitable equipment. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OBSOLETE - No Longer Available TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 electrical characteristics over recommended operating free-air temperature range PARAMETER VIK VOH VOL 0, Q outputs IOZH I/O ports 0, Q outputs IOZL I/O ports II I/O ports TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = - 18 mA IOH = - 2 mA VCC = 4.5 V, IOL = 12 mA VCC = 5.5 V, VO = 2.7 V VCC = 5.5 V, VO = 0.4 V VCC = 5.5 V, VI = 5.5 V VCC = 5.5 V, VI = 2.7 V IIL IOS VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 0.5 V ICC VCC = 5.5 V, VI = GND, IIH All others I Ci CLK/OE f = 1 MHz, MIN 2.4 TYP MAX UNIT -0.8 - 1.5 V 2.7 0.25 V 0.5 20 100 - 20 - 250 - 30 -70 Outputs open A 1 mA A - 250 A - 130 mA 210 mA 8.5 VI = 2 V A 100 25 OE = VIH, V pF 7.5 Co f = 1 MHz, VO = 2 V 10 pF All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fmax FROM (INPUT) TO (OUTPUT) TEST CONDITION MIN without feedback 100 with internal feedback (counter configuration) 100 MAX UNIT MHz R1 = 390 , 74 tpd tpd I, I/O O, I/O R2 = 750 , 1 7 ns CLK Q See Figure 8 1 7 ns ten tdis OE Q 1 8 ns OE Q 1 10 ns ten tdis I, I/O O, I/O 1 9 ns I, I/O O, I/O 1 10 ns with external feedback See 'fmax Specification' near the end of this data sheet. fmax does not apply for TIBPAL16L8'. fmax with external feedback is not production tested and is calculated from the equation located in the fmax specifications section. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 OBSOLETE - No Longer Available TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666. asynchronous preload procedure for registered outputs (see Figure 1 and Note 3) The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below. Step 1. Step 2. Step 3. Step 4. With VCC at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Lower Pin 11 to 5 V. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the voltage level at the output pin. VIHH Pin 11 5V VIL tsu + th td td VOH VIH Input Registered Output Output VIL Figure 1. Asynchronous Preload Waveforms Not applicable for TIBPAL16L8-5C and TIBPAL16L8-7M. NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 V 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VOL OBSOLETE - No Longer Available TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 power-up reset (see Figure 2) Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and feedback setup times are met. VCC 5V 4V tpd (600 ns TYP, 1000 ns MAX) VOH Active Low Registered Output 1.5 V VOL tsu VIH CLK 1.5 V 1.5 V VIL tw This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data. This is the setup time for input or feedback. Figure 2. Power-Up Reset Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 OBSOLETE - No Longer Available TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 fmax SPECIFICATIONS fmax without feedback (see Figure 3) In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback. Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (tsu + th). However, the minimum fmax is determined by the minimum clock period (tw high + tw low). 1 1 Thus, f max without feedback or (t t ). (t whigh t wlow) su h + ) ) CLK Logic Array C1 1D tsu + th or tw high + tw low Figure 3. fmax Without Feedback fmax with internal feedback (see Figure 4) This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop. 1 . Thus, f max with internal feedback (t su t CLK to FB) pd + ) * * Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array. CLK Logic Array C1 1D tsu tpd CLK - to - FB Figure 4. fmax With Internal Feedback 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OBSOLETE - No Longer Available TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 fmax SPECIFICATIONS fmax with external feedback (see Figure 5) This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tsu + tpd CLK-to-Q). 1 . Thus, f max with external feedback (t su t CLK to Q) pd + ) * * CLK Logic Array Next Device C1 1D tsu tpd CLK - to - Q tsu Figure 5. fmax With External Feedback POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 OBSOLETE - No Longer Available TIBPAL16R8-5C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 THERMAL INFORMATION thermal management of the TIBPAL16R8-5C Thermal management of the TIBPAL16R8-5CN and TIBPAL16R8-5CFN is necessary when operating at certain conditions of frequency, output loading, and outputs switching simultaneously. The device and system application will determine the appropriate level of management. Determining the level of thermal management is based on factors such as power dissipation (PD), ambient temperature (TA), and transverse airflow (FPM). Figures 6 (a) and 6 (b) show the relationship between ambient temperature and transverse airflow at given power dissipation levels. The required transverse airflow can be determined at a particular ambient temperature and device power dissipation level in order to ensure the device specifications. Figure 7 illustrates how power dissipation varies as a function of frequency and the number of outputs switching simultaneously. It should be noted that all outputs are fully loaded (CL = 50 pF). Since the condition of eight fully loaded outputs represents the worst-case condition, each application must be evaluated accordingly. MINIMUM TRANSVERSE AIR FLOW vs AMBIENT TEMPERATURE MINIMUM TRANSVERSE AIR FLOW vs AMBIENT TEMPERATURE 1000 Minimum Transverse Air Flow - ft/min Minimum Transverse Air Flow - ft/min 1000 800 PD = 1.6 W PD = 1.4 W PD = 1.2 W PD = 1 W PD = 0.8 W PD = 0.6 W 600 400 200 0 800 PD = 1.6 W PD = 1.4 W PD = 1.2 W PD = 1 W PD = 0.8 W PD = 0.6 W 600 400 200 0 0 10 20 30 40 50 60 70 80 0 10 TA - Ambient Temperature - C 30 40 50 60 TA - Ambient Temperature - C (a) TIBPAL16R8-5CN (b) TIBPAL16R8-5CFN Figure 6 20 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 70 80 OBSOLETE - No Longer Available TIBPAL16R8-5C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 THERMAL INFORMATION POWER DISSIPATION vs FREQUENCY P - Power Dissipation - mW D 1800 VCC = 5 V TA = 25 C CL = 50 pF 1600 8 Outputs Switching 7 Outputs Switching 6 Outputs Switching 5 Outputs Switching 4 Outputs Switching 3 Outputs Switching 2 Outputs Switching 1 Output Switching 1400 1200 1000 800 600 1 2 4 10 20 40 100 200 f - Frequency - MHz Figure 7 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 OBSOLETE - No Longer Available TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 PARAMETER MEASUREMENT INFORMATION 5V S1 R1 From Output Under Test Test Point CL (see Note A) R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V 0 3V High-Level Pulse 1.5 V 0 tw th tsu 1.5 V 3V Data Input 1.5 V 1.5 V 0 (see Note B) 3V Low-Level Pulse VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS 3V 3V 1.5 V Input 1.5 V 0 tpd tpd In-Phase Output 80 % 1.5 V 20 % tr tpd Out-of-Phase Output (see Note D) 20 % 1.5 V VOH 1.5 V VOL tf tpd VOH 1.5 V 80 % tf tr VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 0 (see Note B) Output Control (low-level enabling) 1.5 V 1.5 V 0 (see Note B) ten tdis 2.7 V 1.5 V Waveform 1 S1 Closed (see Note C) tdis ten Waveform 2 S1 Open (see Note C) VOL VOL + 0.5 V VOH 1.5 V VOH - 0.5 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. All input pulses have the following characteristics: For C suffix, PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%; For M suffix, PRR 10 MHz, tr = tf 2 ns, duty cycle = 50% C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing. Figure 8. Load Circuit and Voltage Waveforms 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OBSOLETE - No Longer Available TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 metastable characteristics of TIBPAL16R4-5C, TIBPAL16R6-5C, and TIBPAL16R8-5C At some point a system designer is faced with the problem of synchronizing two digital signals operating at two different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop can influence overall system reliability. Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said to be in the metastable state if the output hangs up in the region between VIL and VIH. This metastable condition lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum propagation delay time (CLK to Q max). From a system engineering standpoint, a designer cannot use the specified data sheet maximum for propagation delay time when using the flip-flop as a data synchronizer - how long to wait after the specified data sheet maximum must be known before using the data in order to guarantee reliable system operation. The circuit shown in Figure 9 can be used to evaluate MTBF (Mean Time Between Failure) and t for a selected flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in opposite states. When the Q output of the DUT is higher than 2 V or lower than 0.8 V, the comparators are at the same logic level. The outputs of the two comparators are sampled a selected time (t) after system clock (SCLK). The exclusive OR gate detects the occurrence of a failure and increments the failure counter. DUT Noise Generator Data in VIH Comparator 1D MTBF Counter 1D 1D C1 + C1 VIL Comparator SCLK C1 1D C1 SCLK + t Figure 9. Metastable Evaluation Test Circuit In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 10. Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state. Data in SCLK SCLK + t MTBF + t t Time (sec) # Failures trec = t - CLK to Q (max) Figure 10. Timing Diagram POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 OBSOLETE - No Longer Available TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 MTBF - Mean Time Between Failures - s By using the described test circuit, MTBF can be determined for several different values of t (see Figure 9). Plotting this information on semilog scale demonstrates the metastable characteristics of the selected flip-flop. Figure 11 shows the results for the TIBPAL16'-5C operating at 1 MHz. 10 9 10 yr 10 8 1 yr 10 7 10 6 1 mo 1 wk 10 5 1 day 10 4 1 hr 10 3 10 2 1 min 10 1 10 s 0 10 fclk = 1 MHz fdata = 500 kHz 20 30 40 50 t - Time Difference - ns 60 70 Figure 11. Metastable Characteristics From the data taken in the above experiment, an equation can be derived for the metastable characteristics at other clock frequencies. The metastable equation: 1 f x f x C1 e ( C2 x Dt) data SCLK MTBF * + The constants C1 and C2 describe the metastable characteristics of the device. From the experimental data, these constants can be solved for: C1 = 4.37 X 10-3 and C2 = 2.01 Therefore 1 MTBF + f SCLK x f data x 4.37 x 10 *3 e ( *2.01 x Dt) definition of variables DUT (Device Under Test): The DUT is a 5-ns registered PLD programmed with the equation Q : = D. MTBF (Mean Time Between Failures): The average time (s) between metastable occurrences that cause a violation of the device specifications. fSCLK (system clock frequency): Actual clock frequency for the DUT. fdata (data frequency): Actual data frequency for a specified input to the DUT. C1: Calculated constant that defines the magnitude of the curve. C2: Calculated constant that defines the slope of the curve. trec (metastability recovery time): Minimum time required to guarantee recovery from metastability, at a given MTBF failure rate. trec = t - tpd (CLK to Q, max) t: The time difference (ns) from when the synchronizing flip-flop is clocked to when its output is sampled. The test described above has shown the metastable characteristics of the TIBPAL16R4/R6/R8-5C series. For additional information on metastable characteristics of Texas Instruments logic circuits, please refer to TI Applications publication SDAA004, "Metastable Characteristics, Design Considerations for ALS, AS, and LS Circuits.'' 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OBSOLETE - No Longer Available TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE I OH - High-Level Output Current - mA 15 0 VCC = 5 V, TA = 25 C 10 5 0 -5 -10 -15 VCC = 5 V, TA = 25 C -10 -20 -30 -40 -50 -60 -70 -80 -90 -20 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 VOL - Low-Level Output Voltage - V -100 0 0.8 0.5 1 1.5 2 2.5 VOH - High-Level Output Voltage - V Figure 12 3 Figure 13 SUPPLY CURRENT vs FREE - AIR TEMPERATURE 220 200 I CC - Supply Current - mA I OL - Low-Level Output Current - mA 20 180 VCC = 5.5 V VCC = 5.25 V 160 140 VCC = 4.5 V VCC = 4.75 V VCC = 5 V 120 100 -75 -50 75 100 -25 0 25 50 TA - Free - Air Temperature - C 125 Figure 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 OBSOLETE - No Longer Available TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 TYPICAL CHARACTERISTICS POWER DISSIPATION vs FREQUENCY 8 - BIT COUNTER MODE PROPAGATION DELAY TIME vs SUPPLY VOLTAGE 6 1100 TA = 25 C CL = 50 pF R1 = 200 R2 = 200 1 Output Switching 5 TA = 80 C 1000 Propagation Delay Time - ns P - Power Dissipation - mW D VCC = 5 V TA = 25 C 900 TA = 0 C TA = 0 C TA = 80 C 800 4 tPHL (I, I/O to O, I/O) 3 tPLH (I, I/O to O, I/O) tPLH (CLK to Q) 2 tPHL (CLK to Q) 1 700 1 2 4 10 20 40 100 0 4.5 200 4.75 5 5.25 VCC - Supply Voltage - V f - Frequency - MHz Figure 15 Figure 16 PROPAGATION DELAY TIME vs FREE - AIR TEMPERATURE PROPAGATION DELAY TIME vs LOAD CAPACITANCE 16 6 VCC = 5 V CL = 50 pF R1 = 200 R2 = 200 1 Output Switching 4 3 2 tPHL (I, I/O to O, I/O) tPLH (I, I/O to O, I/O) tPLH (CLK to Q) VCC = 5 V TA = 25 C R1 = 200 R2 = 200 1 Output Switching 14 Propagation Delay Time - ns Propagation Delay Time - ns 5 tPHL (CLK to Q) 12 tPHL (I, I/O to O, I/O) 10 8 tPHL (CLK to Q) 6 4 tPLH (I, I/O to O, I/O) 1 2 0 -75 tPLH (CLK to Q) 0 -50 -25 0 25 50 75 100 TA - Free - Air Temperature - C 125 0 Figure 17 26 5.5 100 200 300 400 500 CL - Load Capacitance - pF Figure 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 600 OBSOLETE - No Longer Available TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS SRPS011D - D3359, OCTOBER 1989 - REVISED SEPTEMBER 1992 TYPICAL CHARACTERISTICS t sk(o) PROPAGATION DELAY TIME vs NUMBER OF OUTPUTS SWITCHING 0.8 6 VCC = 5 V TA = 25 C R1 = 200 R2 = 200 CL = 50 pF 8-Bit Counter 0.7 0.6 VCC = 5 V TA = 25 C CL = 50 pF R1 = 200 R2 = 200 5 Propagation Delay Time - ns - Skew Between Outputs Switching - ns SKEW BETWEEN OUTPUTS vs NUMBER OF OUTPUTS SWITCHING 0.5 0.4 Outputs Switching in the Opposite Direction 0.3 0.2 4 3 2 = tPHL (I, I/O to O, I/O) = tPLH (I, I/O to O, I/O) = tPHL (CLK to Q) = tPLH (CLK to Q) 1 0.1 Outputs Switching in the Same Direction 0 0 2 3 4 5 6 7 Number of Outputs Switching 8 1 Figure 19 2 3 4 5 6 Number of Outputs Switching 7 8 Figure 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) 5962-85155212A NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 596285155212A TIBPAL16 R8-7MFKB 5962-8515521RA NRND CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515521RA TIBPAL16R8-7MJ B 5962-8515521SA NRND CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515521SA TIBPAL16R8-7MW B TIBPAL16L8-5CFN OBSOLETE PLCC FN 20 TBD Call TI Call TI 0 to 70 TIBPAL16L8-5CN OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 75 TIBPAL16R4-5CN OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 75 TIBPAL16R6-5CFN OBSOLETE PLCC FN 20 TBD Call TI Call TI 0 to 75 16R6-5 TIBPAL16R6-5CN OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 75 TIBPAL16R6-5CN TIBPAL16R8-5CFN NRND PLCC FN 20 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-245C-168 HR 0 to 75 16R8-5 TIBPAL16R8-5CN NRND PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 75 TIBPAL16R8-5CN TIBPAL16R8-7MFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 596285155212A TIBPAL16 R8-7MFKB TIBPAL16R8-7MJB NRND CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515521RA TIBPAL16R8-7MJ B TIBPAL16R8-7MWB NRND CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515521SA TIBPAL16R8-7MW B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPLC004A - OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2013, Texas Instruments Incorporated