1 Mb (64K x 16) Static RAM
CY62127DV30
MoBL®
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-05229 Rev. *D Revised February 2, 2005
Features
• Very high speed: 45 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62127BV
• Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Packages offered in a 48-ball FBGA and a 44-lead TSOP
Type II
• Also available in Lead-Free 48-ball FBGA, and 44-lead
TSOP Type II packages
Functional Description[1]
The CY62127DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O0 through I/O15) are placed in a high-impedance state
when: deselected (CE HIGH), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH) or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
64K x 16
RAM Array I/O0 – I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
2048 x 512
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8 – I/O15
CE
WE
BLE
BHE
A0
A1
A9
Power -Down
Circuit BHE
BLE
CE
A10
10
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 2 of 12
Pin Configuration[2, 3]
Notes:
2. NC pins are not connected to the die.
3. E3 (DNU) can be left as NC or Vss to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
TSOP II (Forward)
12
13
41
44
43
42
16
15
29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
NC
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21
23
24 NC
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
WE
A11
A10
A6
A0
A3CE
I/O
10
I/O
8
I/O
9
A4
A5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A9
A8
OE
VSS
A7
I/O
0
BHE
NC
A2
A1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5I/O
6
I/O
7
A15
A14
A13
A
12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
FBGA (Top View)
NC
DNU
VCC
NC
Product Portfolio
Product
VCC Range (V) Speed
(ns)
Power Dissipation
Operating, ICC (mA)
Standby, ISB2 (µA)f = 1 MHz f = fMAX
Min. Typ. Max. Typ[4] Max. Typ.[4] Max. Typ.[4] Max.
CY62127DV30L 2.2 3.0 3.6 45 0.85 1.5 6.5 13 1.5 5
CY62127DV30LL 45 0.85 1.5 6.5 13 1.5 4
CY62127DV30L 2.2 3.0 3.6 55 0.85 1.5 5 10 1.5 5
CY62127DV30LL 55 0.85 1.5 5 10 1.5 4
CY62127DV30L 2.2 3.0 3.6 70 0.85 1.5 5 10 1.5 5
CY62127DV30LL 70 0.85 1.5 5 10 1.5 4
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 3 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential
......................................................................... −0.3V to 3.9V
DC Voltage Applied to Outputs
in High-Z State[5] ....................................−0.3V to VCC + 0.3V
DC Input Voltage[5] ................................ −0.3V to VCC + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range Ambient Temperature (TA)V
CC[6]
Industrial –40°C to +85°C 2.2V to 3.6V
DC Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
CY62127DV30-45 CY62127DV30-55 CY62127DV30-70
UnitMin. Typ.[4] Max. Min. Typ.[4] Max. Min. Typ.[4] Max.
VOH Output HIGH
Voltage
2.2 < VCC < 2.7 IOH = −0.1 mA 2.0 2.0 2.0 V
2.7 < VCC < 3.6 IOH = −1.0 mA 2.4 2.4 2.4
VOL Output LOW
Voltage
2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 0.4 0.4 V
2.7 < VCC < 3.6 IOL = 2.1 mA 0.4 0.4 0.4
VIH Input HIGH
Voltage 2.2 < VCC < 2.7 1.8 VCC
+ 0.3 1.8 VCC
+ 0.3 1.8 VCC
+ 0.3 V
2.7 < VCC < 3.6 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3
VIL Input LOW
Voltage 2.2 < VCC < 2.7 −0.3 0.6 −0.3 0.6 −0.3 0.6 V
2.7 < VCC < 3.6 −0.3 0.8 −0.3 0.8 −0.3 0.8
IIX Input
Leakage
Current
GND < VI < VCC −1+1−1+1−1+1µA
IOZ Output
Leakage
Current
GND < VO < VCC,
Output Disabled
−1+1−1+1−1+1µA
ICC VCC
Operating
Supply
Current
f = fMAX = 1/tRC VCC = 3.6V,
IOUT = 0 mA,
CMOS level
6.5 13 5 10 5 10 mA
f = 1 MHz 0.85 1.5 0.85 1.5 0.85 1.5
ISB1 Automatic CE
Power-down
Current—
CMOS Inputs
CE > VCC − 0.2V,
VIN > VCC − 0.2V, VIN < 0.2V,
f = fMAX (Address and
Data Only),
f = 0 (OE, WE, BHE and
BLE)
L 1.5 5 1.5 5 1.5 5 µA
LL 1.5 4 1.5 4 1.5 4
ISB2 Automatic CE
Power-down
Current—
CMOS Inputs
CE > VCC − 0.2V,
VIN > VCC − 0.2V or
VIN < 0.2V,
f = 0, VCC = 3.6V
L 1.5 5 1.5 5 1.5 5 µA
LL 1.5 4 1.5 4 1.5 4
Notes:
5. VIL(min.) = −2.0V for pulse durations less than 20 ns., VIH(max.) = VCC+0.75V for pulse durations less than 20 ns.
6. Full device Operation Requires linear Ramp of VCC from 0V to VCC(min) & VCC must be stable at VCC(min) for 500 µs.
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 4 of 12
AC Test Loads and Waveforms[8]
Data Retention Waveform[10]
Notes:
7. Tested initially and after any design or proces changes that may affect these parameters.
8. Test condition for the 45-ns part is a load capacitance of 30 pF.
9. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 200 µs.
10. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Chip Enable signals or by disabling both.
Capacitance[7]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz
VCC = VCC(typ)
8pF
COUT Output Capacitance 8 pF
Thermal Resistance
Parameter Description Test Conditions FBGA TSOP II Unit
θJA Thermal Resistance (Junction to Ambient)[7] Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
55 76 °C/W
θJC Thermal Resistance (Junction to Case)[7] 12 11 °C/W
Data Retention Characteristics
Parameter Description Conditions Min. Typ.[4] Max. Unit
VDR VCC for Data Retention 1.5 V
ICCDR Data Retention Current VCC=1.5V, CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V L4µA
LL 3
tCDR[7] Chip Deselect to Data
Retention Time
0ns
tR[9] Operation Recovery Time 200 µs
V
CC
Typ
VCC
OUTPUT
R2
C = 50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT VTH
Equivalent to: TH
ÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise Time:
1 V/ns Fall Time:
1 V/ns
L
Parameters 3.0V (2.7
–
3.6V) Unit
R1 1103 Ω
R2 1554 Ω
R
TH
645 Ω
V
TH
1.75 V
2.5V (2.2– 2.7V)
16600
15400
8000
1.2
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
t
R
CEor
V
CC
BHE.BLE
VCC(min.) VCC(min.)
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 5 of 12
Switching Characteristics (Over the Operating Range)[11]
Parameter Description
CY62127DV30-45 [8] CY62127DV30-55 CY62127DV30-70
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 45 55 70 ns
tAA Address to Data Valid 45 55 70 ns
tOHA Data Hold from Address Change 10 10 10 ns
tACE CE LOW to Data Valid 45 55 70 ns
tDOE OE LOW to Data Valid 25 25 35 ns
tLZOE OE LOW to Low Z[12] 555ns
tHZOE OE HIGH to High Z[12,14] 15 20 25 ns
tLZCE CE LOW to Low Z[12] 10 10 10 ns
tHZCE CE HIGH to High Z[12,14] 20 20 25 ns
tPU CE LOW to Power-up 0 0 0 ns
tPD CE HIGH to Power-down 45 55 70 ns
tDBE BLE/BHE LOW to Data Valid 45 55 70 ns
tLZBE[13] BLE/BHE LOW to Low Z[12] 555ns
tHZBE BLE/BHE HIGH to High-Z[12,14] 15 20 25 ns
Write Cycle[15]
tWC Write Cycle Time 45 55 70 ns
tSCE CE LOW to Write End 40 40 60 ns
tAW Address Set-up to Write End 40 40 60 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Set-up to Write Start 0 0 0 ns
tPWE WE Pulse Width 35 40 50 ns
tBW BLE/BHE LOW to Write End 40 40 60 ns
tSD Data Set-up to Write End 25 25 30 ns
tHD Data Hold from Write End 0 0 0 ns
tHZWE WE LOW to High Z[12,14] 15 20 25 ns
tLZWE WE HIGH to Low Z[12] 10 10 5 ns
Notes:
11. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL.
12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
13. If both byte enables are toggled together, this value is 10 ns.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 6 of 12
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[16,17]
Read Cycle No. 2 (OE Controlled)[16,17, 18]
Notes:
16. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
17. WE is HIGH for Read cycle.
18. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 7 of 12
Write Cycle No. 1 (WE Controlled)[14, 15, 19, 20, 21]
Write Cycle No. 2 (CE Controlled)[14, 15, 19, 20, 21]
Notes:
19. Data I/O is high-impedance if OE = VIH.
20. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
21. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
A
DDRESS
WE
DATA I/O
OE
BHE/BLE t
BW
DON'T CARE
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
A
DDRESS
WE
DATA I/O
OE
BHE/ BLE t
BW
t
SA
DON'T CARE
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 8 of 12
Write Cycle No. 3 (WE Controlled, OE LOW)[ 20, 21]
Write Cycle No. 4 (BHE-/BLE-controlled, OE LOW)[20, 21]
Switching Waveforms (continued)
DATA
IN
VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
A
DDRESS
WE
DATA I/O
t
BW
BHE/BLE
DON'T CARE
DATA I/O
A
DDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
CE
WE
DATA
IN
VALID
t
BW
BHE/BLE
t
SCE
t
PWE
DON'T CARE
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 9 of 12
Truth Table
Ordering Information
CE WE OE BHE BLE I/O
0
–I/O
7
I/O
8
–I/O
15
Mode Power
H X X X X High Z Deselect/Power-down Standby (I
SB
)
X X X H H High Z Deselect/Power-down Standby (I
SB
)
L H L L L Read All bits Active (I
CC
)
L H L H L Read Lower Byte Only Active (I
CC
)
L H L L H Read Upper Byte Only Active (I
CC
)
L H H L L Output Disabled Active (I
CC
)
L H H H L Output Disabled Active (I
CC
)
L H H L H Output Disabled Active (I
CC
)
High Z
High Z
High Z
Data Out
Data Out
High Z
High Z
Data Out
High Z
High Z
High Z
Data Out
High Z
High Z
LLXLLData In Data In Write Active (I
CC
)
L
L
L
L
X
X
H
L
L
H
Data In
High Z
High Z
Data In
Write Lower Byte Only
Write Upper Byte Only
Active (I
CC
)
Active (I
CC
)
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
45 CY62127DV30LL-45BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Industrial
CY62127DV30LL-45BVXI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free)
CY62127DV30LL-45ZSI ZS44 44-lead TSOP Type II
CY62127DV30LL-45ZSXI ZS44 44-lead TSOP Type II (Pb-Free)
55 CY62127DV30L-55BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Industrial
CY62127DV30LL-55BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62127DV30LL-55BVXI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free)
CY62127DV30L-55ZSI ZS44 44-lead TSOP Type II
CY62127DV30L-55ZSXI ZS44 44-lead TSOP Type II (Pb-Free)
CY62127DV30LL-55ZSI ZS44 44-lead TSOP Type II
70 CY62127DV30L-70BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Industrial
CY62127DV30LL-70BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62127DV30LL-70BVXI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free)
CY62127DV30L-70ZSI ZS44 44-lead TSOP Type II
CY62127DV30LL-70ZSI ZS44 44-lead TSOP Type II
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 10 of 12
Package Diagrams
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams
44-pin TSOP II ZS44
51-85087-*A
CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D Page 12 of 12
Document History Page
Document Title: CY62127DV30 MoBL 1 Mb (64K x 16) Static RAM
Document Number: 38-05229
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 117690 08/27/02 JUI New Data Sheet
*A 127311 06/13/03 MPR Changed From Advanced Status to Preliminary
Changed Isb2 to 5 µA (L), 4 µA (LL)
Changed Iccdr to 4 µA (L), 3 µA (LL)
Changed Cin from 6 pF to 8 pF
*B 128341 07/22/03 JUI Changed from Preliminary to Final
Add 70-ns speed, updated ordering information
*C 129000 08/29/03 CDY Changed Icc 1 MHz typ from 0.5 mA to 0.85 mA
*D 316039 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote # 8 on page #4
Added Lead-Free Package ordering information on page# 9
Changed 44-lead TSOP-II package name from Z44 to ZS44
