LTC6078/LTC6079
1
60789fa
Micropower Precision,
Dual/Quad CMOS
Rail-to-Rail Input/Output Amplifi ers
The LTC®6078/LTC6079 are dual/quad, low offset, low
noise operational amplifi ers with low power consumption
and rail-to-rail input/output swing.
Input offset voltage is trimmed to less than 25µV and the
CMOS inputs draw less than 50pA of bias current. The low
offset drift, excellent CMRR, and high voltage gain make
it a good choice for precision signal conditioning.
Each amplifi er draws only 54µA current on a 3V supply. The
micropower, rail-to-rail operation of the LTC6078/LTC6079
is well suited for portable instruments and single supply
applications.
The LTC6078/LTC6079 are specifi ed on power supply
voltages of 3V and 5V from –40 to 125°C. The dual am-
plifi er LTC6078 is available in 8-lead MSOP and 10-lead
DFN packages. The quad amplifi er LTC6079 is available
in 16-lead SSOP and DFN packages.
■ Photodiode Amplifi er
■ High Impedance Sensor Amplifi er
■ Microvolt Accuracy Threshold Detection
■ Instrumentation Amplifi ers
■ Battery Powered Applications
■ Maximum Offset Voltage of 25µV (25°C)
■ Maximum Offset Drift of 0.7µV/°C
■ Maximum Input Bias:
1pA (25°C)
50pA (≤85°C)
■ Micropower: 54µA per Amp
■ 95dB CMRR (Min)
■ 100dB PSRR (Min)
■ Input Noise Voltage Density: 16nV/√Hz
■ Rail-to-Rail Inputs and Outputs
■ 2.7V to 5.5V Operation Voltage
■ LTC6078 Available in 8-Lead MSOP and 10-Lead DFN
Packages; LTC6079 Available in 16-Lead SSOP and
DFN Packages
Thermocouple Signal Conditioner
APPLICATIO S
U
FEATURES DESCRIPTIO
U
TYPICAL APPLICATIO
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patent Pending.
1k
5.6pF
0.1µFOUT = 10mV/°C
0°C TO 500°C ±0.5°C
5V
5V –
+
60789 TA01a
2.49M
SMT
1/4W
150k
NORMALLY
FLOATING
OMEGA
5TC-TT-K-30-36
THERMOCOUPLE
AMPLIFIER PROTECTED TO ±190V, ACCIDENTAL CONTACT
40.6µV/°C
SMT
1/4W
150k
10k
100pF
K
1/2
LTC6078
LT1025
VOS Distribution
VOS (µV)
NUMBER OF AMPS OUT OF 200
14
12
10
6
8
4
2
0
60789 TA01b
–11 7–9 –7 –5 1 5 9–3 –1 3
LTC6078MS8
VS = 3V
VCM = 0.5V
TA = 25°C
LTC6078/LTC6079
2
60789fa
Total Supply Voltage (V+ to V–) ...................................6V
Input Voltage ...................................................... V– to V+
Output Short Circuit Duration (Note 2) ............ Indefi nite
Operating Temperature Range (Note 3)
LTC6078C, LTC6079C .......................... –40°C to 85°C
LTC6078I, LTC6079I ............................ –40°C to 85°C
LTC6078H, LTC6079H ........................ –40°C to 125°C
(Not Available in DFN Package)
(Note 1)
Specifi ed Temperature Range (Note 4)
LTC6078C, LTC6079C .............................. 0°C to 70°C
LTC6078I, LTC6079I ............................ –40°C to 85°C
LTC6078H, LTC6079H ........................ –40°C to 125°C
Junction Temperature
DFN Packages ................................................... 125°C
All Other Packages ............................................ 150°C
Storage Temperature Range
DFN Packages .................................... –65°C to 125°C
All Other Packages ............................. –65°C to 150°C
Lead Temperature (Soldering, 10 Sec) .................. 300°C
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
TOP VIEW
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1V+
OUTB
–INB
+INB
SHDN_B
OUTA
–INA
+INA
V–
SHDN_A
B
A
TJMAX = 125°C, θJA = 43°C/W
UNDERSIDE METAL CONNECTED TO V–
1
2
3
4
OUTA
–INA
+INA
V–
8
7
6
5
V+
OUTB
–INB
+INB
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
B
A
TJMAX = 150°C, θJA = 200°C/W
ORDER PART
NUMBER
DD PART
MARKING*
LTC6078CDD
LTC6078IDD
LBBB
LBBB
ORDER PART
NUMBER
MS8 PART
MARKING*
LTC6078ACMS8
LTC6078CMS8
LTC6078AIMS8
LTC6078IMS8
LTC6078AHMS8
LTC6078HMS8
LTAJZ
LTAJZ
LTAJZ
LTAJZ
LTAJZ
LTAJZ
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OUTD
–IND
+IND
V–
+INC
–INC
OUTC
NC
OUTA
–INA
+INA
V+
+INB
–INB
OUTB
NC
TOP VIEW
DHC PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
D
A
C
B
TJMAX = 125°C, θJA = 43°C/W
UNDERSIDE METAL CONNECTED TO V–
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
OUTA
–INA
+INA
V+
+INB
–INB
OUTB
NC
OUTD
–IND
+IND
V–
+INC
–INC
OUTC
NC
D
A
C
B
TJMAX = 150°C, θJA = 110°C/W
ORDER PART
NUMBER
DHC PART
MARKING*
LTC6079CDHC
LTC6079IDHC
6079
6079
ORDER PART
NUMBER
GN PART
MARKING
LTC6079CGN
LTC6079IGN
LTC6079HGN
6079
6079I
6079H
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
*The temperature grades and parametric grades are identifi ed by a label on the shipping container.
LTC6078/LTC6079
3
60789fa
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. Test conditions are V+ = 3V, V– = 0V, VCM = 0.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS C, I SUFFIXES H SUFFIX UNITS
MIN TYP MAX MIN TYP MAX
VOS Offset Voltage (Note 5) LTC6078MS8, LTC6078AMS8, LTC6079GN
V
CM = 0.5V, 2.5V
LTC6078DD, LTC6079DHC VCM = 0.5V, 2.5V
LTC6078AMS8 VCM = 0.5V
LTC6078MS8 VCM = 0.5V
LTC6079GN VCM = 0.5V
LTC6078DD VCM = 0.5V
LTC6079DHC VCM = 0.5V
●
●
●
●
●
±7
±7
±20
±25
±30
±30
±35
±25
±30
±70
±97
±115
±120
±150
±7
±25
±30
±35
±25
±95
±135
±165
μV
μV
μV
μV
μV
μV
μV
ΔVOS ⁄ΔT Input Offset Voltage Drift
(Note 5)
LTC6078AMS8
LTC6078MS8
LTC6078DD, LTC6079GN
LTC6079DHC
●
●
●
●
±0.2
±0.3
±0.3
±0.7
±1.1
±1.4
±1.8
±0.2
±0.3
±0.7
±1.1
±1.4
μV/°C
μV/°C
μV/°C
μV/°C
IBInput Bias Current
(Note 6)
VCM = V+/2
VCM = V+/2 ●
0.2
10
1
50
0.2
150
1
350
pA
pA
IOS Input Offset Current
(Note 6)
VCM = V+/2
VCM = V+/2 ●
0.1
0.5 25
0.1
10 100
pA
pA
enInput Noise Voltage 0.1Hz to 10Hz 1 1 µVP-P
Input Noise Voltage Density f = 1kHz
f = 10kHz
18
16
18
16
nV/√Hz
nV/√Hz
inInput Noise Current Density
(Note 8)
0.56 0.56 fA/√Hz
Input Common Mode Range ●V–V+V–V+V
CDIFF Differential Input Capacitance 10 10 pF
CCM Common Mode Input
Capacitance
18 18 pF
CMRR Common Mode Rejection
Ratio
All Packages VCM = 0V to 3V
LTC6078AMS8 VCM = 0V to 3V
LTC6078AMS8 VCM = 0V to 1.7V
LTC6078MS8 VCM = 0V to 3V
LTC6078MS8 VCM = 0V to 1.7V
LTC6079GN VCM = 0V to 3V
LTC6079GN VCM = 0V to 1.7V
LTC6078DD, LTC6079DHC VCM = 0V to 3V
LTC6078DD, LTC6079DHC VCM = 0V to 1.7V
●
●
●
●
●
●
●
●
95
87
91
85
89
84
88
83
87
110
105
103
102
102
102
102
100
102
95
87
91
85
89
84
88
110
103
103
100
102
100
102
dB
dB
dB
dB
dB
dB
dB
dB
dB
PSRR Power Supply Rejection Ratio VS = 2.7V to 5.5V
●
100
97
120 100
97
120 dB
dB
VOUT Output Voltage, High
(Referred to V+)
No Load
ISOURCE = 0.2mA
ISOURCE = 2mA
●
●
35
350
1
15
150
40
400
1
15
150
mV
mV
mV
Output Voltage, Low
(Referred to V–)
No Load
ISINK = 0.2mA
ISINK = 2mA
●
●
1
10
100
30
300
1
10
100
35
350
mV
mV
mV
AVOL Large-Signal Voltage Gain RLOAD = 10k, 0.5V ≤ VOUT ≤ 2.5V ●115 130 110 125 dB
ISC Output Short-Circuit Current Source
Sink
●
●
5
7
10
14
4
6
10
14
mA
mA
SR Slew Rate AV = 1 0.05 0.05 V/μs
GBW Gain-Bandwidth Product
(fTEST = 10kHz)
RL = 100k
●
420
360
750 420
320
750 kHz
kHz
Φ0Phase Margin RL = 10k, CL = 200pF 66 66 Deg
tSSettling Time 0.1% AV = 1, 1V Step 24 24 μs
ELECTRICAL CHARACTERISTICS
LTC6078/LTC6079
4
60789fa
ELECTRICAL CHARACTERISTICS
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. Test conditions are V+ = 3V, V– = 0V, VCM = 0.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS C, I SUFFIXES H SUFFIX UNITS
MIN TYP MAX MIN TYP MAX
ISSupply Current
(per Amplifi er)
No Load
●
54 72
78
54 72
80
μA
μA
Shutdown Current
(per Amplifi er)
Shutdown, VSHDN ≤ 0.8V, LTC6078DD ●0.3 1 μA
VSSupply Voltage Range Guaranteed by the PSRR Test ●2.7 5.5 2.7 5.5 V
Channel Separation fs = 10kHz, RL = 10k –110 –110 dB
Shutdown Logic SHDN High, LTC6078DD
SHDN Low, LTC6078DD
●
●
2
0.8
2
0.8
V
V
tON Turn on Time VSHDN = 0.8V to 2V, LTC6078DD 50 50 µs
tOFF Turn off Time VSHDN = 2V to 0.8V, LTC6078DD 2 2 µs
Leakage of SHDN Pin VSHDN = 0V, LTC6078DD 0.6 μA
The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. Test
conditions are V+ = 5V, V– = 0V, VCM = 0.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS C, I SUFFIXES H SUFFIX UNITS
MIN TYP MAX MIN TYP MAX
VOS Offset Voltage LTC6078MS8, LTC6078AMS8, LTC6079GN
V
CM = 0.5V
LTC6078DD, LTC6079DHC VCM = 0.5V
LTC6078AMS8 VCM = 0.5V
LTC6078MS8 VCM = 0.5V
LTC6079GN VCM = 0.5V
LTC6078DD VCM = 0.5V
LTC6079DHC VCM = 0.5V
●
●
●
●
●
±10
±10
±20
±25
±30
±30
±35
±30
±35
±75
±102
±120
±125
±155
±10
±25
±30
±35
±30
±100
±140
±170
μV
μV
μV
μV
μV
μV
μV
ΔVOS ⁄ΔT Input Offset Voltage Drift
(Note 7)
LTC6078AMS8
LTC6078MS8
LTC6078DD, LTC6079GN
LTC6079DHC
●
●
●
●
±0.2
±0.3
±0.3
±0.7
±1.1
±1.4
±1.8
±0.2
±0.3
±0.7
±1.1
±1.4
μV/°C
μV/°C
μV/°C
μV/°C
IBInput Bias Current VCM = V+/2
VCM = V+/2 ●
0.2
10
1
50
0.2
150
1
350
pA
pA
IOS Input Offset Current VCM = V+/2
VCM = V+/2 ●
0.1
0.5 25
0.1
10 100
pA
pA
enInput Noise Voltage 0.1Hz to 10Hz 1 1 µVP-P
Input Noise Voltage Density f = 1kHz
f = 10kHz
18
16
18
16
nV/√Hz
nV/√Hz
inInput Noise Current Density
(Note 8)
0.56 0.56 fA/√Hz
Input Common Mode Range ●V–V+V–V+V
CDIFF Differential Input Capacitance 10 10 pF
CCM Common Mode Input
Capacitance
18 18 pF
LTC6078/LTC6079
5
60789fa
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: A heat sink may be required to keep the junction temperature
below the absolute maximum. This depends on the power supply voltage
and how many amplifi ers are shorted.
Note 3: The LTC6078C/LTC6079C and LTC6078I/LTC6079I are guaranteed
functional over the operating temperature range of –40°C to 85°C. The
LTC6078H/LTC6079H are guaranteed functional over the operating
temperature range of –40°C to 125°C.
Note 4: The LTC6078C/LTC6079C are guaranteed to meet specifi ed
SYMBOL PARAMETER CONDITIONS C, I SUFFIXES H SUFFIX UNITS
MIN TYP MAX MIN TYP MAX
CMRR Common Mode Rejection
Ratio
All Packages VCM = 0V to 5V
LTC6078AMS8 VCM = 0V to 5V
LTC6078AMS8 VCM = 0V to 3.7V
LTC6078MS8 VCM = 0V to 5V
LTC6078MS8 VCM = 0V to 3.7V
LTC6079GN VCM = 0V to 5V
LTC6079GN VCM = 0V to 3.7V
LTC6078DD, LTC6079DHC VCM = 0V to 5V
LTC6078DD, LTC6079DHC VCM = 0V to 3.7V
●
●
●
●
●
●
●
●
91
90
94
88
90
86
90
86
90
105
105
105
100
105
100
105
100
105
91
90
94
88
90
86
90
105
105
105
100
105
100
105
dB
dB
dB
dB
dB
dB
dB
dB
dB
PSRR Power Supply Rejection Ratio VS = 2.7V to 5.5V
●
100
97
120
97
120 dB
dB
VOUT Output Voltage, High
(Referred to V+)
No Load
ISOURCE = 0.5mA
ISOURCE = 5mA
●
●
50
500
2
20
200
55
550
2
20
200
mV
mV
mV
Output Voltage, Low
(Referred to V–)
No Load
ISINK = 0.5mA
ISINK = 5mA
●
●
1
15
150
40
400
1
15
150
45
450
mV
mV
mV
AVOL Large-Signal Voltage Gain RLOAD = 10k, 0.5V ≤ VOUT ≤ 4.5V ●115 130 110 125 dB
ISC Output Short-Circuit Current Source
Sink
●
●
14
14
25
25
12
12
25
25
mA
mA
SR Slew Rate AV = 1 0.05 0.05 V/μs
GBW Gain-Bandwidth Product
(fTEST = 10kHz)
RL = 100k
●
420
360
750 420
320
750 kHz
kHz
Φ0Phase Margin RL = 10k, CL = 200pF 66 66 Deg
tSSettling Time 0.1% AV = 1, 1V Step 24 24 μs
ISSupply Current
(per Amplifi er)
No Load
●
55 74
82
55 74
84
μA
μA
Shutdown Current
(per Amplifi er)
Shutdown, VSHDN ≤ 1.2V, LTC6078DD ●1.5 5 1.5 5 μA
VSSupply Voltage Range Guaranteed by the PSRR Test ●2.7 5.5 2.7 5.5 V
Channel Separation fs = 10kHz, RL = 10k –110 –110 dB
Shutdown Logic SHDN High, LTC6078DD
SHDN Low, LTC6078DD
●
●
3.5
1.2
3.5
1.2
V
V
tON Turn on Time VSHDN = 1.2V to 3.5V, LTC6078DD 50 50 µs
tOFF Turn off Time VSHDN = 1.2V to 3.5V, LTC6078DD 2 2 µs
Leakage of SHDN Pin VSHDN = 0V, LTC6078DD 0.6 μA
performance from 0°C to 70°C. The LTC6078C/LTC6079C are designed,
characterized and expected to meet specifi ed performance from –40°C
to 85°C but are not tested or QA sampled at these temperatures. The
LTC6078I/LTC6079I are guaranteed to meet specifi ed performance from
–40°C to 85°C. The LTC6078H/LTC6079H are guaranteed to meet specifi ed
performance from –40°C to 125°C.
Note 5: VOS and VOS drift are 100% tested at 25°C and 125°C.
Note 6: IB and IOS are guaranteed by the VS = 5V test.
Note 7: VOS drift is guaranteed by the VS = 3V test.
Note 8: Current noise is calculated from in = √2qIB, where q = 1.6 • 10–19
coulomb.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. Test conditions are V+ = 5V, V– = 0V, VCM = 0.5V unless otherwise noted.
LTC6078/LTC6079
6
60789fa
NUMBER OF AMPS OUT OF 200
14
12
10
6
8
4
2
0
60789 G01
–11 7–9 –7 –5 1 5 9–3 –1 3
VOS (µV)
LTC6078MS8
VS = 3V
VCM = 0.5V
TA = 25°C
TIME (5s/DIV)
60789 G09
VS = 5V
VCM = 0.5V
VOLTAGE NOISE (500nV/DIV)
VCM (V)
0
INPUT BIAS CURRENT (pA)
400
300
200
100
–0
–100
–200
–300
–400 4
1235
60789 G07
VS = 5V
TA = 125°C
FREQUENCY (Hz)
NOISE VOLTAGE (nV/√Hz)
90
80
70
60
50
40
30
20
10
0
1 100 1k 100k
60789 G08
10 10k
VS = 5V
VCM = 0.5V
VS = 3V
VCM = 0.5V
TEMPERATURE (°C)
0
INPUT BIAS CURRENT (pA)
180
160
140
100
120
20
40
60
80
0100
60789 G05
25 50 75 125
VS = 5V
VCM = 2.5V
VCM (V)
0
INPUT BIAS CURRENT (pA)
30
24
18
12
6
–0
–6
–12
–18
–24
–30 4
1235
60789 G06
VS = 5V
TA = 70°C
TA = 85°C
µV/°C
NUMBER OF AMPS OUT OF 200
50
45
40
30
35
25
20
15
10
5
0
60789 G04
–0.8 0.6–0.6 –0.4 0 0.4 0.8–0.2 0.2
LTC6078MS8
VS = 3V
VCM = 0.5V
TA = –40°C TO 125°C
VCM (V)
0
VOS (µV)
1.5 2.5
60789 G03
0.5 1.0 2.0 3.5 4.5
4.0
100
40
20
80
60
0
–20
–100
–40
–60
–80
5.03.0
VS = 5V
TA = 25°C
REPRESENTATIVE PARTS
VCM (V)
0
VOS (µV)
1.5 2.5
60789 G02
0.5 1.0 2.0
40
30
20
10
0
–10
–20
–30
–40
3.0
VS = 3V
TA = 25°C
REPRESENTATIVE PARTS
VOS Drift Distribution Input Bias vs Temperature Input Bias vs VCM
Input Bias vs VCM Voltage Noise Spectrum
0.1Hz to 10Hz Output Voltage
Noise
VOS Distribution VOS vs VCM VOS vs VCM
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC6078/LTC6079
7
60789fa
20µs/DIV 60789 G17
20mV/DIV
VS = 5V
RL = 10k
CL = 100pF
200µs/DIV 60789 G18
1V/DIV
VS = 5V
RL = 10k
CL = 100pF
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
10000
1000
100
10
1
0.1
0.01
100 100k 1M
60789 G16
10k1k
VS = 5V
VCM = 0.5V
TA = 25°C
AV = 100
AV = 10
AV = 1
FREQUENCY (Hz)
PSRR (dB)
140
120
80
100
60
40
20
0
1 10 100 10k 100k 10M
60789 G15
1k 1M
VS = 5V
VCM = 0.5V
TA = 25°C
FREQUENCY (Hz)
100
80
60
40
20
0
–20
–40
1k 100k 1M 10M
60789 G13
10k
GAIN (dB)
100
80
60
40
20
0
–20
–40
PHASE (DEG)
VS = 5V
VCM = 0.5V
CL = 200pF
TA = 25°C
RL = 10k
RL = 100k
GAIN
PHASE
LOAD CURRENT (mA)
OUTPUT VOLTAGE SWING (V)
(REFERRED TO SUPPLY VOLTAGE)
+VS
+VS –0.5
+VS –1.0
+VS –1.5
+VS –2.0
–VS +2.0
–VS +1.5
–VS +1.0
–VS +0.5
–VS
0.01 1 10 100
60789 G10
0.1
VS = 5V
VCM = 0.7V
SOURCE
SINK
TA = 125°C
TA = 25°C
TA = –55°C
SUPPLY VOLTAGE (V)
0 0.5
SUPPLY CURRENT (µA)
1.0 3.0 4.0
60789 G11
2.5 5.0 5.51.5 2.0 3.5 4.5
60
50
40
30
20
10
0
PER AMPLIFIER
VCM = 0.5V
TA = 25°C
TEMPERATURE (°C)
–40 –25
SUPPLY CURRENT (µA)
–10 50 80
60789 G12
35 110 125520 65 95
65
50
60
45
55
40
PER AMPLIFIER
VCM = 0.5V
VS = 5V
VS = 3V
FREQUENCY (Hz)
CMRR (dB)
120
80
100
60
40
20
0
–20
100 10k 100k 10M
60789 G14
1k 1M
VS = 5V
VCM = 0.5V
TA = 25°C
RL = 1k
Open Loop Gain vs Frequency CMRR vs Frequency PSRR vs Frequency
Output Impedance vs Frequency Small Signal Transient Large Signal Transient
Output Voltage Swing vs
Load Current Supply Current vs Supply Voltage Supply Current vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC6078/LTC6079
8
60789fa
CAPACITIVE LOAD (pF)
10
OVERSHOOT (%)
50
45
40
35
30
25
20
15
10
5
0
100 1000
60789 G20
VS = 5V
VCM = 0.5V
TA = 25°C
AV = 10
AV = 1
FREQUENCY (Hz)
100
OUTPUT IMPEDANCE (kΩ)
60789 G19
1k 10k 100k 1M 10M
1000
100
10
1
0.1
0.01
VS = 5V
VCM = 0.5V
TA = 25°C
AV = 1
FREQUENCY (Hz)
100 1k 10k 100k 1M 10M
CHANNEL SEPARATION (dB)
60789 G21
–100
–105
–110
–115
–120
–125
–130
–135
VS = 5V
VCM = 0.5V
RL = 10k
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Disabled Output Impedence vs
Frequency Overshoot vs CL
PI FU CTIO S
UUU
Channel Separation vs Frequency
OUT: Amplifi er Output
–IN: Inverting Input
+IN: Noninverting Input
V+: Positive Supply
V–: Negative Supply
⎯
S
⎯
H
⎯
D
⎯
N
⎯
_
⎯
A: Shutdown Pin of Amplifi er A, active low and only
valid for LTC6078DD. An internal current source pulls the
pin to V+ when fl oating.
⎯
S
⎯
H
⎯
D
⎯
N
⎯
_
⎯
B: Shutdown Pin of Amplifi er B, active low and only
valid for LTC6078DD. An internal current source pulls the
pin to V+ when fl oating.
NC: Not internally connected.
Exposed Pad: Connected to V–.
LTC6078/LTC6079
9
60789fa
Figure 1. Op Amp with Input Voltage Clamp
Preserving Input Precision
Preserving input accuracy of the LTC6078/LTC6079 re-
quires that the application circuit and PC board layout do
not introduce errors comparable or greater than the 10µV
typical offset of the amplifi ers. Temperature differentials
across the input connections can generate thermocouple
voltages of 10’s of microvolts so the connections to the
input leads should be short, close together and away from
heat dissipating components. Air current across the board
can also generate temperature differentials.
The extremely low input bias currents (0.2pA typical) al-
low high accuracy to be maintained with high impedance
sources and feedback resistors. Leakage currents on the
PC board can be higher than the input bias current. For
example, 10GΩ of leakage between a 5V supply lead and
an input lead will generate 500pA! Surround the input
leads with a guard ring driven to the same potential as the
input common mode to avoid excessive leakage in high
impedance applications.
Input Clamps
Large differential voltages across the inputs over very
long time periods can impact the precisely trimmed input
offset voltage of the LTC6078/LTC6079. As an example,
a 2V differential voltage between the inputs over a period
of 100 hours can shift the input offset voltage by tens
of microvolts. If the amplifi er is to be subjected to large
differential input voltages, adding back-to-back diodes
between the two inputs will minimize this shift and retain
the DC precision. If necessary, current-limiting series
resistors can be added in front of the diodes, as shown
in Figure 1. These diodes are not necessary for normal
closed loop applications.
–
+
500Ω
500Ω
60789 F01
APPLICATIO S I FOR ATIO
WUUU
Capacitive Load
LTC6078/LTC6079 can drive capactive load up to 200pF in
unity gain. The capacitive load driving capability increases
as the amplifi er is used in higher gain confi gurations. A
small series resistance between the ouput and the load
further increases the amount of capacitance the amplifi er
can drive.
⎯
S
⎯
H
⎯
D
⎯
N Pins
Pins 5 and 6 are used for power shutdown on the LTC6078
in the DD package. If they are fl oating, internal current
sources pull Pins 5 and 6 to V+ and the amplifi ers operate
normally. In shutdown, the amplifi er output is high imped-
ance, and each amplifi er draws less than 2µA current.
When the chip is turned on, the supply current per amplifi er
is about 35µA larger than its normal values for 50µs.
Rail-to-Rail Input
The input stage of LTC6078/LTC6079 combines both PMOS
and NMOS differential pairs, extending its input common
mode voltage range to both positive and negative supply
voltages. At high input common mode range, the NMOS
pair is on. At low common mode range, the PMOS pair is
on. The transition happens when the common voltage is
between 1.3V and 0.9V below the positive supply.
Thermal Hysteresis
Figure 2 shows the input offset hysteresis of LTC6078MS8
for 3 thermal cycles from –45°C to 90°C. The typical offset
shift after the 3 cycles is only 1µV.
Figure 2. VOS Thermal Hysteresis of LTC6078MS8
VOS CHANGE FROM INITIAL VALUE
NUMBER OF AMPLIFIERS
50
45
40
35
30
25
20
15
10
5
0
60789 F02
–5 5–3–4 –2 –1 2 4 601 3
VS = 3V
VCM = 0.5V
1ST CYCLE
2ND CYCLE
3RD CYCLE
LTC6078/LTC6079
10
60789fa
APPLICATIO S I FOR ATIO
WUUU
PC Board Layout
Mechanical stress on a PC board and soldering-induced
stress can cause the VOS and VOS drift to shift. The DD
and DHC packages are more sensitive to stress. A simple
way to reduce the stress-related shifts is to mount the IC
near the short edge of the PC board, or in a corner. The
board edge acts as a stress boundary, or a region where
the fl exure of the board is minimum. The package should
always be mounted so that the leads absorb the stress and
not the package. The package is generally aligned with the
leads paralled to the long side of the PC board.
The most effective technique to relieve the PC board stress
is to cut slots in the board around the op amp. These slots
can be cut on three sides of the IC and the leads can exit on
the fourth side. Figure 3 shows the layout of a LTC6078DD
with slots at three sides.
Figure 3. Vertical Orientation of LTC6078DD with Slots
60789 F03
LONG DIMENSION
SLOTS
Simplifi ed Schematic of the Amplifi er
R1 R2
R3
V+
V–
R4
–
+
D8
D7
OUT
M8
M9
C1
C2
60789 SS
V+
V–
D5
D6
–
+
OUTPUT
CONTROL
M4
M6
A1
A2
M7
M5
I1
VBIAS
M1 M2
M3
–IN
V+
V–
V+
V–
D3
D4
+IN
V–
M11M10
1µAI2
V+
V–
D1
D2
SHDN BIAS
GENERATION
NOTE: SHDN IS ONLY AVAILABLE
IN THE DFN10 PACKAGE
SCHE ATIC
WW
SI PLIFIED
LTC6078/LTC6079
11
60789fa
–2.5V
1M
1000pF
VOUT
2.5V
–
+
60789 TA04
COLUMBIA RESEARCH LABS
3021 ACCELERATOR
VOUT = 60mV/g
WHERE g = EARTH'S GRAVITATIONAL CONSTANT
1/2
LTC6078
–2.5V
1M
3.8pF
VOUT
2.5V
+
–
60789 TA05
TEMD1000
IR PHOTODIODE
AT 870nm (IR),
VOUT = 600mV/µW RECEIVED POWER
1/2
LTC6078
–
+
2N7002
HSDL-4220
VDD VDD
60789 TA03
100k
909k
5V
0V
49.9Ω
ON/OFF
SHDN
VARYING ON DUTY CYCLE REDUCES
AVERAGE POWER CONSUMPTION
1/2
LTC6078
–
+
2N7002
VDD
IL
VDD
60789 TA02
RS
R2
R1
LOAD
VOUT = IL • R2 • RS – VOS • R2
R1 R1
0V ≤ VOUT ≤ VDD – VGS, MOSFET
VOUT
1/2
LTC6078
TYPICAL APPLICATIO S
U
2.7V High Side Current Sense
Low Average Power IR LED Driver
Accelerometer Signal Conditioner
Photodiode Amplifi er
LTC6078/LTC6079
12
60789fa
TYPICAL APPLICATIO S
U
6 Decade Current Log Amplifi er
60789 TA07
VDD
VCC
133k
100k
Q1
1000pF
VOUT
1µF10nA ≤ IIN ≤ 10mA
Q1, Q2: DIODES INC. DMMT3906W
A TO D: LTC6079
VOUT ≈ 150mV • log (IIN) + 1.23V, IIN IN AMPS
PRECISION
RESISTOR PT146
1k
+3500ppm/°C
100Ω
1.58k
+
–
D
–
+
B
+
–
C
+
–
A
1µF
Q2
33µF
IIN
100Ω
GND
LT6650
IN OUT
Humidity Sensor Signal Conditioner
60789 TA08
VDD
VOUT
0V TO 5V
0% TO 100% RH
34.8k
49.9k
499k
1k
10k 47.5k
1k
100k
VDD
VDD
VDD
VSUP
5.2V TO 20V
VDD
5V
1µF
0.01µF
0.1µF
BAT54S
1µF
IN OUT
SHDN
LT1761-5
BYP
VDD OUT
SET DIV
GRD GND
100k
OFFSET TRIM
GAIN TRIM
49.9k
M1
VDD
VBIAS
100k
100k
A TO C: LTC6079
H: GE PARAMETRICS G-CAP 2 HUMIDITY SENSOR
148pF TO 178pF, 0% TO 90% RH
M1: VN2222L
1000pF
75pF
H
+
–
C
+
–
B
+
–
A
1M
100k
0.1µF
LTC6906
VBIAS
LTC6078/LTC6079
13
60789fa
TYPICAL APPLICATIO S
U
LDO Load Balancing
VDD
60789 TA09
1k
VIN
1.8V TO 20V
10µF
0.01µF
0.1µF
10µF
LOAD
ILOAD
IN OUT
SHDN
LT1763
BYP
FB
+
–
A
R1
2k
R2
2k
0 ≤ ILOAD ≤ 1.5A
1.22V ≤ VOUT ≤ VDD
LDO LOADS MATCH TO WITHIN
1mA WITH 10mΩ OF BALLAST
RESISTANCE (2 INCHES OF AWG
28 GAUGE STRANDED WIRE)
A, B: LTC6078
BALLAST RESISTANCE:
IDENTICAL LENGTH
THERMALLY MATED
WIRE OR PCB TRACE
+
10µF0.01µF
IN OUT
SHDN
LT1763
BYP
FB
2k
10k
2k
100Ω
1k
0.1µF
10µF0.01µF
IN OUT
SHDN
LT1763
BYP
FB
2k
10k
2k
100Ω
+
–
B
R2
R1
VOUT = 1.22V 1 +
⎛
⎝
⎜⎞
⎠
⎟
pH Probe Amplifi er
60789 TA10
VCC
1k
VOUT
1000pF
SENSOR: SENSOREX S200C pH PROBE
LTC6078 INPUT IMPEDANCE ≈ 1TΩ OR GREATER
VOUT = 1.25V + 59.2mV • (pH – 7)
A, B: LTC6078
PRECISION
RESISTOR PT146
1k
+3500ppm/°C
57.6k
+
–
B
LT1634
1.25V
pH
–
+
A
LTC6078/LTC6079
14
60789fa
TYPICAL APPLICATIO S
U
Precision Sample-and-Hold
Thermistor Amplifi er with Overtemperature Alarm
60789 TA12
VOUT
TOV
100k
100k
29.4k
100k
0.01µF
50k
178k
71.5k
A TO D: LTC6079, VDD = 2.7V TO 5.5V, VSS = GND
VOUT = 0 → 1V FOR 0°C TO 100°C, LINEAR
TOV → HIGH WHEN T ≥ 90°C
YSI #44201
THERMOLINEAR
NETWORK
–
+
C
–
+
B
+
–
D
–
+
A
3200Ω
200k
H
6250Ω
B
VDD
1k
LT1634
1.25V
GAIN TRIM
20k
143k
OFFSET TRIM
60789 TA13
VOUT
VIN
VDD
0.1µF
9
6
ISUPPLY < 200µA
VOLTAGE DROOP = 130nV/ms TYP
SLEW RATE = 0.05V/ms TYP
ACQ TIME = 84µs TYP TO 0.1%
S/H
+
–
LTC6078
A
LTC6943
14
+
–
LTC6078
B
7
1
5
4
LTC6078/LTC6079
15
60789fa
TYPICAL APPLICATIO S
U
Precision Voltage-Controlled Current Source
60Hz Notch
60789 TA14
IOUT
VIN
VDD
1µF1µF
IOUT = VIN
RSET
–
+
14
LTC6943
15
0.68µF
0.001µF
1k
RSET
1k
9
67
10
11 12
IERROR < 0.1% AT IOUT = 1µA
1/2
LTC6078
2.5V
–2.5V
60789 TA15
VIN
VOUT
R2
R1
10M10M
540pF
5M
270pF270pF
+
–
NOTCH DEPTH = –60dB AT 60Hz, RTI
VOUT = 1 + • VIN
R2
R1
()
1/2
LTC6078
LTC6078/LTC6079
16
60789fa
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
PACKAGE DESCRIPTIO
U
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
LTC6078/LTC6079
17
60789fa
PACKAGE DESCRIPTIO
U
3.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.20
TYP
4.40 ±0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHC16) DFN 1103
0.25 ± 0.05
PIN 1
NOTCH
0.50 BSC
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.20 ±0.05
0.50 BSC
0.65 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
LTC6078/LTC6079
18
60789fa
PACKAGE DESCRIPTIO
U
MSOP (MS8) 0204
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 ± 0.152
(.193 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
LTC6078/LTC6079
19
60789fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
PACKAGE DESCRIPTIO
U
LTC6078/LTC6079
20
60789fa
© LINEAR TECHNOLOGY CORPORATION 2005
LT 0506 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
PART NUMBER DESCRIPTION COMMENTS
LTC2051/LTC2052 Dual/Quad Zero-Drift Op Amps 3µV VOS, 30nV/°C VOS Drift
LT6011/LT6012 Dual/Quad Precision Op Amps 60µV VOS, IB = 300pA, IS = 135µA
TYPICAL APPLICATIO
U
RELATED PARTS
DC Accurate Composite Amplifi er, Gain of 1000
VEE 10k
VOUT
VIN
VCC
VEE
VCC
VDD
LT1634BCS8-5
–
+
60789 TA06
100Ω
10Ω
10Ω
10k
VSS
2.49k
2.49k
CIRCUIT BW ≈ 1.25MHz
en = 2.6nV/√Hz (RTI) AT 1kHz
CIRCUIT VOS = 25µV (MAX) RTI
1M
VSS
0.1µF
VDD
+
–
LT1226
1/2
LTC6078
