DG611/612/613 Siliconix A Member of the TEMIC Group High-Speed, Low-Glitch D/CMOS Analog Switches Features Benefits Applications @ Fast Switchington: 12 ns @ Improved Data Throughput Fast Sample-and-Holds @ Low Charge Injection: +2 pC @ Minimal Switching Transients @ Synchronous Demodulators @ Wide Bandwidth: 500 MHz Improved System Performance Pixel-Rate Video Switching @ S-V CMOS Logic Compatible @ Easily Interfaced @ Disk/Tape Drives Low rps(ony: 18 2 Low Insertion Loss @ DAC Deglitching @ Low Quiescent Power: 1.2 nW @ Minimal Power Consumption Switched Capacitor Filters @ Single Supply Operation @ GaAs FET Drivers @ Satellite Receivers Description The DG611/612/613 feature high-speed low-capacitance lateral DMOS switches. Charge injection has been minimized to optimize performance in fast sample-and-hold applications. Each switch conducts equally well in both directions when on and blocks up to 16 V,, when off. Capacitances have been minimized to ensure fast switching and low-glitch energy. To achieve such fast and clean switching performance, the DG611/612/613 are built on the Siliconix proprietary D/CMOS process. This process combines n-channel DMOS switching FETS with low-power CMOS control logic and drivers. An epitaxial layer prevents latchup. The DG611 and DG612 differ only in that they respond to opposite logic levels. The versatile DG613 has two normally open and two normally closed switches. It can be given various configurations, including four SPST, two SPDT, one DPDT. For additional information see Applications Note AN207. Functional Block Diagram and Pin Configuration DG611 Dual-In-Line and SOIC IN, (| LU a IN2 aT YY as] >? Sy LS iia] S2 ve S fl V+ GND [5] 12] Vi S4 [6 | 1] S3 w Eh, ee INg m4 a IN3 Top View Ordering Information DG611/612 DG611DJ 1 16-Pin Plastic DIP 40 to 85C 16-Pin Narrow SOIC 16-Pin CerDIP 55 to 125C LCC-20 1-200 DG611 bec D; IN; NC INz D2 Key Sy) $2 v- V+ NC NC GND VL S4 S3 D4 INy NC IN3 D3 Top View Four SPST Switches per Package Truth Table Logic DG611 DG612 0 ON OFF i OFF ON Logic 0 < 1V Logie 1 = 4V Switches Shown for DG611 Logie 1 Input P-32167Rev. C (11/1593)Siliconix A Member of the TEMIC Group DG611/612/613 Functional Block Diagram and Pin Configuration (Cont'd) DG613 DG613 Dual-In-Line and SOIC Lec CT D, IN; NC IN, Dp IN, Gl] Fal IN) Key > hy Y Vfl a! Oe . Bs ia} Vv v- [a V+ 4 13 13] NC G Cy ful & D. VO D S4 ER Ayia B] D, INg NC IN3 D3 Top View Top View Ordering Information DG613 Four SPST Switches per Package | Temp Range Package: "Part Number Truth Table 16-Pin Plastic DIP | DG613DJ = Logie fo SW SWa 40 to 85C : : 16-Pin Narrow SOIC | DG613DY 0 OFF 16-Pin CerDIP DG613AK/883 1 ON $5 to 125C 7 LCC-20 DG613AZ/883 Logic 0 s 1V Logic 1 = 4V Switches Shown for Logic 1 Input Absolute Maximum Ratings VEO Vc cece cece etter n ee -0.3 V to21V Power Dissipation (Package) VHtOGND . 2... cece e eee eee -03 Vto21V 16-Pin Plastic DIP Va tOGND o.oo e eee ee eter eeeeaes -19 Vt003V 16-Pin Narrow SOIC# VLtOGND 200.0. 0 eee e ee ce cece een ens -1Vto(V+)+1V 16-Pin CerDIP 2.1... see eee or 20 mA, whichever occurs first 2O-Pin LOCE eee eee eee e cece eter tees VIN8 occ cee ee ete eee nte eens (V-) -1Vto (V+) +1V or 20 mA, whichever occurs first Notes: Vs, V8 eee e cence eee ee eeces (V-) -0.3 V to (V-) + 16V a. Signals on Sx, Dx, or INx exceeding V+ or V will be clamped by or 20 mA, whichever occurs first internal diodes. Limit forward diode current to maximum current Continuous Current (Any Terminal) ................005 +30 mA b a ead ided dered to PC Board . leads welded or solder joard, Current, S or D (Pulsed at 1 us, 10% Duty Cycle) ....... +100 mA c. Derate 6 mW/*C above 75C Storage Temperature: CerDIP 65 to 150C d. Derate 7.6 mW/C above 75C Plastic 65 to 125C e. Derate 12 mW/C above 75C CAUTION: ESD (electrostatic discharge) sensitive. All pins are diode protected; however, permanent damage may occur on unconnected devices subjected to high energy electrostatic fields. Use proper ESD control procedures. Recommended Operating Range P-32167-Rev. C (11/15/93) ... SVto21V .. 710Vt00V 4V10V+ VIN (6c eee ent e eee e tence enteeees OV to Vu V-1t0(V+)-5V 1-201DG611/612/613 Siliconix A Member of the TEMic Group Specifications* Test Conditions A Suffix D Suffix Unless Otherwise Specified -55 to 125C 40 ta 85C V+ =15V,V-=-3V Parameter Symbol VL=5V,Vn=4Vi1ve Temp | Typ | Min? | Max? | Min? | Max? | Unit Analog Signal Range VANALOG V~=-5V,Vt=12V Full -5 7 -5 7 Vv Room 18 45 45 Switch On-Resistance tp: S(on) Is = -1 mA, Vp =0V Full 60 60 Q Resistance Match Bet Ch. Arps(on) Room 2 . 0. . 0.25 5 Source Off Leakage Is(ofty Vs = 0V, Vp = 10V or 0.001 OD O -20 0 Drain Off Leakage Current | Ip(ofty Vs = 10V, Vp = OV Room } 0,001 | 0.25 | 025) 025 | 025 | aa . Room | +0.001 | ~0.4 0.4 -0.4 0.4 Switch On Leakage Current Ipen) Vs = Vp =0V Hot ~40 40 40 40 Input Voltage High Vin Full 4 4 Vv Input Voltage Low Vit Full 1 1 Room | 0.005 -1 1 -1 1 Input Current lin Hot -20 | 20 | -20 | 20 | BA Input Capacitance Cn Room 5 pF Dynamic Characteristics Off State Input Capacitance Crotty Vs =0V Room 3 Off State Output Capacitance | Cpyoff) Vp =0V Room 2 pF On State Input Capacitance Cscon) Vs = Vp =0V Room 10 Bandwidth BW Ry = 50 Room 500 MHz Turn-On Time ton Rr = 300Q, Cy = 3 pE Vs = +2V Room 12 25 25 Turn-Off Time? OFF See Test Circuit, Figure 2 Room | 8 20 20 Turn-On Time ton Room 9 2 3 ns Ry = 300 @, CL = 75 pE Vs = +2V See Test Circuit, Figure 2 Room 16 25 25 Turn-Off Time toPF Full 35 35 Charge Injection Q Cy = 1nk Vs=0V Room 4 C Ch. Injection Change & AQ CL=1nk| Vs| s3V Room 3 4 4 p Off Isolation OIRR Rw = 50, Ry = 502,f=5MHz | Room 74 dB Crosstalk XTALK Rw = 10 Q, Ry = 50Q,f=5 MHz | Room 87 Power Supplies 7 : cee Room | 0.005 1 1 Positive Supply Curent I+ Full 5 5 . Room | 0.005 ~-1 -1 Negative Supply Current I- Full 5 5 Vin =OVor5v pA . Room 0.005 1 1 Logic Supply Current IL Full 5 5 Room | -0.005 -1 -1 Ground Current IGnp Full 5 _ 1-202 P-32167Rev. C (11/15/93)Siliconix A Member of the TEMIC Group Specifications for Unipolar Supplies DG611/612/613 Test Conditions A Suffix D Suffix Unless Otherwise Specified -55 10 125C | 40 to 85C V+ =12V,V- =0V Parameter Symbol VL =5V. Vin =4V,1VE Temp> | Typ* | Min@ | Max4 | Min? | Max? | Unit Analog Switch Analog Signal Range VANALOG Full 0 7 a 7 Vv Switch On-Resistance TDs(on) Ig = -1 mA, Vp =1V Room 25 60 60 Q Dynamic Characteristics : : : Turn-On Time ton Ry, = 3002, CL =3pRVs=2V Room 15 30 30 as Turn-Off Time 1OFF See Test Circuit, Figure 2 Room | 10 25 25 Notes: a. Refer to PROCESS OPTION FLOWCHART (Section 5 of the 1994 Data Book or FaxBack number 7103). b. Room = 25C, Full = as determined by the operating temperature suffix. we mo EG Typical Characteristics Tps(on) VS. Vp and Power Supply Voltages _ 400 ~ 400 Gq Is = -1 mA G 3 350 3 350 300 = 300 z a = 250 3 250 QO 8 200 8 200 i i A s 150 : 150 g S 100 a 100 i 50 = 50 a no 8 a 0 0 -5-4 -2 0O 2 4 & 10. 12 Vp Drain Voltage (V) Leakage Current vs. Analog Voltage 3 | I 10 nA V+=15V ze 1 V-=-3V nA & = 2 S 2 E 1 @ 100 pa 2 Iscott), Ep(otf) 9 o l 4 = 8 {| 1) S 10pA 4 a 1-4 * ; g n = 1pA ~ -2 Ip(on) i. -3 0.1 pA 4 -2 0 2 4 6 8 10 Vp or Vs Drain or Source Voltage (V) P-32167Rev. C (11/15/93) Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. Guaranteed by design, not subject to production test. Vin = input voltage to perform proper function. AQ = |Qat Vs = 3 V - Qat Vs = -3 VI. Fps(on) VS- Vp and Temperature V+ =15V V-=-3V Is = -1mA ~55 -2 #0 2 4 6 ~55C 8 10 12 Vp Drain Voltage (V) Leakage Currents vs. Temperature 25 0 25 50 Temperature (C) 7S 100 125 1-203DG611/612/613 Typical Characteristics (Cont'd) Input Switching Threshold vs. Vy, 6 V+ =15V & SP v-=-3V op | , 2 , s S S > ite oe 3 e E 3 2 3 ee 7? a 7 4 0 0 5 10 15 Vi Logic Supply Voltage (V) Charge Injection vs. Analog Voltage 20 V+=i15V V~=-3V 10 % & 0 z Oo -10 20 3-2-1012 3 45 678 9 10 VANALOG Analog Voltage (V) 0 3 dB Bandwidth/Insertion Loss vs. Frequency R, = 502 3 dB Point Insertion Loss (dB) 1 10 100 1000 f Frequency (MHz) 1-204 (4B) Time (ns) Supply Current (mA) Siliconix A Member of the TEMIC Group Switching Times vs. Temperature 24 22 20 18 16 14 12 10 8 6 V+=15V V-=-3V 4 RL = 3009 2 Cy = 10 pF 0 -55 -35 -15 5 25 45 65 85 105 125 Temperature (C) 120 Crosstalk and Off Isolation vs. Frequency V+=15V V-=-3V -100 ~-80 Crosstalk -60 Off Isolation 40 20 1 10 100 f Frequency (MHz) Supply Currents vs. Switching Frequency 6 5 V+ =15V V-=-3V 4 vpsasv 3 Cx = 0,5V 2 1 0 -1 -2 -3 ~4 1k 100k 100k 1M 10M f Frequency (Hz) P-32167Rev. C (11/15/93)Siliconix A Member of the TEMIC Group DG611/612/613 Schematic Diagram (Typical Channel) V+ 0 1_-0 gs Level Translator Driver I oD DMOS Switch Figure 1. Test Circuits +5V +15V t Sv t, < 10 ns \ tg < 10 ns VL V+ Logic Input L 50% +2V 6 s aD ov | IT IN Vs= +2V RL 90% GND v- 300 2 | * Switch Output 5 = = 20% ov = = 3Vv *1 ton loFF Cy (includes fixture and stray capacitance) Vo = Vs R Ri + mps(on) Figure 2. Switching Time +5V +15V VL V+ RB s D T or" LT oO Vo I oP 4 CL 1nF Ts 6 les v- I = 1 -3V rH Figure 3. Charge Injection P-32167Rev. C (11/15/93) Xtaxx Isolation = 20 log C= RF bypass Figure 4. Crosstalk 1-205DG611/612/613 Applications High-Speed Sample-and-Hold In a fast sample-and-hold application, the analog switch characteristics are critical. A fast switch reduces aperture uncertainty. A low charge injection eliminates offset (step) errors. A low leakage reduces droop errors. The Si581, a fast input buffer, helps to shorten acquisition and settling Siliconix A Member of the TEMIC Group times. A low leakage, low dielectric absorption hold capacitor must be used. Polycarbonate, polystyrene and polypropylene are good choices. The JFET output buffer reduces droop due to its low input bias current. (See Figure 5.) +5V +12V NK Buffer t t Output Buffer Tnput > S__of'a r +5 V Output + jutpu aa ! LESS T toAD a 5VControl O IN 4 Cyo , DG611 60, pF. Polystyrene Lt 4 -5V Figure . High-Speed Sample-and-Hold Pixel-Rate Switch Windows, picture-in-picture, title overlays are economically generated using a high-speed analog switch such as the DG613. For this application the two video sources must be synclocked. The glitch-less analog switch eliminates halos. (See Figure 6.) +5V +12V i Output Buffer Background ( 75Q TQ Composite Output ViV Titles 75Q V Control O % DG613 + 4 -5V Figure 6. A Pixel-Rate Switch Creates Title Overlays 1-206 P-32167Rev. C (11/15/93}Siliconix A Member of the TEMIC Group Applications (Cont'd) GaAs FET Drivers Figure 7 illustrates a high-speed GaAs FET driver. To turn the GaAs FET on 0 V are applied to its gate via S,, whereas to turn it off, -8 V are applied via Sj. This high-speed, DG611/612/613 low-power driver is especially suited for applications that require a large number of RF switches, such as phased array radars. IK 2 SY TLo wy -8V Figure 7. A High-Speed GaAs FET Driver that Saves Power P-32167Rev. C (11/15/93) GaAs RF RF IN : OUT 1-207