NJU8753
-1-
Ver.2003-09-26
Analog Signal Input Class D Amplifier
with DC-DC Converter for Piezo Speaker
GENERAL DESCRIPTION
The NJU8753 is an analog signal input class D power
amplifier with DC-DC converter for Piezo speaker. Input
part operates on 2.85V(typ) and a built-in DC-DC
converter generates variable output voltage(up to 12V)
with input voltage(2.6 to 4.2V). Therefore, it drives
Piezo speaker with louder sound and high efficiency.
The NJU8753 incorporates BTL amplifier, which
eliminate AC coupling capacitors, capable of driving
monaural Piezo speaker with simple external LC
low-pass filters.
Class D operation achieves lower power operation for
Piezo speaker, thus the NJU8753 is suited for battery-
powered applications.
FEATURES
Piezo Speaker Driving
Output voltage: 8Vrms(Typ.) @VDDO=10.0V
1-channel Analog Signal Input, 1-channel BTL output
Standby(Hi-Z),
Built-in DC-DC Converter
Built-in Low Voltage Detector
Built-in Short Protector
Operating Voltage :2.6~3.6V(VDD, VREG)
:2.6~4.2V(VBAT)
CMOS Technology
Package Outline :QFN28
PIN CONFIGURATION
PACKAGE OUTLINE
NJU8753KN1
PRELIMINARY
TEST1
TEST3
VREG
FB
VSS
VSS1
VSS1
L
X
L
X
VOUT
V
R
EN2
NC
VDDO
VDD
VSS
IIN
COM
EN1
TEST2
VDDO
VDDO
OUTP
VSS
NC
VSS
OUTN
VDDO
28
1
QFN28
NJU8753
- 2 - Ver.2003-09-26
BLOCK DIAGRAM
Pulse
Width
Modulator
Short
Protector
VDD
Control Logic Low Voltage
Detecto
r
Soft Start
VSS
+
-
+
-
IN
COM
EN1
VDDO
OUTP
VSS
VDDO
OUTN
VSS
Switching
Regulator
EN2 FB VR L
X
VOUT VREG
VSS1
TEST1
TEST2
TEST3
NJU3555NJU3555NJU8753
-3-
Ver.2003-09-26
PIN DESCRIPTION
No. SYMBOL I/O Function
1 TEST1 I
Maker test 1
This pin must be connected to GND.
2 TEST3 I
Maker test 3
This pin must be connected to GND.
3 VREG − Switching regulator Power Supply : VREG=2.85V
4 FB I Switching regulator Feedback resistor
5 VSS − Power GND : VSS=0V
6,7 VSS1 − Switching regulator Power GND : VSS1=0V
8,9 LX I Switching regulator voltage input
10 VOUT − Switching regulator Power Supply : Vout=10.0V
11 VR O Switching regulator Output voltage
12 EN2 I
Switching regulator Standby Control
High : Step-up ON Low : Standby ON
This pin must be connected to VREG when step-up ON.
13 NC − Non connection
14, 15 VDDO − Output Power supply
16 OUTN O Negative Output
17 VSS − Power GND : VSS=0V
18 NC − Non connection
19 VSS − Power GND : VSS=0V
20 OUTP O Positive output
21, 22 VDDO − Output Power supply
23 TEST2 I
Maker Test 2
This pin must be connected to GND.
24 EN1 I
Power Amplifier Standby Control
High : Standby OFF Low : Standby ON
This pin must be connected to VDD when Standby OFF.
25 COM − Analog common
26 IN I Audio Signal Input
27 VSS I Power GND : VSS=0V
28 VDD − Power Supply : VDD=2.85V
*Pin No.5(VSS), 6(VSS1), 7(VSS1), 17(VSS), 19(VSS), 27(VSS) should be connected at the nearest
point to the IC.
*Pin No.14(VDDO) , 15(VDDO), 21(VDDO), 22(VDDO) should be connected at the nearest point to the IC.
*Pin No.3(VREG) and 28(VDD) must be connected to VDD, when these pins are not used.
NJU8753
- 4 - Ver.2003-09-26
FUNCTIONAL DESCRIPTION
(1) Signal Output
The OUTP and OUTN generate PWM output signals, which will be converted to analog signal via external
2nd-order or higher LC filter. A switching regulator with a high response against a voltage fluctuation is the best
selection for the VDDO, which are the power supply for output drivers. To obtain better THD performance, the
stabilization of the power is required.
(2) EN1
By setting the EN1 pin to “L”, the standby mode is enabled. In the standby mode, the entire functions of the
NJU8753 enter a low-power state, and the output pins (OUTP and OUTN) are high impedance.
(3) Low Voltage Detector
When the power supply voltage drops down to below VDD(MIN), the internal oscillation is halted for prevention
to generate unwanted frequency, and the output pins (OUTP, OUTN) become in high impedance.
(4) Step-up switching regulator
The switching regulator is used as power supply(VDDO) for power amplifier of class-D. The PFM controlled
switching regulator works with external components, which are coil, capacitor, Schottky-diode and resistor for
Step-up voltage.
By setting the EN2 pin to “H”, the step-up operation is enabled, and in case of “L”, standby mode is enabled.
Step-up voltage is set by internal reference voltage(VREG / 2) and external resistors.
The step-up voltage can be calculated by the following methods:
<Calculation of the step-up voltage>
The step-up voltage is determined by internal reference voltage(VREF), R1 and R2. (See Figure.2)
ex. VDD=2.85V, Internal reference voltage(VREF) = VREG / 2=1.425[V], R1=2MΩ, R2=330kΩ
” Step-up voltage[V] = VREF×((R1+R2)/R2) = 1.425×((2M + 330k)/330k) = 10.06[V] ”
Note 1) Apply VREG first, next VBAT. Otherwise, the voltage stress may cause a permanent damage to the IC.
(5) Short Circuit Protection
The short protector, which protects the NJU8753 against high short-circuit current, turns off the output driver.
After about 5 seconds from the protection, the NJU8753 returns to normal operation. The short protector
functions at the following accidents.
-Short between OUTP and OUTN
-Short between OUTP and VSS
-Short between OUTN and VSS
Note 1) The detectable current and the period for the protection depend on the power supply voltage
and ambient temperature.
Note 2) The short protector is not effective for a long term short-circuit current but for an instantaneous accident.
Continuous high-current may cause permanent damage to the NJU8753.
NJU3555NJU3555NJU8753
-5-
Ver.2003-09-26
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER SYMBOL RATING UNIT
Supply Voltage
VDD
VREG
VDDO
-0.3 ~ +4.0
-0.3 ~ +4.0
-0.3 ~ +15.0
V
V
V
LX Input Voltage VLX -0.3 ~ +15.0 V
FB Input Voltage VFB -0.3 ~ +4.0 V
Input Voltage Vin -0.3 ~ VDD+0.3 V
Operating Temperature Topr -40 ~ +85 °C
Storage Temperature Tstg -40 ~ +125 °C
Power Dissipation PD 640* mW
* : Mounted on a glass epoxy PCB(50mm x 50mm x 1.6mm).
Note 1) All voltage are relative to “VSS= 0V” reference.
Note 2) The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause
permanent damage to the LSI.
Note 3) De-coupling capacitors for VDD(Pin 28)-VSS(Pin 27), VREG(Pin 3)-VSS(Pin 5) and LX(Pin 8,9)-VSS(Pin
17,18,19) should be connected for stable operation.
ELECT RICAL CHARACTER ISTI C
(Ta=25°C, VDD=VREG=2.85V, VBAT=3.7V, VDDO=10V, VSS=0V, VSS1=0V,
TEST1=TEST2=TEST3=0V, EN1=EN2=2.85V,
Input Signal=1kHz, Input Signal Level=150mVrms, Frequency Band=20Hz~20kHz,
Load Impedance=2.0µF 2nd-order 11.5kHz LC Filter(Q=0.72))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Note
VDD Supply Voltage VDD 2.6 2.85 3.6 V
VREG Supply Voltage VREG 2.6 2.85 3.6 V
VBAT Input Voltage VBAT 2.6 3.7 4.2 V
VDDO Supply Voltage VDDO 8.0 10.0 12.0 V
Input Impedance ZIN IN pin - 20 - KΩ
Voltage Gain AV - 31 - dB
Output THD THD Input Signal Level
=200mVrms - 0.05 0.08 % 4
Maximum Output Vo Output THD=10% - 8.0 - Vrms
S/N SN A weight - 80 - dB 4
Operating Current(Standby) IST EN1=EN2=0V - - 1 µA
Operating Current
(No signal input) ISS No-load operating
No Signal Input - 10 15 mA
VIH EN1, EN2 pins 0.7VDD - VDD V
Input Voltage VIL EN1, EN2 pins 0 - 0.3VDD V
Input Leakage Current ILK EN1, EN2 pins - - ±1.0 µA
Switching regulator
Oscillating Frequency fOSC 220 300 380 kHz
Switching regulator
Maximum Load Current IOUT Step-up Voltage =10.0V
VOUT= 10.0V X 95% 50 - - mA
Switching regulator
Load Stability ∆VOUT Step-up Voltage =10.0V
IOUT =10mA~50mA - 100 - mV
NJU8753
- 6 - Ver.2003-09-26
Note 4) Test system of the output THD and S/N
The output THD and S/N are tested in the system shown in Figure 1, where a 2nd-order LC LPF and
another filter incorporated in an audio analyzer are used.
2nd-order LC LPF : Refer to “Typical Application Circuit”
Filters : 22Hz HPF + 20kHz LPF(AES17)
(with the A-Weight filter for S/N and Dynamic-range tests)
Input Signal
THD
Measuring
Apparatus
Filte
r
20kHz
(AES17)
2nd-order
LC LPF
NJU8753 Test Board Audio Analyzer
Figure 1. Output THD and S/N Test System
NJU8753
NJU3555NJU3555NJU8753
-7-
Ver.2003-09-26
TYPICAL APPLICATION CIRCUIT
Note 5) De-coupling capacitors must be connected between each power supply pin and GND.
The capacity value should be adjusted on the application circuit and the operation temperature. It may
malfunction if capacity value is small.
Note 6) The power supply for VDDO require fast driving response performance such as a switching regulator for
better THD.
THD performance becomes worse by ripple if the capacity of De-coupling capacitors is small.
Note 7) The above circuit shows only application example and does not guarantee the any electrical
characteristics. Therefore, please test the circuit carefully to fit your application.
The cutoff frequency of the LC filter influences the quality of sound.
The Q factor of the LC filter must be less than “1”. Otherwise, the operating current increase when the
frequency of input signal is closed to the cutoff frequency.
Note 8) The transition time for EN1 and EN2 signals must be less than 100µs. Otherwise, a malfunction may
be occurred.
Note 9) (1)-(28) indicates pin number.
Piezo Speaker
Figure 2. Application Circuit example
NJU8753
OUTP(20)
OUTN(16)
VDD(28)
VSS(27)
0.1µF
10µF
VDD
IN(26)
COM(25)
EN1(24)
10µF
47µH
2µF
47uH
4.7Ω
4.7Ω
IN 2.2µF
22000pF
2.4kΩ
VDDO
(
14,15
)
VOUT
(
10
)
VBAT
VSS(17,19)
FB(4)
LX(8,9)
TEST1
(
1
)
TEST2
(
23
)
VDDO
(
21,22
)
Schottky diode
(IF=1A,VF=0.45V)
R1
R2
2MΩ
330kΩ
0.1µF10µF
TEST3(2)
EN2(12)
VREG(3)
VSS(5)
0.1µF
10µF
VDD
0.1µF
0.1µF
22µH(DCR=0.5Ω)
22µF
VR(11)
VSS1(6,7)
0.1µF
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
