CS5451A Six-channel, Delta-sigma Analog-to-digital Converter Features Description * Synchronous Sampling * On-chip 1.2 V Reference (25 ppm/C typ.) * Power Supply Configurations: The CS5451A is a highly integrated delta-sigma () analog-to-digital converter (ADC) developed for the power measurement industry. The CS5451A combines six ADCs, decimation filters, and a serial interface on a single chip. The CS5451A interfaces directly to a current transformer or shunt to measure current, and to a resistive divider or transformer to measure voltage. The product features a serial interface for communication with a microcontroller or DSP. The product is initialized and fully functional upon reset, and includes a voltage reference. - VA+ = +3 V; VA- = -2 V; VD+ = +3 V - Supply Tolerances: 10% * Power Consumption - 23 mW Typical at VD+ = +3 V * Simple Four-wire Serial Interface * Charge pump driver output generates negative power supply. * Ground-referenced Bipolar Inputs VIN1+ VIN1IIN2+ IIN2VIN2+ VIN2- IIN3+ IIN3VIN3+ VIN3VREFIN VREFOUT RESET VD+ x1, 20 4th Order Modulator Decimation Filter x1 4th Order Modulator Decimation Filter x1, 20 4th Order Modulator Decimation Filter SE 4th Order Modulator x1 OWRS Decimation Filter Serial Interface 4th Order Modulator x1, 20 SDO FSO Decimation Filter SCLK 4th Order Modulator x1 Decimation Filter x1 Voltage Reference AGND http://www.cirrus.com See page 13. VA+ GAIN IIN1+ IIN1- ORDERING INFORMATION: Clock VA- XIN Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved) Pulse Output Regulator CPD DGND AUG `05 DS635F2 CS5451A TABLE OF CONTENTS 1. PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.5 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.6 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. PACKAGE DIMENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . . 13 8. REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LIST OF FIGURES Figure 1. Serial Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. One Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. Serial Port Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Generating VA- with a Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 DS635F2 CS5451A PIN DESCRIPTION Serial Clock Output SCLK 1 28 VD+ Digital Supply Serial Data Output SDO 2 27 DGND Digital Ground Frame Sync FSO 3 26 CPD Charge Pump Drive Serial Port Enable SE 4 25 XIN Master Clock Current Input Gain GAIN 5 24 RESET Reset Analog Ground AGND 6 23 OWRS Output Word Rate Select Reference Input VREFIN 7 22 VIN1+ Differential Voltage Input 1 Reference Output VREFOUT 8 21 VIN1- Differential Voltage Input 1 20 IIN1+ Differential Current Input 1 19 IIN1- Differential Current Input 1 CS5451A 1. Positive Analog Supply VA+ 9 Negative Analog Supply VA - 10 Differential Voltage Input 3 VIN3+ 11 18 VIN2+ Differential Voltage Input 2 Differential Voltage Input 3 VIN3- 12 17 VIN2- Differential Voltage Input 2 Differential Current Input 3 IIN3+ 13 16 IIN2+ Differential Current Input 2 Differential Current Input 3 IIN3- 14 15 IIN2- Differential Current Input 2 Clock Generator Master Clock Input 25 XIN - External clock signal or oscillator input. Control Pins and Serial Data I/O Serial Clock Output 1 SCLK - Serial port clock signal that determines the output data rate for SDO pin. Rate of SCLK is dependent on the XIN frequency and state of OWRS pin. Serial Data Output 2 SDO -Serial port data output pin. Data will be output at a rate defined by SCLK. Frame Sync 3 FSO - Framing signal indicates when data samples are about to be transmitted on the SDO pin. Serial Port Enable 4 SE - When SE is low, the output pins of the serial port are tri-stated. Current Input Gain 5 GAIN - A logic high sets current channel gain to 1, a logic low sets the gain to 20. If no connection is made to this pin, it will default to logic low level (through internal 200 k resistor to DGND). 23 OWRS - A logic low sets the output word rate (OWR) to XIN/2048 (Hz). A logic high sets the OWR to XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low level (through internal 200 k resistor to DGND). 24 RESET - Low activates Reset, all internal registers are set to their default states. Output Word Rate Select Reset Analog Inputs/Outputs Voltage Reference Input 7 VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator. Voltage Reference Output 8 VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magnitude of 1.2 V and is referenced to the AGND pin on the converter. Differential Voltage Inputs 11,12 VIN3+, VIN3- - Differential analog input pins for the voltage channel 3. 18,17 VIN2+, VIN2- - Differential analog input pins for the voltage channel 2. 22,21 VIN1+, VIN1- - Differential analog input pins for the voltage channel 1. Differential Current Inputs 13,14 IIN3+, IIN3- - Differential analog input pins for the current channel 3. 16,15 IIN2+, IIN2- - Differential analog input pins for the current channel 2. 20,19 IIN1+, IIN1- - Differential analog input pins for the current channel 1. Power Supply Connections Analog Ground 6 AGND - Analog ground. Positive Analog Supply 9 VA+ - The positive analog supply. Typical +3 V 10% relative to AGND. Negative Analog Supply 10 VA- - The negative analog supply. Typical -2 V 10% relative to AGND. Charge Pump Drive 26 CPD - Designed to drive external charge pump circuitry that will produce a negative analog supply (VA-)voltage. Digital Ground 27 DGND - Digital Ground. Positive Digital Supply 28 VD+ - The positive digital supply. Typical +3 V 10% relative to AGND. DS635F2 3 CS5451A 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter DC Power Supplies Positive Digital Positive Analog Negative Analog Voltage Reference Input Symbol Min Typ Max Unit VD+ VA+ VA- 2.7 2.7 -2.2 3.0 3.0 -2.0 3.3 3.3 -1.8 V V V VREF+ - 1.2 - V ANALOG CHARACTERISTICS * * * * Min/Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = VD+ = 3 V 10%; VA- = -2 V 10%; AGND = DGND = 0 V; VREFIN = +1.2 V. All voltages with respect to 0 V. XIN = 4.096 MHz. Parameter Symbol Min Typ Max Unit THD 74 - - dB CMRR 80 - - dB VA- - VA+ V - XIN/4 - Hz Accuracy (All Channels) Total Harmonic Distortion Common Mode Rejection (DC, 50, 60 Hz) Common Mode + Signal on Input Input Sampling Rate Analog Inputs (Note 1) Differential Input Voltage Range [(IIN+) - (IIN-)] or [(VIN+) - (VIN-)] Gain=20 Gain=1 VIN VIN - 80 1.6 - mVP-P VP-P Bipolar Offset Gain=20 Gain=1 VOS VOS - 11.5 0.5 20 4.0 mV mV - -105 - dB Crosstalk (Channel-to-channel) Input Capacitance Effective Input Impedance Noise (Referred to Input) 0-60 Hz 0-1 kHz 0-2 kHz (50, 60 Hz) Gain = 20 Gain = 1 IC IC - - 20 1 pF pF Gain=20 Gain=1 EII EII 50 500 60 600 - k k - - 1 20 2.5 50 3.75 75 Vrms Vrms Vrms Vrms Vrms Vrms 1.15 1.2 1.25 V - 25 50 ppm/C Gain=20 Gain=1 Gain=20 Gain=1 Gain=20 Gain=1 Reference Output Output Voltage REFOUT Temperature Coefficient VR - 6 10 mV PSRR 60 - - dB VREF+ 1.15 1.2 1.25 V Input Capacitance - - 10 pF Input CVF Current - - 1 A Load Regulation (Output Current 1 A Source or Sink) Power Supply Rejection Reference Input Input Voltage Range 4 DS635F2 CS5451A ANALOG CHARACTERISTICS (continued) Parameter Symbol Min Typ Max Unit PSCA PSCD PSCD - 4.0 5.0 1.0 5.3 6.3 1.5 mA mA mA PC PC - 27 23 35 31 mW mW PSRR PSRR PSRR 50 50 60 65 90 - dB dB dB Power Supplies Power Supply Currents IA+ ID+ with CPD Typical VA+ = VD+ = +3 V; VA- = -2 V ID+ without CPD Power Consumption (Note 2) With CPD Without CPD Power Supply Rejection 50, 60 Hz (Note 3) 50, 60 Hz (Note 3) (DC) Voltage Channel Current Channel Notes: 1. Specifications for Gain = 20 apply only to Current Channels. Voltage Channels are fixed to Gain = 1 2. 3. All outputs unloaded. All inputs CMOS level. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3 V, AGND = DGND = 0 V, VA- = -2 V (using chargepump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins. The "+" and "-" input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel's inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB): 106.07 PSRR = 20 log ------------------ V eq DIGITAL CHARACTERISTICS (See Note 4) * * * * Min/Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = VD+ = 3V 10%; VA- = -2 V 10%; AGND = DGND = 0 V. All voltages with respect to 0 V. XIN = 4.096 MHz Parameter Symbol Min Typ Max Unit XIN 3 4.096 5 MHz 40 - 60 % OWR OWR - XIN/2048 XIN/1024 - Hz Hz High-Level Input Voltage VIH 0.6 VD+ - VD+ V Low-Level Input Voltage VIL 0.0 - 0.8 V Master Clock Characteristics Master Clock Frequency Master Clock Duty Cycle Filter Characteristics High Rate Filter Output Word Rate OWRS = 0 OWRS = 1 Input/Output Characteristics High-Level Output Voltage Iout = -5.0 mA VOH (VD+) - 1.0 - - V Low-Level Output Voltage Iout = 5.0 mA VOL - - 0.4 V Iin - 1 10 A 3-State Leakage Current IOZ - - 10 A Digital Output Pin Capacitance Cout - 9 - pF Input Leakage Current (Note 5) Notes: 4. All measurements performed under static conditions. 5. DS635F2 For OWRS and GAIN pins, input leakage current is 30 A (Max). 5 CS5451A SWITCHING CHARACTERISTICS * * * * Min/Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = VD+ = 3 V 10%; VA- = -2 V 10%; AGND = DGND = 0 V. All voltages with respect to 0 V. Logic Levels: Logic 0 = 0 V, Logic 1 = VD+ Symbol Min Typ Max Unit Rise Times (Note 6) Parameter Any Digital Input (except XIN) XIN only Any Digital Output trise - 50 1.0 10 - s ns ns Fall Times (Note 6) Any Digital Input (except XIN) XIN only Any Digital Output tfall - 50 1.0 10 - s ns ns SCLK SCLK - 500 1000 - kHz kHz t1 t2 - 0.5 0.5 - SCLK SCLK t3 - - 50 ns t4 - 0.5 - SCLK Serial Port Timing Serial Clock Frequency (Note 7) OWRS = "0" OWRS = "1" Serial Clock (Note 7 and 8) Pulse Width High Pulse Width Low SCLK falling to New Data Bit FSO Falling to SCLK Rising Delay (Note 7 & 8) FSO Pulse Width (Note 7 & 8) t5 - 1 - SCLK (Note 9) t6 - - 50 ns t7 - - 50 ns SE Rising to Output Enabled SE Falling to Output in Tri-state Notes: 6. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF. 7. 8. 9. Device parameters are specified with XIN = 4.096 MHz. Device parameters are specified with OWRS = 1. After SE is asserted, the states of SDO and SCLK are FSO is undefined. MSB(V1) SDO MSB(V1) - 1 t3 t1 LSB(I3) t2 SCLK t4 FSO t5 t7 SE t6 Figure 1. Serial Port Timing 6 DS635F2 CS5451A ABSOLUTE MAXIMUM RATINGS WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog Negative Analog VD+ VA+ VA- -0.3 -0.3 -2.5 - +3.5 +3.5 -0.3 V V V Input Current, Any Pin Except Supplies (Note 10 and 11) IIN - - 10 mA IOUT - - 25 mA (Note 12) PDN - - 500 mW Analog Input Voltage All Analog Pins VINA (VA-) - 0.3 - (VA+) + 0.3 V Digital Input Voltage All Digital Pins VIND -0.3 - (VD+) + 0.3 V Ambient Operating Temperature TA -40 - 85 C Storage Temperature Tstg -65 - 150 C Output Current Power Dissipation Notes: 10. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins. 11. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 12. Total power dissipation, including all input currents and output currents. DS635F2 7 CS5451A 3. THEORY OF OPERATION The CS5451A is a six-channel analog-to-digital converter (ADC) followed by a serial interface that allows communication with a target device. The analog inputs are structured for 3-phase power meter applications, with three dedicated voltage and current channels. Figure 2 illustrates the CS5451A typical inputs and power supply connections. The voltage-sensing element introduces a voltage waveform on the voltage channel inputs VIN(1-3) and is subject to a fixed 1x gain amplifier. A fourth-order delta-sigma modulator samples the amplified signal for digitization. Simultaneously, the current-sensing element introduces a voltage waveform on the current channel input IIN(1-3) and is subject to two selectable gains of the programmable gain amplifier (PGA). The amplified signal is sampled by a fourth-order delta-sigma modulator for digitization. Both converters sample at a rate of XIN/8, the over-sampling provides a wide dynamic range and simplified anti-alias filter design. The decimating digital filters on all channels are Sinc3 filters. The single bit data is passed to the low-pass decimation filter and output at a fixed word rate. The decimation rate is selectable for two output word rates. The 16-bit output word is then transmitted via a master serial data port. The six-channel data is multiplexed on the serial data output and is preceded by a frame sync signal. +3 V VA+ VD+ REFIN Optional External Reference V 1.2 V REFOUT VIN1+, VIN2+, or VIN3+ + PHASE VIN1-, VIN2-, or VIN3- IIN1+, IIN2+, or IIN3+ I PHASE NOTE: Current input channels actually measure voltage. IIN1-, IIN2-, or IIN3- AGND VA- DGND -2 V Figure 2. Typical Connection Diagram 8 DS635F2 CS5451A 4. 4.1 FUNCTIONAL DESCRIPTION Analog Inputs The CS5451A is equipped with six fully differential input channels. The inputs VIN(1-3) and IIN(1-3) are designated as the voltage and current channel inputs, respectively. The full-scale differential input voltage for the current and voltage channel is 800 mVP (gain = 1x). 4.1.1 Voltage Channel 800mV P ----------------- 565.69mVRMS 2 which is approximately 70.7% of maximum peak voltage. Current Channel The output of the current sense resistor or transformer is connected to the IIN(1-3)+ and IIN(1-3)- input pins of the CS5451A. To accommodate different current-sensing devices the current channels incorporates a programmable gain amplifier (PGA) that can be set to one of two input ranges. Input pin GAIN (see Table 1) define the PGA's two gain selections and corresponding maximum input signal level. GAIN Maximum Input Range 0 40mV 20x 1 800mV 1x Table 1. Current Channel PGA Setting 4.2 Digital Filters The decimating digital filter samples the modulator bit stream at XIN/8 and produces a fixed output word rate. The digital filters are implemented as sinc3 filters with the following transfer function: 1 - z - DR H ( z ) = ---------------------- 1 - z-1 DS635F2 The output word rate (OWR) is selected by the OWRS pin and defined by Table 2. OWRS DR Output Word Rate 0 256 XIN/2048 1 128 XIN/1024 Table 2. Decimation Filter OWR 4.3 The output of the line voltage resistive divider or transformer is connected to the VIN(1-3)+ and VIN(1-3)- input pins of the CS5451A. The voltage channels are equipped with a 1x fixed gain amplifier. The full-scale signal level that can be applied to the voltage channel is 800 mV. If the input signal is a sine wave the maximum RMS voltage is: 4.1.2 The decimation rate is determined by the exponent DR (see Table 2). Performing Measurements The ADC outputs are transferred in 16-bit, signed (two's complement) data formats. Table 3 defines the relationship between the differential voltage applied to any one of the input channels and the corresponding output code. Note that for the current channels, the state of the GAIN input pin is assumed to driven low such that the PGA gain on the current channels is 1x. If the PGA gain of the current channels is set to 20x, a +40 mV voltage is applied to any pair of IIN(1-3) pins would cause an output code of 32767. Differential Input Voltage (mV) Output Code (hexadecimal) Output Code (decimal) +800 7FFF 32767 0.0122 to 0.0366 0001 1 -0.0122 to 0.0122 0000 0 -0.0122 to -0.0366 FFFF -1 -800 8000 -32768 Notes: Assume PGA gain is set to 1x. Table 3. Differential Input Voltage vs. Output Code 4.4 Serial Interface The CS5451A communicates with a target device via a master serial data output port. Output data is provided on the SDO output synchronous with the SCLK output. A third output, FSO, is a framing signal used to signal the start of output data. These three outputs will be driven as long as the SE (serial enable) input is held high. Otherwise, these outputs will be high-impedance. Data out (SDO) changes as a result of SCLK falling, and always outputs valid data on the rising edge of SCLK. When data is being transferred the SCLK frequency is XIN/8 when OWRS is low or XIN/4 when OWRS is high. 3 9 CS5451A 96 SCLKs SCLK FSO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 SDO [ Low ] Channel 1 ( V ) Channel 1 ( I ) ... ... ... ... ... ... 3 2 1 0 Ch. 2 ( V )... Ch. 2 ( I ) ... Ch. 3 ( V ) ... Ch. 3 ( I ) ... [ Low ] Figure 3. One Data Frame When data is not being transferred SCLK is held low. (see Figure 3.) RESET is activated, all internal registers are set to a default state. The framing signal (FSO) output is normally low. FSO goes high, with a pulse width equal to one SCLK period, when the instantaneous voltage and current data samples are about to be transmitted out of the serial interface (after each A/D conversion cycle). SCLK is not active during FSO high. Upon powering up, the RESET pin must be held low (active) until after the power stabilizes. For 96 SCLK periods after FSO falls, SCLK is active and SDO provides valid output. Six channels of 16-bit data are output, MSB first. Figure 4 illustrates how the voltage and current measurements are output for the three phases. SCLK will then be held low until the next sample period. 4.5 System Initialization A hardware reset is initiated when the RESET pin is forced low with a minimum pulse width of 50 ns. When SCLK 4.6 Voltage Reference The CS5451A is specified for operation with a +1.2 V reference between the VREFIN and AGND pins. The converter includes an internal 1.2 V reference that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. The VREFIN can be used to connect external filtering and/or references. 4.7 Power Supply The low, stable analog power consumption and superior supply rejection of the CS5451A allow for the use of a simple charge-pump negative supply generator. The use of a negative supply alleviates the need for level 96 SCLKs FSO Each data segment is 16 bits long. SDO Channel 1 V Channel 1 I Channel 2 V Channel 3 I Channel 3 V Channel 2 I Figure 4. Serial Port Data Transfer 10 DS635F2 CS5451A shifting of the analog inputs. The CPD pin and capacitor C1 provide the necessary analog supply current as shown in Figure 5. The Schottky diodes D1 and D2 are chosen for their low forward voltages and high-speed capabilities. The capacitor C2 provides the required charge storage and bypassing of the negative supply. The CPD output signal provides the charge pump driver signal. The frequency of the charge pump driver signal is synchronous to XIN. The nominal average frequency is 1 MHz. The level on the VA- pin is fed back internally so that the CPD output will regulate the VA- level to -2/3 of VA+ level. The value of capacitor C1 (see Figure 5) is dependent on the XIN clock frequency. The 39 nF value for C1 was selected for a XIN clock frequency equal to 4.096 MHz. For more information about the operation of this type of charge pump circuit, the reader can refer to Cirrus Logic, Inc.'s application note AN152: Using the DS635F2 CPD AGND 39 nF C1 VA- D2 BAT 85 D1 BAT 85 C2 1 F Figure 5. Generating VA- with a Charge Pump CS5521/24/28, and CS5525/26 Charge Pump Drive for External Loads. 11 CS5451A 5. PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING N D E11 A2 E e b2 SIDE VIEW A A1 END VIEW L SEATING PLANE 1 2 3 TOP VIEW INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0 NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4 MILLIMETERS MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8 MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0 NOM -0.13 1.75 -10.20 7.80 5.30 0.65 0.90 4 NOTE MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8 2,3 1 1 JEDEC #: MO-150 Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 2. 12 DS635F2 CS5451A 6. ORDERING INFORMATION Model CS5451A-IS CS5451A-ISZ (lead free) Temperature Package -40 to +85 C 28-pin SSOP 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5451A-IS 240 C 2 365 Days CS5451A-ISZ (lead free) 260 C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Revision Date Changes A1 JUL 2003 Initial Release PP1 OCT 2003 Initial release for Preliminary Product Information F1 FEB 2005 Update electrical specifications w/ most-current characterization data. F2 AUG 2005 Update electrical specifications w/ most-current characterization data. Added MSL data. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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