CS5451A-ISR - Cirrus Logic, Inc.

http://www.cirrus.com

CS5451A

Six-channel, Delta-sigma Analog-to-digital Converter

Features

• Synchronous Sampling

• On-chip 1.2 V Reference (25 ppm/°C typ.)

• Power Supply Configurations:

- VA+ = +3 V; VA- = -2 V; VD+ = +3 V

- Supply Tolerances: ±10%

• Power Consumption

- 23 mW Typical at VD+ = +3 V

• Simple Four-wire Serial Interface

• Charge pump driver output generates

negative power supply.

• Ground-referenced Bipolar Inputs

Description

The CS5451A is a highly in tegrated delta-sigma (∆Σ) an-

alog-to-digital converter (ADC) developed for the power

measurement industry. The CS5451A combines six ∆Σ

ADCs, decimation filters, and a serial interface on a sin-

gle chip. The CS5451A interfaces directly to a current

transforme r or s hunt to me asur e curren t, an d to a re sis-

tive divider or transformer to measure voltage. The

product features a serial interface for communication

with a microcontroller or DSP. The product is initialized

and fully functional upon reset, and includes a voltage

reference.

ORDERING INFORMATION:

See page 13.

VREFIN

VREFOUT

IIN1+

IIN1-

VIN1+

VIN1-

VIN2+

VIN2-

VIN3+

VIN3-

IIN2+

IIN2-

IIN3+

IIN3-

VA+ VD+

AGND

FSO

SDO

SCLK

Voltage

Reference

Serial

Interface

RESET

Decimation Filter

x1, 20

4th Order ∆Σ Modulator

x1, 20

4th Order ∆Σ Modulator

GAIN

CPD

OWRS

XIN DGND

VA-

Clock Pulse Output

Regulator

AUG ‘05

DS635F2

CS5451A
2DS635F2
TABLE OF CONTENTS
1. PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. THEORY OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2 Digital Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.3 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.4 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.5 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.6 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. PACKAGE DIMENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
6. ORDERING INFORMATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . .13
8. REVISION HISTORY  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
LIST OF FIGURES
Figure 1. Serial Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 2. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 3. One Data Frame  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 4. Serial Port Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 5. Generating VA- with a Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

CS5451A

DS635F2 3

1. PIN DESCRIPTION

Clock Generator

Master Clock Input 25 XIN - External clock signal or oscillator input.

Control Pins and Serial Data I/O

Serial Clock Output 1SCLK - Serial port clock signal that determines the output data rate for SDO pin. Rate of SCLK is

dependent on the XIN frequency and state of OWRS pin.

Serial Data Output 2SDO -Serial port data output pin. Data will be output at a rate defined by SCLK.

Frame Sync 3FSO - Framing signal indicates when data samples are about to be transmitted on the SDO pin.

Serial Port Enable 4SE - When SE is low, the output pins of the serial port are tri-stated.

Current Input Gain 5GAIN - A logic high set s current channel gain to 1, a logic low sets the gain to 20. If no connection

is made to this pin, it will default to logic low level (through internal 200 kΩ resistor to DGND).

Output Word Rate Select 23 OWRS - A logic low sets the output word rate (OWR) to XIN/2048 (Hz). A logic high sets the

OWR to XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low

level (through internal 200 kΩ resistor to DGND).

Reset 24 RESET - Low activates Reset, all internal registers are set to their default states.

Analog Inputs/Outputs

Voltage Reference Input 7VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator.

Voltage Reference Output 8VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magni-

tude of 1.2 V and is referenced to the AGND pin on the converter.

Differential Voltage Input s 11,12

18,17

22,21

VIN3+, VIN3- - Differential analog input pins for the vo ltage channel 3.

VIN2+, VIN2- - Differential analog input pins for the voltage channel 2.

VIN1+, VIN1- - Differential analog input pins for the voltage channel 1.

Differential Current Inputs 13,14

16,15

20,19

IIN3+, IIN3- - Differential analog input pins for the current channel 3.

IIN2+, IIN2- - Differential analog input pins for the current channel 2.

IIN1+, IIN1- - Differential analog input pins for the current channel 1.

Power Supply Connections

Analog Ground 6AGND - Analog ground.

Positive Analog Supply 9VA+ - The positive analog supply. Typical +3 V ±10% relative to AGND.

Negative Analog Supp ly 10 VA- - The negative analog supply. Typical -2 V ±10% relative to AGND.

Charge Pump Drive 26 CPD - Designed to drive external charge pump circuitry that will produce a negative analog sup-

ply (VA-)voltage.

Digital Ground 27 DGND - Digital Ground.

Positive Digital Supply 28 VD+ - The positive digital supply. Typical +3 V ±10% relative to AGND.

IIN2-

VIN2+

IIN2+

RESET

IIN1+

IIN1-

XIN

VIN1-

VIN2-

CPD

DGND

VIN1+

VD+

OWRS

IIN3-

VIN3+

IIN3+

GAIN

VA+

VA -

VREFOUT

VIN3-

FSO

SDO

VREFIN

SCLK

AGND

Differential Current I nput 2

Differential Voltage Input 2

Differential Current I nput 2

Reset

Differential Current I nput 1

Master Clo ck

Differential Voltage Input 1

Differential Voltage Input 2

Charge Pump Drive

Digital Gro und

Differential Voltage Input 1

Digital Supply

Output Word Rate S elect

Differential Current Input 3

Differential Voltage Input 3

Differential Current Input 3

Current Input Gain

Positive Analog Supply

Negative Analog S upply

Serial Port Enable

Reference Output

Differential Voltage Input 3

Frame Sync

Ser ial Data Output

Reference Input

Serial Clock Output

Analo g Ground

CS5451A

4DS635F2

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ANALOG CHARACTERISTICS

• Min/Max characteristics and specifications are guaranteed over all Operating Con ditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = VD+ = 3 V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V; VREFIN = +1.2 V. All voltages with respect to 0 V.

• XIN = 4.096 MHz.

Parameter Symbol Min Typ Max Unit

DC Power Supplies Positive Digital

Positive Analog

Negative Analog

VD+

VA+

VA-

2.7

-2.2

3.0

-2.0

3.3

-1.8

Voltage Reference Input VREF+ - 1.2 - V

Parameter Symbol Min Typ Max Unit

Accuracy (All Channels)

Total Harmonic Distortion THD 74 - - dB

Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB

Common Mode + Signal on Input VA- - VA+ V

Input Sampling Rate - XIN/4 - Hz

Analog Inputs (Note 1)

Differential Input Voltage Range Gain=20

[(IIN+) - (IIN-)] or [(VIN+) - (VIN-)] Gain=1 VIN

VIN -

-80

1.6 -

-mVP-P

VP-P

Bipolar Offset Gain=20

Gain=1 VOS

VOS -

-±11.5

±0.5 ±20

±4.0 mV

Crosstalk (Channel-to-channel) (50, 60 Hz) - -105 - dB

Input Capacitance Gain = 20

Gain = 1 IC

IC -

-20

1pF

Effective Input Impedance Gain=20

Gain=1 EII

EII 50

500 60

600 -

-kΩ

kΩ

Noise (Referred to Input)

0-60 Hz Gain=20

Gain=1

0-1 kHz Gain=20

Gain=1

0-2 kHz Gain=20

Gain=1

2.5

3.75

µVrms

Reference Output

Output Voltage REFOUT 1.15 1.2 1.25 V

Temperature Coefficient - 25 50 ppm/°C

Load Regulation (Output Current 1 µA Source or Sink) ∆VR-610mV

Power Supply Rejection PSRR 60 - - dB

Reference Input

Input Voltage Range VREF+ 1.15 1.2 1.25 V

Input Capacitance - - 10 pF

Input CVF Current - - 1 µA

CS5451A

DS635F2 5

ANALOG CHARACTERISTICS (continued)

Notes: 1. Specifications for Gain = 20 apply only to Current Channels. Voltag e Channels are fixed to Gain = 1

2. All outputs unloaded. All inputs CMOS level.

3. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3 V, AGND = DGND = 0 V, VA- = -2 V (using charge-

pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed on to the VA+ and VD+ pins.

The “+” and “-” input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words

are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this

rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied

at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defi ned as Veq.

PSRR is then (in dB):

DIGITAL CHARACTERISTICS (See Note 4)

• Min/Max characteristics and specifications are guaranteed over all Operating Con ditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = VD+ = 3V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• XIN = 4.096 MHz

Notes: 4. All measurements performed under static conditions.

5. For OWRS and GAIN pins, input leakage current is 30 µA (Max).

Parameter Symbol Min Typ Max Unit

Power Supplies

Power Supply Currents IA+

Typical VA+=VD+=+3V; VA-=-2V ID+ with CPD

ID+ without CPD

PSCA

PSCD

4.0

5.0

1.0

5.3

6.3

1.5

Power Consumption With CPD

(Note 2) Without CPD PC

PC -

-27

23 35

31 mW

Power Supply Rejection (DC)

50, 60 Hz (Note 3) Voltage Channel

50, 60 Hz (Note 3) Current Channel

PSRR

Parameter Symbol Min Typ Max Unit

Master Clock Characteristics

Master Clock Frequency XIN 3 4.096 5 MHz

Master Clock Duty Cycle 40 - 60 %

Filter Characteristics

High Rate Filter Output Word Rate OWRS = 0

OWRS = 1 OWR

OWR -

-XIN/2048

XIN/1024 -

-Hz

Input/Output Characteristics

High-Level Input Voltage VIH 0.6 VD+ - VD+ V

Low-Level Input Voltage VIL 0.0 - 0.8 V

High-Level Output Voltage Iout = -5.0 mA VOH (VD+) - 1.0 - - V

Low-Level Output Voltage Iout = 5.0 mA VOL --0.4V

Input Leakage Current (Note 5) Iin -±1±10µA

3-State Leakage Current IOZ --±10µA

Digital Output Pin Capacitance Cout -9-pF

PSRR 20 106.07

Veq

------------------

⎩⎭

⎨⎬

⎧⎫

log⋅=

CS5451A
6DS635F2
SWITCHING CHARACTERISTICS 
• Min/Max characteristics and specifications are guaranteed over all Operating Con ditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 3 V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V. All voltages with respect to 0 V. 
• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+
Notes: 6. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
7. Device parameters are specified with XIN = 4.096 MHz.
8. Device parameters are specified with OWRS = 1.
9. After SE is asserted, the states of SDO and SCLK are FSO is undefined. 
Parameter Symbol Min  Typ Max Unit
Rise Times Any Digital Input (except XIN)
(Note 6) XIN only
Any Digital Output trise
-
-
-
-
-
50
1.0
10
-
µs
ns
ns
Fall Times Any Digital Input (except XIN)
(Note 6) XIN only
Any Digital Output tfall
-
-
-
-
-
50
1.0
10
-
µs
ns
ns
Serial Port Timing
Serial Clock Frequency OWRS = “0”
(Note 7) OWRS = “1” SCLK
SCLK -
-500
1000 -
-kHz
kHz
Serial Clock Pulse Width High
(Note 7 and 8) Pulse Width Low t1
t2
-
-0.5
0.5 -
-SCLK
SCLK
SCLK falling to New Data Bit t3- - 50 ns
FSO Falling to SCLK Rising Delay (Note 7 & 8) t4-0.5-SCLK
FSO Pulse Width (Note 7 & 8) t5-1-SCLK
SE Rising to Output Enabled (Note 9) t6- - 50 ns
SE Falling to Output in Tri-state t7- - 50 ns
t7
t2
t1
t3
4
t
5
t
MSB(V1) MSB(V1) - 1 LSB(I3)
SE 6
t
SDO
SCLK
FSO
Figure 1.  Serial Port Timing

CS5451A

DS635F2 7

ABSOLUTE MAXIMUM RATINGS

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes: 10. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins.

11. Transient current of up to 100 mA will not cause SCR latch-up. Ma ximum input current for a power supply pi n is

±50 mA.

12. Total power dissipation, including all input currents and output currents.

Parameter Symbol Min Typ Max Unit

DC Power Supplies Positive Digital

Positive Analog

Negative Analog

VD+

VA+

VA-

-0.3

-2.5

+3.5

-0.3

Input Current, Any Pin Except Supplies (Note 10 and 11) IIN --±10mA

Output Current IOUT --±25mA

Power Dissipation (Note 12) PDN - - 500 mW

Analog Input Voltage All Analog Pins VINA (VA-) - 0.3 - (VA+) + 0.3 V

Digital Input Voltage All Digital Pins VIND -0.3 - (VD+) + 0.3 V

Ambient Operating Temperature TA-40 - 85 °C

Storage Temperature Tstg -65 - 150 °C

CS5451A

8DS635F2

3. THEORY OF OPERATION

The CS5451A is a six-channel analog-to-digital convert-

er (ADC) followed by a serial interface that allows com-

munication with a target device. The analog inputs are

structured for 3-phase power meter applications, with

three dedicated voltage and current channels. Figure 2

illustrates the CS5451A typical inputs and power supply

connections.

The voltage-sensing element introduces a voltage

waveform on the voltage channel inputs VIN(1-3)± and

is subject to a fixed 1x gain amplifier. A fourth-order de l-

ta-sigma modulator samples the amplified signal for dig-

itization.

Simultaneously, the current-sensing element introduces

a voltage waveform on the current channel input

IIN(1-3)± and is subject to two selectable gains of the

programmable gain amplifier (PGA). The amplified sig-

nal is sampled by a fourth-order delta-sigma modulator

for digitization. Both converters sample at a rate of

XIN/8, the over-sampling provides a wide dynamic

range and simplified anti-alias filter design.

The decimating digital filters on all channels are Sinc3

filters. The single bit data is passed to the low-pass dec-

imation filter and output at a fixed word rate. The deci-

mation rate is selectable for two output word rates.

The 16-bit output word is then transmitted via a master

serial data port. The six-channel data is multiplexed on

the serial data output and is preceded by a frame sync

signal.

VA+ VD+

VIN1+, VIN2+, or VIN3+

VIN1-, VIN2-, or VIN3-

IIN1+, IIN2+, or IIN3+

IIN1-, IIN2-, or IIN3-

AGND

DGND

REFIN

REFOUT

Optional

External

Reference

PHASE

-2 V

PHASE

VA-

+3 V

1.2 V

NOTE: Current input channels

actually measure voltage.

Figure 2. Typical Connection Diagram

CS5451A

DS635F2 9

4. FUNCTIONAL DESCRIPTION

4.1 Analog Inputs

The CS5451A is eq uipped with six fully differentia l input

channels. The inputs VIN(1-3)± and IIN(1-3)± are des-

ignated as the voltage and current channel inputs, re-

spectively. The full-scale differential input voltage for

the current and voltage channel is ±800 mVP

(gain = 1x).

4.1.1 Voltage Channel

The output of the line voltage resistive divider or trans-

former is connec ted to the VIN(1-3)+ and VIN(1-3)- in-

put pins of the CS5451A. The voltage channels are

equipped with a 1x fixed gain amplifier. The full-scale

signal level that can be app lied to the voltage chann el is

±800 mV. If the input signal is a sine wave the maximum

RMS voltage is:

which is approximately 70.7% of maximum peak volt-

age.

4.1.2 Current Channel

The output of the current sense resistor or transformer

is connected to the IIN( 1-3)+ and IIN(1-3)- input p ins of

the CS5451A. To acco mmodat e differen t current- sens-

ing devices the current channels incorporates a pro-

grammable gain amplifier (PGA) that can be set to one

of two input ranges. Input pin GAIN (see Table 1) define

the PGA’s two gain selections and corresponding max-

imum input signal level.

4.2 Digital Filters

The decimating digital filter samples the modulator bit

stream at XIN/8 and produces a fixed output word rate.

The digital filters are implemented as sinc3 filters with

the following transfer function:

The decimation rate is determined by the exponent DR

(see Table 2).

The output w ord rate (OWR) is selected by the OW RS

pin and defined by Table 2.

4.3 Performing Measurements

The ADC outputs are transferr ed in 16-bit, signed (two’s

complement) data formats. Tab le 3 defines the relation-

ship between the differential voltage applied to any one

of the input channels and the corresponding output

code. Note that for the cu rrent channels, the state o f the

GAIN input pin is assumed to driven low such that the

PGA gain on the current channels is 1 x. If the PGA gain

of the current channels is set to 20x, a +40 mV voltage

is applied to any pair of IIN(1- 3)± pins would cause an

output code of 32767.

Table 3. Differential Input Voltage vs. Output Code

4.4 Serial Interface

The CS5451A communicates with a target device via a

master serial data output port. Output data is provided

on the SDO output synchronous with the SCLK output.

A third output, FSO, is a framing signal used to signal

the start of output data. These three outputs will be driv-

en as long as the SE (serial enable) input is held high.

Otherwise, these outputs will be high-impedance.

Data out (SDO) changes as a result of SCLK falling, and

always outputs valid data on the rising edge of SCLK.

When data is being transferred the SCLK frequency is

XIN/8 when OWRS is low or XIN/4 when OWRS is high.

GAIN Maximum Input Range

0 ±40mV 20x

1 ±800mV 1x

Table 1. Current Channel PGA Setting

800mVP

----------------- 565.69mVRMS

≅

Hz() 1z

DR–

–

1–

–

----------------------

⎝⎠

⎜⎟

⎛⎞

OWRS DR Output Word Rate

0 256 XIN/2048

1 128 XIN/1024

Table 2. Decimatio n Filt er OWR

Differential Input

Voltage (mV) Output Code

(hexadecimal) Output Code

(decimal)

+800 7FFF 32767

0.0122 to 0.0366 0001 1

-0.0122 to 0.0122 0000 0

-0.0122 to -0.0366 FFFF -1

-800 8000 -32768

Notes: Assume PGA gain is set to 1x.

CS5451A

10 DS635F2

When data is not being transferred SCLK is held low.

(see Figure 3.)

The framing signal (FSO) output is normally low. FSO

goes high, with a pulse width e qual to one SCLK period,

when the instantaneous voltage and current data sam-

ples are about to be transmitted out of the serial inter-

face (after each A/D conversion cycle). SCLK is not

active during FSO high.

For 96 SCLK periods after FSO falls, SCLK is active and

SDO provides valid output. Six channels of 16-bit data

are output, MSB first. Figure 4 illustrates how the volt-

age and current measurements are output for the three

phases. SCLK will then be held low until the next sam-

ple period.

4.5 System Initialization

A hardware reset is initiated when the RESET pin is

forced low with a minimum pulse width of 50 ns. When

RESET is activated, all internal registers are set to a de-

fault state.

Upon powering up, the RESET pin must be held low

(active) until after the power stabilizes.

4.6 Voltage Reference

The CS5451A is specified for operation with a +1.2 V

reference between the VREFIN and AGND pins. The

converter includes an internal 1.2 V reference that can

be used by connecting the VREFOUT pin to the VRE-

FIN pin of the device. The VREFIN can be used to con-

nect external filtering and/or references.

4.7 Power Supply

The low, stable analog power consumption and superior

supply rejection of the CS5451A allow for the use of a

simple charge-pump negative supply generator. The

use of a negative supply alleviates the need for level

SCLK

FSO

SDO 1215 14

13 0123456789

1011 15

14 13 12 11 10 9 8 7 654321

Channel 1 ( I )

Channel 1 ( V )

01514 . . .

Ch. 2 ( V ) Ch. 2 ( I ) Ch. 3 ( V ) Ch. 3 ( I )

... ... ...

. . .

[ Low ] [ Low ]

. . .

012

96 SCLKs

Figure 3. One Data Frame

SCLK

FSO

SDO Channel 1 V

Channel 2 I

Channel 3 I

Channel 2 V

Channel 3 V

Channel 1 I

Each data segment

is 16 bits long.

96 SCLKs

Figure 4. Serial Port Data Transfer

CS5451A

DS635F2 11

shifting of the analog inputs. The CPD p in and capacitor

C1 provide the necessary analog supply current as

shown in Figure 5. The Schottky diodes D1 and D2 are

chosen for their low forward voltages and high-speed

capabilities. The capacitor C2 provides the required

charge storage and bypassing of the negative supply.

The CPD output signal provides the charge pum p driver

signal. The frequency of the charge pump driver signal

is synchronous to XIN. The nominal average frequency

is 1 MHz. The level on the VA- p in is fed ba ck inter nally

so that the CPD output will regulate the VA- level to -2/3

of VA+ level.

The value of capacitor C1 (see Figure 5) is dependent

on the XIN clock frequency. The 39 nF value for C1 was

selected for a XIN clock frequency equ al to 4.09 6 MHz.

For more informa tio n ab out the op er ation of this type of

charge pump circuit, the re ad er can refer to Cirrus Log-

ic, Inc.’s application note AN152: Using the CS5521/24/28, an d CS55 25/26 Charge Pump Drive for

External Loads.

AGND

BAT 85

39 nF

CPD

VA-

BAT 85 1µF

Figure 5. Generating VA- with a Charge Pump

CS5451A

12 DS635F2

5. PACKAGE DIMENSIONS

Notes: 1. “D” and “E1” are reference datums and do not included mo ld flash or protrusions, but do include mold mismatch

and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in

excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more

than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.084 -- -- 2.13

A1 0.002 0.006 0.010 0.05 0.13 0.25

A2 0.064 0.069 0.074 1.62 1.75 1.88

b 0.009 -- 0.015 0.22 -- 0.38 2,3

D 0.390 0.4015 0.413 9.90 10.20 10.50 1

E 0.291 0.307 0.323 7.40 7.80 8.20

E1 0.197 0.209 0.220 5.00 5.30 5.60 1

e 0.022 0.026 0.030 0.55 0.65 0.75

L 0.025 0.0354 0.041 0.63 0.90 1.03

∝0° 4° 8° 0° 4° 8°

JEDEC #: MO-150

28L SSOP PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

∝

CS5451A

DS635F2 13

6. ORDERING INFORMATION

7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

8. REVISION HISTORY

Model Temperature Package

CS5451A-IS -40 to +85 °C 28-pin SSOP

CS5451A-ISZ (lead free)

Model Number Peak Reflow Temp MSL Rating* Max Floor Life

CS5451A-IS 240 °C 2 365 Days

CS5451A-ISZ (lead free) 260 °C 3 7 Days

Revision Date Changes

A1 JUL 2003 Initial Release

PP1 OCT 2003 Initial release for Preliminary Product Information

F1 FEB 2005 Update electrical specifications w/ most-current characterization data.

F2 AUG 2005 Update electrical specifications w/ most-current characterization data. Added

MSL data.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.com

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Cirrus Logic, Inc. and its sub sidiarie s (“Cirrus”) be lieve that the informatio n containe d in this d ocument is accu rate and re liable. However, the information is subject

to change wi tho ut no ti c e an d i s pr ovi de d “A S I S” wi t hout war ra nty of an y ki nd ( exp res s o r imp li ed) . Cus tomer s are a dvi sed t o o btain the latest version of relevant

information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms an d conditions of sale

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