LMH6525, LMH6526 www.ti.com SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 LMH6525/LMH6526 Four-Channel Laser Diode Driver with Dual Output Check for Samples: LMH6525, LMH6526 FEATURES 1 * 23 * * * * * * * * * Fast Switching: Rise and Fall Times: 0.6/1.0 ns. Low Voltage Differential Signaling (LVDS) Channels Enable Interface for the Fast Switching Lines Low Output Current Noise: 0.24 nA/Hz Dual Output: Selectable by SELA/B Pin (Active HIGH) - SELA = LMH6526 SEB = LMH6525 Four Independent Current Channels - Gain of 300, 300 mA Write Channel - Gain of 150, 150 mA Low-Noise Read Channel - Two Gain of 150, 150 mA Write Channels - 600 mA Minimum Combined Output Current Integrated AC Coupled HFM Oscillator - Selectable Frequency and Amplitude Setting - By External Resistors - 200 MHz to 600 MHz Frequency Range - Amplitude to 100 mA Peak-to-Peak Modulation Complete Shutdown by ENABLE Pin 5V Single-Supply Operation Logic inputs TTL and CMOS compatible Space Saving Package (OFN) * * LMH6525 has Differential Enable Oscillator Inputs LMH6526 has Single Ended Enable Oscillator Inputs APPLICATIONS * * * Combination DVD/CD Recordable and Rewritable Drives DVD Camcorders DVD Recorders DESCRIPTION The LMHTM6525/6526 is a laser diode driver for use in combination DVD/CD recordable and rewritable systems. The part contains two high-current outputs for reading and writing the DVD (650 nm) and CD (780 nm) lasers. Functionality includes read, write and erase through four separate switched current channels. The channel currents are summed together at the selected output to generate multilevel waveforms for reading, writing and erasing of optical discs. The LVDS interface delivers DVD write speeds of 16x and higher while minimizing noise and crosstalk. The LMH6525/6526 is optimized for both speed and power consumption to meet the demands of next generation systems. The part features a 150 mA read channel plus one 300 mA and two 150 mA write channels, which can be summed to allow a total output current of 600 mA or greater. The channel currents are set through four independent current inputs. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LMH is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005-2013, Texas Instruments Incorporated LMH6525, LMH6526 SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 www.ti.com Block Diagrams I4 EN4 EN4B CHANNEL 4 I3 EN3 EN3B CHANNEL 3 LMH6525 OUTPUT A I2 EN2 EN2B IOUTA CHANNEL 2 OUTPUT B IR IOUTB CHANNEL 4 I3 EN3 EN3B CHANNEL 3 I2 EN2 EN2B CHANNEL 2 LMH6526 IR READ CHANNEL ENR I4 EN4 EN4B OUTPUT A IOUTA OUTPUT B IOUTB READ CHANNEL ENR VDD ENOSC VDD VDD RF OSCILLATOR ENOSCB VDD ENOSC RF OSCILLATOR VDD VDD GNDB GNDA SELA RFB RAB RFA RAA ENABLE VDDA GNDB GNDA SELB RAB RFB RAA RFA ENABLE VDDA These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) An on-board High-Frequency Modulator (HFM) oscillator helps reduce low-frequency noise of the laser and is enabled by applying LVDS levels on the ENOSC pins for the LMH6525, while the LMH6526 is enabled by applying an asymmetrical signal on the ENOSC pin. The fully differential oscillator circuit minimizes supply line noise, easing FCC approval of the overall system. The SELA/B pin (active HIGH) selects the output channel and oscillator settings. External resistors determine oscillator frequency and amplitude for each setting. The write and erase channels can be switched on and off through dedicated LVDS interface pins. Absolute Maximum Ratings ESD Tolerance (1) (2) Human Body Model Machine Model (3) 2 KV (4) 200V Supply Voltages V+ - V- 5.5V Differential Input Voltage 5.5V Output Short Circuit to Ground (5) Continuous Input Common Mode Voltage V- to V+ Storage Temperature Range -65C to +150C Junction Temperature (1) (2) (3) (4) (5) (6) (6) +150C If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical Characteristics tables. For testing purposes, ESD was applied using "Human Body Model"; 1.5 k in series with 100 pF. Machine Model, 0 in series with 200 pF. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. The maximum power dissipation is a function of TJ(MAX), JA and TA. The maximum allowable power dissipation at any ambient temperature is PD= (TJ(MAX) -- TA)/ JA. All numbers apply for packages soldered directly onto a PC board.. Operating Ratings Supply Voltage (V+ - V-) 4.5V VS 5.5V Operating Temperature Range (TA) Package Thermal Resistance (1) (2) 2 (1) -40C TA 85C (2) (1) , QFN Package Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. Parametric performance is as indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Applications section for information on temperature de-rating of this device. The maximum power dissipation is a function of TJ(MAX), JA and TA. The maximum allowable power dissipation at any ambient temperature is PD= (TJ(MAX) -- TA)/ JA. All numbers apply for packages soldered directly onto a PC board.. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 LMH6525, LMH6526 www.ti.com SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 Operating Ratings (continued) (JC) 3C/W (JA) (no heatsink) (JA) (no heatsink see (3) 42C/W (3) ) 30.8C/W IINR/3/4 1.5 mA (Max) IIN2 1.0 mA (Max) RFREQ 1000 (Min) RAMP 1000 (Min) FOSC 100-600 MHz AOSC 10-100 mAPP This figure is taken from a thermal modeling result. The test board is a 4 layer FR-4 board measuring 101 mm x 101 mm x 1.6 mm with a 3 x 3 array of thermal vias. The ground plane on the board is 50 mm x 50 mm. Ambient temperature in simulation is 22C, still air. Power dissipation is 1W. Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 Submit Documentation Feedback 3 LMH6525, LMH6526 SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 +5V DC Electrical Characteristics www.ti.com (1) Unless otherwise specified, all limits specified for TJ = 25C, RL = 10. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units LVDS VI Input Voltage Range |VGPD| < 50 mV (4) 0 1.7 2.4 V (4) -100 0 100 mV 25 0 95 115 135 8 20 A VIDTH Input Diff. Threshold |VGPD| < 50 mV VHYST Input Diff. Hysteresis VIDTHH - VIDTHL RIN Input Diff. Impedance IIN Input Current Excluding RIN Current , VCM = 1.25V mV Current Channels RIN Input Resistance all Channels RIN to Ground 580 675 IOS2 Current Offset Channel 2 Channel R,3,4 Off IIN = 0, EN = High 2.1 16 mA IOS,R,3,4 Current Offset Channel R,3,4 All Channels Off IIN = 0, EN = High 1.2 9 mA AIW Current Gain Channel 2 345 386 430 A/A AIR Current Gain Channel Read 135 159 180 A/A AI,3,4 Current Gain Channel 3 and 4 160 182 200 A/A ILIN-R,2,3,4 Output Current Linearity 200 A < IIN < 1000 A; RLOAD = 5 Channels Read, 2,3 and 4 1.7 3 % IOUTW Output Current Channel 2 @ 1 mA input current 285 300 mA IOUTR Output Current Channel Read @ 1 mA input current 140 162 mA IOUT3,4 Output Current Channel 3 and 4 @ 1 mA input current 160 183 mA 475 (5) IOUTTOTAL Total Output Current All Channels VTLO TTL Low Voltage Input (H to L), ENR ENOSC (LMH6526) 1.29 0.8 V VTLO TTL Low Voltage Input (H to L) B-Select (LMH6525) A-Select (LMH6526) 1.40 0.8 V VELO Enable Low Voltage Enable Input (H to L) 1.98 0.8 V VTHI TTL High Voltage Input (L to H), ENR ENOSC (LMH6526) 2 1.27 V VTHI TTL High Voltage Input (L to H) B-Select (LMH6525) A-Select (LMH6526) 2 1.51 V VEHI Enable High Voltage Enable Input (L to H) 2.8 ISpd Supply Current, Power Down Enable = Low 0.003 0.1 mA ISr1 Supply Current, Read Mode, Oscillator Disabled ENOSC = Low; ENOSCB = High I2 = I3 = I4 = IR = 125 A 81.5 100 mA ISr2 Supply Current, Read Mode, Oscillator Enabled ENOSC = High; ENOSCB = Low I2 = I3 = I4 = IR = 125 A RFA = 3.5 k 81.5 100 mA ISwr Supply Current, Write Mode EN2 = EN3 = EN4 = High; I2 = I3 = I4 = IR = 125 A 180 210 mA IS Supply Current All Channels disable, no input current. SELA/B = Low RAA, RAB, RFA, RFB = 33 40 mA (1) (2) (3) (4) (5) 4 600 mA 2.13 V Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. Parametric performance is as indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Applications section for information on temperature de-rating of this device. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. VGPD = ground potential difference voltage between driver and receiver Total input current is 4 mA (all 4 channels equal) and output currents are summed together (see typical performance characteristics). Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 LMH6525, LMH6526 www.ti.com SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 +5V AC ELECTRICAL CHARACTERISTICS Unless otherwise specified, all limits specified for TJ = 25C, IOUT = 40 mA DC and 40 mA pulse, RL = 50. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (1) Typ (2) Max (1) Units tr Write Rise Time IOUT = 40 mA (Read) + 40 mA (10% to 90%) RLOAD = 5 0.6 ns tf Write Fall Time IOUT = 40 mA (Read) + 40 mA (90% to 10%) RLOAD = 5 1.6 ns tr Write Rise Time IOUT = 100 mA (Read) + 100 mA (10% to 90%) RLOAD = 5 0.6 ns tf Write Fall Time IOUT = 100 mA (Read) + 100 mA (90% to 10%) RLOAD = 5 1.0 ns tr Write Rise Time IOUT = 150 mA (Read) + 150 mA (10% to 90%) RLOAD = 5 0.6 ns tf Write Fall Time IOUT = 150 mA (Read) + 150 mA (90% to 10%) RLOAD = 5 1.0 ns OS Output Current Overshoot IOUT = 40 mA (Read) + 40 mA 18 % IN0 Output Current Noise IOUT = 40 mA; RLOAD = 50; f = 50 MHz; ENOSC = Low 0.24 nA/Hz tON IOUT ON Prod. Delay Switched on EN2 and EN2B 3.1 ns tOFF IOUT OFF Prop. Delay Switched on EN2 and EN2B 3.3 ns tdisr Disable Time, Read Channel Switched on ENR 3.5 as Tenr Enable Time, Read Channel Switched on ENR 2.8 ns tdis Disable Time (Shutdown) Enable = High to Low 37 ns ten Enable Time (Shutdown) Enable = Low to High 4.5 s BWC Channel Bandwidth, -3 dB IOUT = 50 mA, All Channels 250 KHz FOSC Oscillator Frequency RF = 3.48 k Range 200 MHz to 600 MHz TDO Disable Time Oscillator LMH6525 5 ns TEO Enable Time Oscillator LMH6525 4 ns TDO Disable Time Oscillator LMH6526 7 ns TEO Enable Time Oscillator LMH6526 4 ns (1) (2) (3) (3) 290 360 430 MHz All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. This is the average between the positive and negative overshoot. Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 Submit Documentation Feedback 5 LMH6525, LMH6526 SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 www.ti.com CONNECTION DIAGRAMS 1 ENOSC IOUTA 2 IOUTA ENOSC 3 NC ENOSCB 4 ENR ENR 5 ENABLE ENABLE 6 VDDA VDDA 7 28-Pin (QFN) Top View GNDA GNDA 28-Pin (QFN) Top View 7 6 5 4 3 2 1 IR 8 28 GNDB I2 9 27 IOUTB IR 8 28 GNDB I3 10 26 VDD I2 9 27 IOUTB I4 11 25 VDD I3 10 RFA 12 24 VDD I4 11 RFB 13 23 NC RFA RAA 14 22 EN4 RFB RAA 14 SELB EN2B EN2 EN3B EN3 EN4B 22 EN4 15 See Package Number NJD0028A 16 17 18 19 20 21 EN3 21 VDD 23 NC EN4B 20 24 13 EN3B 19 12 EN2 18 VDD EN2B 17 VDD 25 SELA 16 26 LMH6526 RAB 15 RAB LMH6525 See Package Number NJD0028A Table 1. Pin Description Pin # Description Remarks 1. Laser driver output channel A 2. LVDS Oscillator Enable pin Internal Oscillator activated if logical input is high 3. LVDS Oscillator Enable pin B (only LMH6525) Internal Oscillator activated if logical input is low 4. Read Channel Enable pin Read Channel active if pin is high 5. Chip Enable pin Chip Enabled if pin is high 6. Supply Voltage A 7. Ground Connection A 8. Read Channel current setting 1 mA input current result in 150 mA output current 9. Channel 2 current setting 1 mA input current result in 300 mA output current 10. Channel 3 current setting 1 mA input current result in 150 mA output current 11. Channel 4 current setting 1 mA input current result in 150 mA output current 12. Oscillator Frequency setting Channel A Set by external resistor to ground 13. Oscillator Frequency setting Channel B Set by external resistor to ground 14. Oscillator Amplitude setting Channel A Set by external resistor to ground 15. Oscillator Amplitude setting Channel B Set by external resistor to ground 16. Channel select B (LMH6525) Channel select A (LMH6526) Channel selected if pin is high 17. LVDS input Channel 2B Channel 2 active if logical input is low 18. LVDS input Channel 2 Channel 2 active if logical input is high 19. LVDS input Channel 3B Channel 3 active if logical input is low 20. LVDS input Channel 3 Channel 3 active if logical input is high 21. LVDS input Channel 4B Channel 4 active if logical input is low 22. LVDS input Channel 4 Channel 4 active if logical input is high 23. NC 24. Supply Voltage 25. Supply Voltage 6 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 LMH6525, LMH6526 www.ti.com SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 Table 1. Pin Description (continued) Pin # Description 26. Supply Voltage 27. Laser driver output channel B 28. Ground Connection B Remarks Truth Tables Table 2. IOUT Control ENABLE ENR EN2 EN3 EN4 IOUT 0 X X X X OFF 1 0 0 0 0 OFF 1 1 0 0 0 AR * IINR 1 1 1 0 0 AR * IINR + A2 * IIN2 1 1 0 1 0 AR * IINR + A3 * IIN3 1 1 0 0 1 AR * IINR + A4 * IIN4 Table 3. Oscillator Control ENABLE ENOSC ENR EN2 EN3 EN 4 OSCILLATOR 0 X X X X X OFF 1 0 X X X X OFF 1 1 X X X X ON NOTE Note: EN2, EN3, EN4 AND ENOSC are LVDS SIGNALS USING THE LMH6525. EN2, EN3 and EN4 are LVDS signals using the LMH6526. Waveforms ENABLE ENR ON EN2B EN2 ON EN3B EN3 ON ON EN4B EN4 ON ON AMPLITUDE SET BY IR AMPLITUDE SET BY I2 IOUTA AMPLITUDE SET BY I3 ON AMPLITUDE SET BY I4 SUMMATION OF I2, I3 and I4 Figure 1. Functional Timing Diagram Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 Submit Documentation Feedback 7 LMH6525, LMH6526 SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 www.ti.com ENABLE ENR IOUTA tdis ten Figure 2. Enable Timing ENABLE ENR IOUTA tenr tdisr Figure 3. Read Timing ENABLE EN2B,3B,4B EN2,3,4 tOFF tON IOUTA tr tf Figure 4. Write Timing ENABLE ENR ENOSC IOUTA TDO TEO Figure 5. Oscillator Timing 8 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 LMH6525, LMH6526 www.ti.com SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 Detailed Block Diagram EN4 100: CLOSED IF HIGH + - EN4B + - I4 500: EN3 100: + - CLOSED IF HIGH EN3B + - I3 500: EN2 CLOSED IF HIGH + 100: - EN2B IOUTA + I2 IOUTB 500: CLOSED IF HIGH ENR IR + 500: CLOSED IF HIGH ENOSC ENOSCB NC at LMH6526 SHUTDOWN CONTROL OSC CONTROL SELB (LMH6525) SELA (LMH6526) RFA RFB RAA RAB ENABLE Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 Submit Documentation Feedback 9 LMH6525, LMH6526 SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 www.ti.com Application Schematic DIGITAL SYSTEM DACs DAC BETWEEN PINS 6 AND 7 5V BETWEEN PINS 26 AND 28 5V DAC 47 PF DAC 100 nF 68 nF 47 PF 3k DIGITAL SYSTEM LOGIC 3k 3k 8 IR 4 ENR LMH6525 LMH6526 VDDA VDD VDD VDD 3k DIGITAL DRIVER 6 24 25 26 DAC ENR IOUTA 9 1 18 EN2 EN2B EN2 EN2B 17 LASER DIODE 10 20 19 EN3 EN3B EN3 EN3B 11 IOUTB 27 22 EN4 EN4B 21 LVDS DRIVERS EN4 EN4B LASER DIODE OSCILLATOR 12 RFA 13 29 GNDB SELB ENABLE GNDA NA for LMH6526 SELA for LMH6526 23 28 ENOSCB NC TAB ENOSC 7 DIGITAL LOGIC RFB 14 R AA 15 RAB 2 ENOSC 3 ENOSCB 16 SELB 5 ENABLE GNDA AND VDDA ARE ANALOG SIGNAL GROUND AND POWER. THEY ARE NOT CONNECTED TO GNDB AND VDD INSIDE THE CHIP FREQUENCY A FREQUENCY B AMPLITUDE A AMPLITUDE B LOWER RESISTANCE = HIGHER FREQUENCY AND AMPLITUDE 10 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 LMH6525, LMH6526 www.ti.com SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 Typical Performance Characteristics (TJ = 25C, V+ = 5V, V- = 0V; Unless Specified). Oscillator Amplitude vs. RA Oscillator Amplitude vs. RA 140 140 120 120 IDC = 150 mA 100 RLOAD = 10: f = 300 MHz 100 AMPLITUDE (mAPP) AMPLITUDE (mAPP) VS = 5V VS = 5V IDC = 150 mA 80 60 RLOAD = 10: VS = 5V f = 300 MHz IDC = 150 mA RLOAD = 5: 40 f = 300 MHz VS = 5V 80 IDC = 150 mA 60 RLOAD = 5: f = 300 MHz 40 20 20 0 0 0 10 20 30 40 50 60 70 0 80 1 2 3 4 RA (k:) 5 6 7 8 9 10 70 80 RA (k:) Figure 6. Figure 7. Oscillator Frequency vs. RF Pulse Response 600 0.5 VS = 5V RLOAD = 5: 0.4 400 OUTPUT (V) FREQUENCY (MHz) 500 300 200 0.3 0.2 VS = 5V RLOAD = 5: 0.1 100 VSTEP = 40 mA VDC = 40 mA 0 0 1 2 3 4 5 6 7 8 10 0 9 20 30 60 Figure 9. Noise vs. Frequency Headroom & Output Current vs. Total Input Current 900 RLOAD = 25: 3.5 OSC = OFF 3 IDC = 40 mA 2.5 2 1.5 1 700 2.1 1.8 HEADROOM VS = 5.0V 500 1.5 400 1.2 300 0.9 VS = 4.5V 200 100 0 0 20 30 40 50 2.4 600 0.5 10 2.7 VS = 5.5V 800 OUTPUT CURRENT (mA) CURRENT NOISE (nA/ Hz) 50 Figure 8. 4 1 40 TIME (ns) RF (k:) HEADROOM (V) 0 0.6 OUTPUT CURRENT 0.3 RL = 5: 0 0 FREQUENCY (MHz) 1 2 3 4 5 6 7 8 TOTAL INPUT CURRENT (mA) Figure 10. Figure 11. Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 Submit Documentation Feedback 11 LMH6525, LMH6526 SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION CIRCUIT DESCRIPTION General & Spec The LMH6525/6526 is a 4-channel-input, dual-output laser driver. The dual outputs are meant to drive two different laser diodes, one for CD reading and writing and one for DVD reading and writing. The part has an oscillator that can be set for both amplitude and frequency. The oscillator has four input pins for setting both the amplitude and frequency by connecting external resistors to ground. The part operates at 5V and is capable to deliver a minimum total output current of 500 mA. INPUTS Current-Setting Inputs The 4 input channels are transconductance-type inputs. This means the output current of the channel is proportional to the current (not voltage) sourced into the input pin. That is why these pins are designated by the letter "I" to indicate the current input nature of the pin. The read channel current-setting pin is "IR", the Channel 2 current-setting pin is "I2" and so on. Using a transconductance-type input eliminates the high-impedance inputs associated with a voltage input amplifier. The lower input impedances of the input nodes lowers the susceptibility of the part to EMI/RFI. The Read Channel (IR) and Channel 3 (I3) and 4 (I4) current-setting inputs have a gain of 150. The Channel 2 input (I2) has a current gain of 300. Sourcing one milliampere into the pins IR, I3 or I4, will result in 150 mA at the output for each Channel, while 1 mA into I2 will result in 300 mA at the output for Channel 2. These currents of 150 mA and 300 mA are the maximum allowable currents per channel. The total allowable output current from all the channels operating together exceeds 500 mA. Channel Enable Inputs Each of the four channels has one (read) or two enable inputs that allow the channel to be turned on or off. The read channel enable (ENR) is a single-ended TTL/CMOS compatible input. A single-ended signal is adequate for this channel because the read channel is generally enabled the entire time the drive is reading or writing. The three write/erase channels need to be operated much faster so these channel enables are LVDS (Low Voltage Differential Signal) inputs. Each channel has two inputs, such as EN2 and EN2B. Following the standard an LVDS output consists of a current source of 3.5 mA, and this current produces across the internal termination resistor of 100 in the LMH6525 or LMH6526 a voltage of 350 mV. The polarity of the current through the resistor can change very quickly thus switching the channel current on or off. The bias level of the LVDS signal is about 1.2V, so the operating levels are 175 mV above and below this bias level. The ENxB inputs act as the not input so if the other input is at logical `1' state and the not input at `0' state the channel is activated. The internal 100 resister provides a proper termination for the LVDS signals, saving space and simplifying layout and assembly. Control Inputs There are two other control inputs (next to the oscillator enable which is covered in the next section). There are the global chip Enable and output select pin SELA or SELB. Setting the Enable pin to a level above 2V will enable the part. This means the supply current raises from sleep mode value to the normal operating values. The SELA or SELB input (TTL/ CMOS levels) controls which output is active. When at logical `1' state the output indicated by it's name is active. The mode of this pin also controls the oscillator circuitry which means that the appropriate setting resistors become active as described in the next section. Oscillator Inputs The oscillator section can be switched on or off by a LVDS signal for the LMH6525 and by a TTL/ CMOS signal for the LMH6526. When switched on the oscillator will modulate the output current. The settings of the frequency and amplitude are done by 4 resistors, two for every channel. RFA and RFB pins set the oscillator frequency for the A and B outputs respectively. The RAA and RAB pins set the oscillator amplitude for the A and B channels respectively. These 4 inputs work by having current drawn out of the pin by a setting resistor or potentiometer. The frequency and amplitude increase by decreasing setting resistor value. There are two charts in the Typical Performance Characteristics section that relates the setting resistor value to the resulting frequency or amplitude. Normally the settings for the frequency and amplitude are done by connecting the pin via a resistor to ground. If needed to program this settings it is possible to connect these RFx and RAx pins via a current limiting resistor to 12 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 LMH6525, LMH6526 www.ti.com SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 the output of an op amp or DAC. When using such a circuitry the output can be held at a negative voltage, which means even if the channel pins RFx and RAx are not selected, current is drawn from the pin. This is only true when the negative voltage has such a value that the internal transistors connected to the pin will conduct. This will influence the settings of the active pins RFx and RAx. Due to this effect it is recommended, when using a negative voltage lower as -0.5V, to disable this voltage simultaneously with the channel. OUTPUT The outputs can source currents in excess of 600 mA. The output pins have been designed to have minimal series inductance in order to minimize current overshoot on fast pulses. The outputs have a saturation voltage of about 1V. The table below shows the typical output saturation Voltages into a 5 load at various supply voltages. Table 4. Output Saturation Supply Voltage (V) Maximum Output (mA) 5 Saturation Voltage (V) 4.5V 700 0.8 5.0V 777 0.89 5.5V 846 1.02 As can be seen, even with a 4.5V supply voltage the part can deliver 700 mA while the saturation voltage is at 0.8V. This means the output voltage of the part can be at maximum 700e-3*5 = 3.5V. With a saturated output voltage (see Figure 12) of 0.8V the voltage on the supply pin of the part is 4.3V. The used supply voltage is 4.5V so there is a supply voltage loss of 0.2V over the supply line resistance, but nevertheless the part can drive laser diodes with a forward voltage up to 3.5V with currents over 500 mA. When operating at 5.5V the part can deliver currents over 800 mA. In this case the output at the anode of the laser diode is 846e-3*5 = 4.23V, combined with the saturated output voltage of 1.02V the supply voltage of the part at the power pin is 5.25V and this means the supply line loss is 0.25V. So at 5.5V supply voltage the part can drive laser diodes with a forward voltage in access of 4V. VSUPPLY SUPPLY LINE RESISTANCE SATURATED OUTPUT VOLTAGE OUTPUT STAGE LASER DIODE LMH65xx Figure 12. Output Configuration Application Hints SUPPLY SEQUENCING As the LMH6525/6526 is fabricated in the CMOS7 process, latch-up concerns are minimal. Be aware that applying a low impedance input to the part when it has no supply voltage will forward bias the ESD diode on the input pin and then source power into the part's VDD pin. If the potential exists for sustained operation with active inputs and no supply voltage, all the active inputs should have series resistors to limit the current into the input pins to levels below a few milliamperes. Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 Submit Documentation Feedback 13 LMH6525, LMH6526 SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 www.ti.com DECOUPLING The LMH6525/6526 has very high output currents changing within a nanosecond. This makes decoupling especially important. High performance, low impedance ceramic capacitors should be located as close as possible to the supply pins. The LMH6525/6526 needs two decoupling capacitors, one for the analog power and ground VDDA, GNDA) and one for the power side supply and ground (3xVDD and GNDB). The high level of output current dictates the power side decoupling capacitor should be 0.1 microfarads minimum. Larger values may improve rise times depending on the layout and trace impedances of the connections. The capacitors should have direct connection across the supply pins on the top layer, preferably with small copper-pour planes. These planes can connect to the bottom side ground and/or power planes with vias but there should be a topside low impedance path with no vias if possible. (see also Figure 15 Decoupling Capacitors). OVERSHOOT As the LMH6525/6526 has fast rise times of less then a nanosecond, any inductance in the output path will cause overshoot. This includes the inductance in the laser diode itself as well as any trace inductance. A series connection of a resistor and a capacitor across the laser diode could be helpful to reduce unwanted overshoot or to reduce the very high peaks caused by the relaxation oscillations of a laser diode when driven from below the knee voltage. But keep always in mind that this causes a slower rise and/ or fall time. Typical values are 10 and 100 pF. The actual values required depend on the laser diode used and the circuit layout and should be determined empirically. THERMAL General The LMH6525/6526 is a very high current output device. This means that the device must have adequate heatsinking to prevent the die from reaching its absolute maximum rating of 150C. The primary way heat is removed from the LMH6525/6526 is through the Die Attach Pad, the large center pad on the bottomside of the device. Heat is also carried out of the die through the bond wires to the traces. The outputs and the VDD pads of the device have double bond wires on this device so they will conduct about twice as much heat to the pad. In any event, the heat able to be transferred out the bond wires is far less than that which can be conducted out of the die attach pad. Heat can also be removed from the top of the part but the plastic encapsulation has worse thermal conductivity then copper. This means a heat sink on top of the part is less effective than the same copper area on the circuit board that is thermally attached to the Die Attach Pad. PBC Heatsinks In order to remove the heat from the die attach pad there must be a good thermal path to large copper pours on the circuit board. If the part is mounted on a dual-layer board the simplest method is to use 6 or 8 vias under the die attach pad to connect the pad thermally (as well as electrically, of course) to the bottomside of the circuit board. The vias can then conduct heat to a copper pour area with a size as large as possible. Please see application note AN-1187 (Literature Number SNOA401) for guidelines about these vias and QFN packaging in general. Derating It is essential to keep the LMH6525/6526 die under 150C. This means that if there is inadequate heat sinking the part may overheat at maximum load while at maximum operating ambient of 85C. How much power (current) the part can deliver to the load at elevated ambient temperatures is purely dependent on the amount of heat sinking the part is provided with. LAYOUT Inputs Critical inputs are the LVDS lines. These are two coupled lines of a certain impedance, mostly 100. For some reason those lines could have another value but in that case the termination resistance must have the same value. The differential input resistance of the LMH6525 and LMH6526 is 100 and normally the impedance of the incoming transmission line matches that value. When using a flexible flat cable it is important to know the impedance of two parallel wires in that cable. Flex cables can have different pitch distances, but a commonly 14 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 LMH6525, LMH6526 www.ti.com SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 used cable has a pitch of 0.5 mm. When verified by TDR equipment, the measurements show an impedance of about 142. It is possible to calculate the impedance of such a cable when some parameters are known. Needed parameters are the pitch (a) of the wires, the thickness (d) en r (see Figure 13). When Checked under a microscope: the thickness of the wires is 0.3 mm. The pitch is 0.5 mm, while the ;r must be 1 for air. The impedance of two parallel wires is given by this formula, Z = (276/r) * log{(2*a)/d} (1) With the data above filled in this formula the result is: Z = 144 (2) d a Figure 13. Parallel Wires Both the measured and the calculated numbers match very closely. The impedance of the flex cable is a physical parameter so when designing a transmission path using this flex cable, the impedance of the total path must be based on 140. There is another parameter which is the termination resistance inside the LMH6525 or LMH6526 which is 100. When terminating the 140 transmission path with an impedance of 100 a mismatch will occur causing reflections on the transmission line. To solve this problem it is possible to connect directly at the input terminals of the part two resistors of 20 one on every pin to keep it symmetrical. Normally this causes signal loss over the total extra series resistance of 40 when using a voltage source for driving the transmission line. An advantage of a LVDS source is it's current nature. The current of a LVDS output is 3.5 mA and this current produces across a resistor of 140 a voltage of 490 mV, while this voltage across the 100 internal termination resistor of the part remains at 350 mV, which is conform the LVDS standard. With the usage of a series resistance of 40 and the termination resistor of 100 the total termination resistance now matches the line impedance and reflections will be as low as possible. A helpful tool for calculating impedances of transmission lines is the: `Transmission Line Rapidesigner' available from the Texas Instruments Interface Products Group. Application Note AN-905 (Literature Number SNLA035) details the use of this handy software tool. The Read Enable and Enable inputs are slower and much less critical. The Oscillator Enable input is toggled in combination with the write pulse so special attention should be given to this signal to insure it is routed cleanly. It may be desirable to put a termination resistor close to the LMH6526 for the Enable Oscillator line, to achieve the best turn-on and turn-off performance of the oscillator. OUTPUTS In order to achieve the fastest output rise times the layout of the output lines should be short and tight (see Figure 14). It is intended that the Output B trace be routed under the decoupling capacitor and that the ground return for the laser be closely coupled to the output and terminated at the ground side of the decoupling capacitor. Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 Submit Documentation Feedback 15 LMH6525, LMH6526 SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 www.ti.com Figure 14. Laser Connection The capacitance on the output lines should also be reduced as much as possible. As always the loop area of the laser current should be minimized and keep in mind that it is important not to have vias in the current path of the output lines. Via's will introduce some inductance which lead to extra overshoot on the pulse shape. DECOUPLING CAPACITORS As mentioned before, the decoupling capacitors are critical to the performance of the part. The output section above mentioned that the power-side decoupling capacitor should be as close as possible to the VDD and GND pins and that the B output should pass under the decoupling capacitor. Similarly the analog-side decoupling capacitor should be as close as possible to the VDDA and GNDA pins. Figure 15 shows a layout where the analog (VDDA and GNDA) decoupling cap C1 is placed next to pins 6 and 7. (Note the layout is rotated 90 degrees from the last figure.) The ground extends into a plane that should connect to the oscillator amplitude and current setting resistors. C2 is the power-side decoupling capacitor and it can be seen placed as close to the VDD and GNDB pins as possible while straddling the B output trace. This layout has also provided for a second power decoupling capacitor C3 that connects from VDD to a different GND copper pour. It must be noted that the two ground planes extending from C2 and C3 must be tied together. This will be shown in the thermal section below. Bear in mind that the closeness of the parts to the LMH6525/6526 may be dictated by manufacturing rework considerations such that the LMH6525/6526 can be de-soldered with a hot-air rework station without the need to remove the capacitors. The relevant manufacturing organization can provide guidelines for this minimum spacing. 16 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 LMH6525, LMH6526 www.ti.com SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 Figure 15. Decoupling Capacitors OSCILLATOR RESISTORS The resistors and/or potentiometers used to set oscillator frequency or amplitude should be as close to the part as possible. If the grounds are split when using a single-sided flex circuit, it is essential that these resistors and potentiometers share the same ground as the GNDA pin and decoupling capacitor. THERMAL As mentioned previously, the primary way to get heat out of the QFN package is by the large Die Attach Pad at the center of the part's underside. On two-layer circuits this can be done with vias. On single-sided circuits the pad should connect with a copper pour to either the GND pin or, if a better thermal path can be achieved, with the VDD pins. Be aware that the unused pins on the part can also be used to connect a copper pour area to the Die Attach Pad. Figure 16 Heat Sinking (with the same orientation as the first layout example) shows using the unused pin to provide a thermal path to copper pour heat sinks. In this layout the analog ground has been separated from the power ground so pin 7 is not connected to the Die Attach Paddle even though it would help remove heat from the part. The above layout is based on a single-sided circuit board. If a dual-sided circuit board was used there would also be vias on the Die Attach Pad that would conduct heat to a copper plane on the bottom side of the board. Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 Submit Documentation Feedback 17 LMH6525, LMH6526 SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 www.ti.com Figure 16. Heat Sinking 18 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 LMH6525, LMH6526 www.ti.com SNOSAF1B - JUNE 2005 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision A (March 2013) to Revision B * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 18 Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LMH6525 LMH6526 Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMH6525SP/NOPB ACTIVE UQFN NJD 28 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L6525SP LMH6526SP/NOPB ACTIVE UQFN NJD 28 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L6526SP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6525SP/NOPB UQFN NJD 28 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 LMH6526SP/NOPB UQFN NJD 28 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6525SP/NOPB UQFN NJD 28 1000 210.0 185.0 35.0 LMH6526SP/NOPB UQFN NJD 28 1000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NJD0028A SPA28A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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